1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> 10 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 11 */ 12 13 #include <linux/err.h> 14 #include <linux/bug.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/compiler.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/log2.h> 22 #include <linux/io.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/slab.h> 25 #include <linux/platform_device.h> 26 #include <linux/mutex.h> 27 #include <linux/acpi.h> 28 #include <linux/seq_file.h> 29 #include <linux/interrupt.h> 30 #include <linux/list.h> 31 #include <linux/bitops.h> 32 #include <linux/pinctrl/pinconf.h> 33 #include <linux/pinctrl/pinconf-generic.h> 34 35 #include "core.h" 36 #include "pinctrl-utils.h" 37 #include "pinctrl-amd.h" 38 39 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 40 { 41 unsigned long flags; 42 u32 pin_reg; 43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 44 45 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 46 pin_reg = readl(gpio_dev->base + offset * 4); 47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 48 49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 50 return GPIO_LINE_DIRECTION_OUT; 51 52 return GPIO_LINE_DIRECTION_IN; 53 } 54 55 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 56 { 57 unsigned long flags; 58 u32 pin_reg; 59 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 60 61 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 62 pin_reg = readl(gpio_dev->base + offset * 4); 63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 64 writel(pin_reg, gpio_dev->base + offset * 4); 65 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 66 67 return 0; 68 } 69 70 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 71 int value) 72 { 73 u32 pin_reg; 74 unsigned long flags; 75 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 76 77 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 78 pin_reg = readl(gpio_dev->base + offset * 4); 79 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 80 if (value) 81 pin_reg |= BIT(OUTPUT_VALUE_OFF); 82 else 83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 84 writel(pin_reg, gpio_dev->base + offset * 4); 85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 86 87 return 0; 88 } 89 90 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 91 { 92 u32 pin_reg; 93 unsigned long flags; 94 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 95 96 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 97 pin_reg = readl(gpio_dev->base + offset * 4); 98 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 99 100 return !!(pin_reg & BIT(PIN_STS_OFF)); 101 } 102 103 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 104 { 105 u32 pin_reg; 106 unsigned long flags; 107 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 108 109 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 110 pin_reg = readl(gpio_dev->base + offset * 4); 111 if (value) 112 pin_reg |= BIT(OUTPUT_VALUE_OFF); 113 else 114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 115 writel(pin_reg, gpio_dev->base + offset * 4); 116 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 117 } 118 119 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 120 unsigned debounce) 121 { 122 u32 time; 123 u32 pin_reg; 124 int ret = 0; 125 unsigned long flags; 126 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 127 128 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 129 pin_reg = readl(gpio_dev->base + offset * 4); 130 131 if (debounce) { 132 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 133 pin_reg &= ~DB_TMR_OUT_MASK; 134 /* 135 Debounce Debounce Timer Max 136 TmrLarge TmrOutUnit Unit Debounce 137 Time 138 0 0 61 usec (2 RtcClk) 976 usec 139 0 1 244 usec (8 RtcClk) 3.9 msec 140 1 0 15.6 msec (512 RtcClk) 250 msec 141 1 1 62.5 msec (2048 RtcClk) 1 sec 142 */ 143 144 if (debounce < 61) { 145 pin_reg |= 1; 146 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 147 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 148 } else if (debounce < 976) { 149 time = debounce / 61; 150 pin_reg |= time & DB_TMR_OUT_MASK; 151 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 152 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 153 } else if (debounce < 3900) { 154 time = debounce / 244; 155 pin_reg |= time & DB_TMR_OUT_MASK; 156 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 158 } else if (debounce < 250000) { 159 time = debounce / 15625; 160 pin_reg |= time & DB_TMR_OUT_MASK; 161 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 162 pin_reg |= BIT(DB_TMR_LARGE_OFF); 163 } else if (debounce < 1000000) { 164 time = debounce / 62500; 165 pin_reg |= time & DB_TMR_OUT_MASK; 166 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 167 pin_reg |= BIT(DB_TMR_LARGE_OFF); 168 } else { 169 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 170 ret = -EINVAL; 171 } 172 } else { 173 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 174 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 175 pin_reg &= ~DB_TMR_OUT_MASK; 176 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 177 } 178 writel(pin_reg, gpio_dev->base + offset * 4); 179 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 180 181 return ret; 182 } 183 184 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 185 unsigned long config) 186 { 187 u32 debounce; 188 189 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 190 return -ENOTSUPP; 191 192 debounce = pinconf_to_config_argument(config); 193 return amd_gpio_set_debounce(gc, offset, debounce); 194 } 195 196 #ifdef CONFIG_DEBUG_FS 197 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 198 { 199 u32 pin_reg; 200 u32 db_cntrl; 201 unsigned long flags; 202 unsigned int bank, i, pin_num; 203 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 204 205 bool tmr_out_unit; 206 unsigned int time; 207 unsigned int unit; 208 bool tmr_large; 209 210 char *level_trig; 211 char *active_level; 212 char *interrupt_enable; 213 char *interrupt_mask; 214 char *wake_cntrl0; 215 char *wake_cntrl1; 216 char *wake_cntrl2; 217 char *pin_sts; 218 char *pull_up_sel; 219 char *pull_up_enable; 220 char *pull_down_enable; 221 char *output_value; 222 char *output_enable; 223 char debounce_value[40]; 224 char *debounce_enable; 225 226 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 227 seq_printf(s, "GPIO bank%d\t", bank); 228 229 switch (bank) { 230 case 0: 231 i = 0; 232 pin_num = AMD_GPIO_PINS_BANK0; 233 break; 234 case 1: 235 i = 64; 236 pin_num = AMD_GPIO_PINS_BANK1 + i; 237 break; 238 case 2: 239 i = 128; 240 pin_num = AMD_GPIO_PINS_BANK2 + i; 241 break; 242 case 3: 243 i = 192; 244 pin_num = AMD_GPIO_PINS_BANK3 + i; 245 break; 246 default: 247 /* Illegal bank number, ignore */ 248 continue; 249 } 250 for (; i < pin_num; i++) { 251 seq_printf(s, "pin%d\t", i); 252 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 253 pin_reg = readl(gpio_dev->base + i * 4); 254 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 255 256 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 257 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 258 ACTIVE_LEVEL_MASK; 259 interrupt_enable = "interrupt is enabled|"; 260 261 if (level == ACTIVE_LEVEL_HIGH) 262 active_level = "Active high|"; 263 else if (level == ACTIVE_LEVEL_LOW) 264 active_level = "Active low|"; 265 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 266 level == ACTIVE_LEVEL_BOTH) 267 active_level = "Active on both|"; 268 else 269 active_level = "Unknown Active level|"; 270 271 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 272 level_trig = "Level trigger|"; 273 else 274 level_trig = "Edge trigger|"; 275 276 } else { 277 interrupt_enable = 278 "interrupt is disabled|"; 279 active_level = " "; 280 level_trig = " "; 281 } 282 283 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 284 interrupt_mask = 285 "interrupt is unmasked|"; 286 else 287 interrupt_mask = 288 "interrupt is masked|"; 289 290 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 291 wake_cntrl0 = "enable wakeup in S0i3 state|"; 292 else 293 wake_cntrl0 = "disable wakeup in S0i3 state|"; 294 295 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 296 wake_cntrl1 = "enable wakeup in S3 state|"; 297 else 298 wake_cntrl1 = "disable wakeup in S3 state|"; 299 300 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 301 wake_cntrl2 = "enable wakeup in S4/S5 state|"; 302 else 303 wake_cntrl2 = "disable wakeup in S4/S5 state|"; 304 305 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 306 pull_up_enable = "pull-up is enabled|"; 307 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 308 pull_up_sel = "8k pull-up|"; 309 else 310 pull_up_sel = "4k pull-up|"; 311 } else { 312 pull_up_enable = "pull-up is disabled|"; 313 pull_up_sel = " "; 314 } 315 316 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 317 pull_down_enable = "pull-down is enabled|"; 318 else 319 pull_down_enable = "Pull-down is disabled|"; 320 321 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 322 pin_sts = " "; 323 output_enable = "output is enabled|"; 324 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 325 output_value = "output is high|"; 326 else 327 output_value = "output is low|"; 328 } else { 329 output_enable = "output is disabled|"; 330 output_value = " "; 331 332 if (pin_reg & BIT(PIN_STS_OFF)) 333 pin_sts = "input is high|"; 334 else 335 pin_sts = "input is low|"; 336 } 337 338 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 339 if (db_cntrl) { 340 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 341 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 342 time = pin_reg & DB_TMR_OUT_MASK; 343 if (tmr_large) { 344 if (tmr_out_unit) 345 unit = 62500; 346 else 347 unit = 15625; 348 } else { 349 if (tmr_out_unit) 350 unit = 244; 351 else 352 unit = 61; 353 } 354 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 355 debounce_enable = "debouncing filter (high and low) enabled|"; 356 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 357 debounce_enable = "debouncing filter (low) enabled|"; 358 else 359 debounce_enable = "debouncing filter (high) enabled|"; 360 361 snprintf(debounce_value, sizeof(debounce_value), 362 "debouncing timeout is %u (us)|", time * unit); 363 } else { 364 debounce_enable = "debouncing filter disabled|"; 365 snprintf(debounce_value, sizeof(debounce_value), " "); 366 } 367 368 seq_printf(s, "%s %s %s %s %s %s\n" 369 " %s %s %s %s %s %s %s %s %s 0x%x\n", 370 level_trig, active_level, interrupt_enable, 371 interrupt_mask, wake_cntrl0, wake_cntrl1, 372 wake_cntrl2, pin_sts, pull_up_sel, 373 pull_up_enable, pull_down_enable, 374 output_value, output_enable, 375 debounce_enable, debounce_value, pin_reg); 376 } 377 } 378 } 379 #else 380 #define amd_gpio_dbg_show NULL 381 #endif 382 383 static void amd_gpio_irq_enable(struct irq_data *d) 384 { 385 u32 pin_reg; 386 unsigned long flags; 387 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 388 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 389 390 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 391 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 392 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 393 pin_reg |= BIT(INTERRUPT_MASK_OFF); 394 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 395 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 396 } 397 398 static void amd_gpio_irq_disable(struct irq_data *d) 399 { 400 u32 pin_reg; 401 unsigned long flags; 402 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 403 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 404 405 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 406 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 407 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 408 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 409 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 410 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 411 } 412 413 static void amd_gpio_irq_mask(struct irq_data *d) 414 { 415 u32 pin_reg; 416 unsigned long flags; 417 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 418 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 419 420 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 421 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 422 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 423 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 424 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 425 } 426 427 static void amd_gpio_irq_unmask(struct irq_data *d) 428 { 429 u32 pin_reg; 430 unsigned long flags; 431 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 432 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 433 434 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 435 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 436 pin_reg |= BIT(INTERRUPT_MASK_OFF); 437 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 438 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 439 } 440 441 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 442 { 443 u32 pin_reg; 444 unsigned long flags; 445 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 446 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 447 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 448 BIT(WAKE_CNTRL_OFF_S4); 449 450 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 451 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 452 453 if (on) 454 pin_reg |= wake_mask; 455 else 456 pin_reg &= ~wake_mask; 457 458 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 459 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 460 461 return 0; 462 } 463 464 static void amd_gpio_irq_eoi(struct irq_data *d) 465 { 466 u32 reg; 467 unsigned long flags; 468 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 469 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 470 471 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 472 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 473 reg |= EOI_MASK; 474 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 475 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 476 } 477 478 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 479 { 480 int ret = 0; 481 u32 pin_reg, pin_reg_irq_en, mask; 482 unsigned long flags; 483 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 484 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 485 486 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 487 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 488 489 switch (type & IRQ_TYPE_SENSE_MASK) { 490 case IRQ_TYPE_EDGE_RISING: 491 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 492 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 493 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 494 irq_set_handler_locked(d, handle_edge_irq); 495 break; 496 497 case IRQ_TYPE_EDGE_FALLING: 498 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 499 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 500 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 501 irq_set_handler_locked(d, handle_edge_irq); 502 break; 503 504 case IRQ_TYPE_EDGE_BOTH: 505 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 506 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 507 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 508 irq_set_handler_locked(d, handle_edge_irq); 509 break; 510 511 case IRQ_TYPE_LEVEL_HIGH: 512 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 513 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 514 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 515 irq_set_handler_locked(d, handle_level_irq); 516 break; 517 518 case IRQ_TYPE_LEVEL_LOW: 519 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 520 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 521 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 522 irq_set_handler_locked(d, handle_level_irq); 523 break; 524 525 case IRQ_TYPE_NONE: 526 break; 527 528 default: 529 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 530 ret = -EINVAL; 531 } 532 533 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 534 /* 535 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 536 * debounce registers of any GPIO will block wake/interrupt status 537 * generation for *all* GPIOs for a length of time that depends on 538 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 539 * INTERRUPT_ENABLE bit will read as 0. 540 * 541 * We temporarily enable irq for the GPIO whose configuration is 542 * changing, and then wait for it to read back as 1 to know when 543 * debounce has settled and then disable the irq again. 544 * We do this polling with the spinlock held to ensure other GPIO 545 * access routines do not read an incorrect value for the irq enable 546 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 547 * spurious irqs, and disable the irq again after polling. 548 */ 549 mask = BIT(INTERRUPT_ENABLE_OFF); 550 pin_reg_irq_en = pin_reg; 551 pin_reg_irq_en |= mask; 552 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 553 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 554 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 555 continue; 556 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 557 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 558 559 return ret; 560 } 561 562 static void amd_irq_ack(struct irq_data *d) 563 { 564 /* 565 * based on HW design,there is no need to ack HW 566 * before handle current irq. But this routine is 567 * necessary for handle_edge_irq 568 */ 569 } 570 571 static struct irq_chip amd_gpio_irqchip = { 572 .name = "amd_gpio", 573 .irq_ack = amd_irq_ack, 574 .irq_enable = amd_gpio_irq_enable, 575 .irq_disable = amd_gpio_irq_disable, 576 .irq_mask = amd_gpio_irq_mask, 577 .irq_unmask = amd_gpio_irq_unmask, 578 .irq_set_wake = amd_gpio_irq_set_wake, 579 .irq_eoi = amd_gpio_irq_eoi, 580 .irq_set_type = amd_gpio_irq_set_type, 581 /* 582 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 583 * also generates an IRQ. We need the IRQ so the irq_handler can clear 584 * the wake event. Otherwise the wake event will never clear and 585 * prevent the system from suspending. 586 */ 587 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, 588 }; 589 590 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 591 592 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 593 { 594 struct amd_gpio *gpio_dev = dev_id; 595 struct gpio_chip *gc = &gpio_dev->gc; 596 irqreturn_t ret = IRQ_NONE; 597 unsigned int i, irqnr; 598 unsigned long flags; 599 u32 __iomem *regs; 600 u32 regval; 601 u64 status, mask; 602 603 /* Read the wake status */ 604 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 605 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 606 status <<= 32; 607 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 608 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 609 610 /* Bit 0-45 contain the relevant status bits */ 611 status &= (1ULL << 46) - 1; 612 regs = gpio_dev->base; 613 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 614 if (!(status & mask)) 615 continue; 616 status &= ~mask; 617 618 /* Each status bit covers four pins */ 619 for (i = 0; i < 4; i++) { 620 regval = readl(regs + i); 621 if (!(regval & PIN_IRQ_PENDING) || 622 !(regval & BIT(INTERRUPT_MASK_OFF))) 623 continue; 624 generic_handle_domain_irq(gc->irq.domain, irqnr + i); 625 626 /* Clear interrupt. 627 * We must read the pin register again, in case the 628 * value was changed while executing 629 * generic_handle_domain_irq() above. 630 * If we didn't find a mapping for the interrupt, 631 * disable it in order to avoid a system hang caused 632 * by an interrupt storm. 633 */ 634 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 635 regval = readl(regs + i); 636 if (irq == 0) { 637 regval &= ~BIT(INTERRUPT_ENABLE_OFF); 638 dev_dbg(&gpio_dev->pdev->dev, 639 "Disabling spurious GPIO IRQ %d\n", 640 irqnr + i); 641 } 642 writel(regval, regs + i); 643 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 644 ret = IRQ_HANDLED; 645 } 646 } 647 648 /* Signal EOI to the GPIO unit */ 649 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 650 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 651 regval |= EOI_MASK; 652 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 653 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 654 655 return ret; 656 } 657 658 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 659 { 660 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 661 662 return gpio_dev->ngroups; 663 } 664 665 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 666 unsigned group) 667 { 668 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 669 670 return gpio_dev->groups[group].name; 671 } 672 673 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 674 unsigned group, 675 const unsigned **pins, 676 unsigned *num_pins) 677 { 678 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 679 680 *pins = gpio_dev->groups[group].pins; 681 *num_pins = gpio_dev->groups[group].npins; 682 return 0; 683 } 684 685 static const struct pinctrl_ops amd_pinctrl_ops = { 686 .get_groups_count = amd_get_groups_count, 687 .get_group_name = amd_get_group_name, 688 .get_group_pins = amd_get_group_pins, 689 #ifdef CONFIG_OF 690 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 691 .dt_free_map = pinctrl_utils_free_map, 692 #endif 693 }; 694 695 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 696 unsigned int pin, 697 unsigned long *config) 698 { 699 u32 pin_reg; 700 unsigned arg; 701 unsigned long flags; 702 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 703 enum pin_config_param param = pinconf_to_config_param(*config); 704 705 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 706 pin_reg = readl(gpio_dev->base + pin*4); 707 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 708 switch (param) { 709 case PIN_CONFIG_INPUT_DEBOUNCE: 710 arg = pin_reg & DB_TMR_OUT_MASK; 711 break; 712 713 case PIN_CONFIG_BIAS_PULL_DOWN: 714 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 715 break; 716 717 case PIN_CONFIG_BIAS_PULL_UP: 718 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 719 break; 720 721 case PIN_CONFIG_DRIVE_STRENGTH: 722 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 723 break; 724 725 default: 726 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 727 param); 728 return -ENOTSUPP; 729 } 730 731 *config = pinconf_to_config_packed(param, arg); 732 733 return 0; 734 } 735 736 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 737 unsigned long *configs, unsigned num_configs) 738 { 739 int i; 740 u32 arg; 741 int ret = 0; 742 u32 pin_reg; 743 unsigned long flags; 744 enum pin_config_param param; 745 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 746 747 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 748 for (i = 0; i < num_configs; i++) { 749 param = pinconf_to_config_param(configs[i]); 750 arg = pinconf_to_config_argument(configs[i]); 751 pin_reg = readl(gpio_dev->base + pin*4); 752 753 switch (param) { 754 case PIN_CONFIG_INPUT_DEBOUNCE: 755 pin_reg &= ~DB_TMR_OUT_MASK; 756 pin_reg |= arg & DB_TMR_OUT_MASK; 757 break; 758 759 case PIN_CONFIG_BIAS_PULL_DOWN: 760 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 761 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 762 break; 763 764 case PIN_CONFIG_BIAS_PULL_UP: 765 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 766 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 767 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 768 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 769 break; 770 771 case PIN_CONFIG_DRIVE_STRENGTH: 772 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 773 << DRV_STRENGTH_SEL_OFF); 774 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 775 << DRV_STRENGTH_SEL_OFF; 776 break; 777 778 default: 779 dev_err(&gpio_dev->pdev->dev, 780 "Invalid config param %04x\n", param); 781 ret = -ENOTSUPP; 782 } 783 784 writel(pin_reg, gpio_dev->base + pin*4); 785 } 786 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 787 788 return ret; 789 } 790 791 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 792 unsigned int group, 793 unsigned long *config) 794 { 795 const unsigned *pins; 796 unsigned npins; 797 int ret; 798 799 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 800 if (ret) 801 return ret; 802 803 if (amd_pinconf_get(pctldev, pins[0], config)) 804 return -ENOTSUPP; 805 806 return 0; 807 } 808 809 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 810 unsigned group, unsigned long *configs, 811 unsigned num_configs) 812 { 813 const unsigned *pins; 814 unsigned npins; 815 int i, ret; 816 817 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 818 if (ret) 819 return ret; 820 for (i = 0; i < npins; i++) { 821 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 822 return -ENOTSUPP; 823 } 824 return 0; 825 } 826 827 static const struct pinconf_ops amd_pinconf_ops = { 828 .pin_config_get = amd_pinconf_get, 829 .pin_config_set = amd_pinconf_set, 830 .pin_config_group_get = amd_pinconf_group_get, 831 .pin_config_group_set = amd_pinconf_group_set, 832 }; 833 834 #ifdef CONFIG_PM_SLEEP 835 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 836 { 837 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 838 839 if (!pd) 840 return false; 841 842 /* 843 * Only restore the pin if it is actually in use by the kernel (or 844 * by userspace). 845 */ 846 if (pd->mux_owner || pd->gpio_owner || 847 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 848 return true; 849 850 return false; 851 } 852 853 static int amd_gpio_suspend(struct device *dev) 854 { 855 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 856 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 857 int i; 858 859 for (i = 0; i < desc->npins; i++) { 860 int pin = desc->pins[i].number; 861 862 if (!amd_gpio_should_save(gpio_dev, pin)) 863 continue; 864 865 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4); 866 } 867 868 return 0; 869 } 870 871 static int amd_gpio_resume(struct device *dev) 872 { 873 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 874 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 875 int i; 876 877 for (i = 0; i < desc->npins; i++) { 878 int pin = desc->pins[i].number; 879 880 if (!amd_gpio_should_save(gpio_dev, pin)) 881 continue; 882 883 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4); 884 } 885 886 return 0; 887 } 888 889 static const struct dev_pm_ops amd_gpio_pm_ops = { 890 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 891 amd_gpio_resume) 892 }; 893 #endif 894 895 static struct pinctrl_desc amd_pinctrl_desc = { 896 .pins = kerncz_pins, 897 .npins = ARRAY_SIZE(kerncz_pins), 898 .pctlops = &amd_pinctrl_ops, 899 .confops = &amd_pinconf_ops, 900 .owner = THIS_MODULE, 901 }; 902 903 static int amd_gpio_probe(struct platform_device *pdev) 904 { 905 int ret = 0; 906 int irq_base; 907 struct resource *res; 908 struct amd_gpio *gpio_dev; 909 struct gpio_irq_chip *girq; 910 911 gpio_dev = devm_kzalloc(&pdev->dev, 912 sizeof(struct amd_gpio), GFP_KERNEL); 913 if (!gpio_dev) 914 return -ENOMEM; 915 916 raw_spin_lock_init(&gpio_dev->lock); 917 918 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 919 if (!res) { 920 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 921 return -EINVAL; 922 } 923 924 gpio_dev->base = devm_ioremap(&pdev->dev, res->start, 925 resource_size(res)); 926 if (!gpio_dev->base) 927 return -ENOMEM; 928 929 irq_base = platform_get_irq(pdev, 0); 930 if (irq_base < 0) 931 return irq_base; 932 933 #ifdef CONFIG_PM_SLEEP 934 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 935 sizeof(*gpio_dev->saved_regs), 936 GFP_KERNEL); 937 if (!gpio_dev->saved_regs) 938 return -ENOMEM; 939 #endif 940 941 gpio_dev->pdev = pdev; 942 gpio_dev->gc.get_direction = amd_gpio_get_direction; 943 gpio_dev->gc.direction_input = amd_gpio_direction_input; 944 gpio_dev->gc.direction_output = amd_gpio_direction_output; 945 gpio_dev->gc.get = amd_gpio_get_value; 946 gpio_dev->gc.set = amd_gpio_set_value; 947 gpio_dev->gc.set_config = amd_gpio_set_config; 948 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 949 950 gpio_dev->gc.base = -1; 951 gpio_dev->gc.label = pdev->name; 952 gpio_dev->gc.owner = THIS_MODULE; 953 gpio_dev->gc.parent = &pdev->dev; 954 gpio_dev->gc.ngpio = resource_size(res) / 4; 955 #if defined(CONFIG_OF_GPIO) 956 gpio_dev->gc.of_node = pdev->dev.of_node; 957 #endif 958 959 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 960 gpio_dev->groups = kerncz_groups; 961 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 962 963 amd_pinctrl_desc.name = dev_name(&pdev->dev); 964 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 965 gpio_dev); 966 if (IS_ERR(gpio_dev->pctrl)) { 967 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 968 return PTR_ERR(gpio_dev->pctrl); 969 } 970 971 girq = &gpio_dev->gc.irq; 972 girq->chip = &amd_gpio_irqchip; 973 /* This will let us handle the parent IRQ in the driver */ 974 girq->parent_handler = NULL; 975 girq->num_parents = 0; 976 girq->parents = NULL; 977 girq->default_type = IRQ_TYPE_NONE; 978 girq->handler = handle_simple_irq; 979 980 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 981 if (ret) 982 return ret; 983 984 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 985 0, 0, gpio_dev->gc.ngpio); 986 if (ret) { 987 dev_err(&pdev->dev, "Failed to add pin range\n"); 988 goto out2; 989 } 990 991 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 992 IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 993 if (ret) 994 goto out2; 995 996 platform_set_drvdata(pdev, gpio_dev); 997 998 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 999 return ret; 1000 1001 out2: 1002 gpiochip_remove(&gpio_dev->gc); 1003 1004 return ret; 1005 } 1006 1007 static int amd_gpio_remove(struct platform_device *pdev) 1008 { 1009 struct amd_gpio *gpio_dev; 1010 1011 gpio_dev = platform_get_drvdata(pdev); 1012 1013 gpiochip_remove(&gpio_dev->gc); 1014 1015 return 0; 1016 } 1017 1018 #ifdef CONFIG_ACPI 1019 static const struct acpi_device_id amd_gpio_acpi_match[] = { 1020 { "AMD0030", 0 }, 1021 { "AMDI0030", 0}, 1022 { "AMDI0031", 0}, 1023 { }, 1024 }; 1025 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1026 #endif 1027 1028 static struct platform_driver amd_gpio_driver = { 1029 .driver = { 1030 .name = "amd_gpio", 1031 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1032 #ifdef CONFIG_PM_SLEEP 1033 .pm = &amd_gpio_pm_ops, 1034 #endif 1035 }, 1036 .probe = amd_gpio_probe, 1037 .remove = amd_gpio_remove, 1038 }; 1039 1040 module_platform_driver(amd_gpio_driver); 1041 1042 MODULE_LICENSE("GPL v2"); 1043 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1044 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1045