1 /* 2 * GPIO driver for AMD 3 * 4 * Copyright (c) 2014,2015 AMD Corporation. 5 * Authors: Ken Xue <Ken.Xue@amd.com> 6 * Wu, Jeff <Jeff.Wu@amd.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 */ 12 13 #include <linux/err.h> 14 #include <linux/bug.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/compiler.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/log2.h> 22 #include <linux/io.h> 23 #include <linux/gpio.h> 24 #include <linux/slab.h> 25 #include <linux/platform_device.h> 26 #include <linux/mutex.h> 27 #include <linux/acpi.h> 28 #include <linux/seq_file.h> 29 #include <linux/interrupt.h> 30 #include <linux/list.h> 31 #include <linux/bitops.h> 32 #include <linux/pinctrl/pinconf.h> 33 #include <linux/pinctrl/pinconf-generic.h> 34 35 #include "pinctrl-utils.h" 36 #include "pinctrl-amd.h" 37 38 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 39 { 40 unsigned long flags; 41 u32 pin_reg; 42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 43 44 spin_lock_irqsave(&gpio_dev->lock, flags); 45 pin_reg = readl(gpio_dev->base + offset * 4); 46 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 47 writel(pin_reg, gpio_dev->base + offset * 4); 48 spin_unlock_irqrestore(&gpio_dev->lock, flags); 49 50 return 0; 51 } 52 53 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 54 int value) 55 { 56 u32 pin_reg; 57 unsigned long flags; 58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 59 60 spin_lock_irqsave(&gpio_dev->lock, flags); 61 pin_reg = readl(gpio_dev->base + offset * 4); 62 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 63 if (value) 64 pin_reg |= BIT(OUTPUT_VALUE_OFF); 65 else 66 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 67 writel(pin_reg, gpio_dev->base + offset * 4); 68 spin_unlock_irqrestore(&gpio_dev->lock, flags); 69 70 return 0; 71 } 72 73 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 74 { 75 u32 pin_reg; 76 unsigned long flags; 77 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 78 79 spin_lock_irqsave(&gpio_dev->lock, flags); 80 pin_reg = readl(gpio_dev->base + offset * 4); 81 spin_unlock_irqrestore(&gpio_dev->lock, flags); 82 83 return !!(pin_reg & BIT(PIN_STS_OFF)); 84 } 85 86 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 87 { 88 u32 pin_reg; 89 unsigned long flags; 90 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 91 92 spin_lock_irqsave(&gpio_dev->lock, flags); 93 pin_reg = readl(gpio_dev->base + offset * 4); 94 if (value) 95 pin_reg |= BIT(OUTPUT_VALUE_OFF); 96 else 97 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 98 writel(pin_reg, gpio_dev->base + offset * 4); 99 spin_unlock_irqrestore(&gpio_dev->lock, flags); 100 } 101 102 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 103 unsigned debounce) 104 { 105 u32 time; 106 u32 pin_reg; 107 int ret = 0; 108 unsigned long flags; 109 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 110 111 spin_lock_irqsave(&gpio_dev->lock, flags); 112 pin_reg = readl(gpio_dev->base + offset * 4); 113 114 if (debounce) { 115 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 116 pin_reg &= ~DB_TMR_OUT_MASK; 117 /* 118 Debounce Debounce Timer Max 119 TmrLarge TmrOutUnit Unit Debounce 120 Time 121 0 0 61 usec (2 RtcClk) 976 usec 122 0 1 244 usec (8 RtcClk) 3.9 msec 123 1 0 15.6 msec (512 RtcClk) 250 msec 124 1 1 62.5 msec (2048 RtcClk) 1 sec 125 */ 126 127 if (debounce < 61) { 128 pin_reg |= 1; 129 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 130 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 131 } else if (debounce < 976) { 132 time = debounce / 61; 133 pin_reg |= time & DB_TMR_OUT_MASK; 134 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 135 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 136 } else if (debounce < 3900) { 137 time = debounce / 244; 138 pin_reg |= time & DB_TMR_OUT_MASK; 139 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 140 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 141 } else if (debounce < 250000) { 142 time = debounce / 15600; 143 pin_reg |= time & DB_TMR_OUT_MASK; 144 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 145 pin_reg |= BIT(DB_TMR_LARGE_OFF); 146 } else if (debounce < 1000000) { 147 time = debounce / 62500; 148 pin_reg |= time & DB_TMR_OUT_MASK; 149 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 150 pin_reg |= BIT(DB_TMR_LARGE_OFF); 151 } else { 152 pin_reg &= ~DB_CNTRl_MASK; 153 ret = -EINVAL; 154 } 155 } else { 156 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 158 pin_reg &= ~DB_TMR_OUT_MASK; 159 pin_reg &= ~DB_CNTRl_MASK; 160 } 161 writel(pin_reg, gpio_dev->base + offset * 4); 162 spin_unlock_irqrestore(&gpio_dev->lock, flags); 163 164 return ret; 165 } 166 167 #ifdef CONFIG_DEBUG_FS 168 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 169 { 170 u32 pin_reg; 171 unsigned long flags; 172 unsigned int bank, i, pin_num; 173 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 174 175 char *level_trig; 176 char *active_level; 177 char *interrupt_enable; 178 char *interrupt_mask; 179 char *wake_cntrl0; 180 char *wake_cntrl1; 181 char *wake_cntrl2; 182 char *pin_sts; 183 char *pull_up_sel; 184 char *pull_up_enable; 185 char *pull_down_enable; 186 char *output_value; 187 char *output_enable; 188 189 for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) { 190 seq_printf(s, "GPIO bank%d\t", bank); 191 192 switch (bank) { 193 case 0: 194 i = 0; 195 pin_num = AMD_GPIO_PINS_BANK0; 196 break; 197 case 1: 198 i = 64; 199 pin_num = AMD_GPIO_PINS_BANK1 + i; 200 break; 201 case 2: 202 i = 128; 203 pin_num = AMD_GPIO_PINS_BANK2 + i; 204 break; 205 default: 206 return; 207 } 208 209 for (; i < pin_num; i++) { 210 seq_printf(s, "pin%d\t", i); 211 spin_lock_irqsave(&gpio_dev->lock, flags); 212 pin_reg = readl(gpio_dev->base + i * 4); 213 spin_unlock_irqrestore(&gpio_dev->lock, flags); 214 215 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 216 interrupt_enable = "interrupt is enabled|"; 217 218 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) 219 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) 220 active_level = "Active low|"; 221 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) 222 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) 223 active_level = "Active high|"; 224 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) 225 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1)) 226 active_level = "Active on both|"; 227 else 228 active_level = "Unknow Active level|"; 229 230 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 231 level_trig = "Level trigger|"; 232 else 233 level_trig = "Edge trigger|"; 234 235 } else { 236 interrupt_enable = 237 "interrupt is disabled|"; 238 active_level = " "; 239 level_trig = " "; 240 } 241 242 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 243 interrupt_mask = 244 "interrupt is unmasked|"; 245 else 246 interrupt_mask = 247 "interrupt is masked|"; 248 249 if (pin_reg & BIT(WAKE_CNTRL_OFF)) 250 wake_cntrl0 = "enable wakeup in S0i3 state|"; 251 else 252 wake_cntrl0 = "disable wakeup in S0i3 state|"; 253 254 if (pin_reg & BIT(WAKE_CNTRL_OFF)) 255 wake_cntrl1 = "enable wakeup in S3 state|"; 256 else 257 wake_cntrl1 = "disable wakeup in S3 state|"; 258 259 if (pin_reg & BIT(WAKE_CNTRL_OFF)) 260 wake_cntrl2 = "enable wakeup in S4/S5 state|"; 261 else 262 wake_cntrl2 = "disable wakeup in S4/S5 state|"; 263 264 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 265 pull_up_enable = "pull-up is enabled|"; 266 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 267 pull_up_sel = "8k pull-up|"; 268 else 269 pull_up_sel = "4k pull-up|"; 270 } else { 271 pull_up_enable = "pull-up is disabled|"; 272 pull_up_sel = " "; 273 } 274 275 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 276 pull_down_enable = "pull-down is enabled|"; 277 else 278 pull_down_enable = "Pull-down is disabled|"; 279 280 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 281 pin_sts = " "; 282 output_enable = "output is enabled|"; 283 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 284 output_value = "output is high|"; 285 else 286 output_value = "output is low|"; 287 } else { 288 output_enable = "output is disabled|"; 289 output_value = " "; 290 291 if (pin_reg & BIT(PIN_STS_OFF)) 292 pin_sts = "input is high|"; 293 else 294 pin_sts = "input is low|"; 295 } 296 297 seq_printf(s, "%s %s %s %s %s %s\n" 298 " %s %s %s %s %s %s %s 0x%x\n", 299 level_trig, active_level, interrupt_enable, 300 interrupt_mask, wake_cntrl0, wake_cntrl1, 301 wake_cntrl2, pin_sts, pull_up_sel, 302 pull_up_enable, pull_down_enable, 303 output_value, output_enable, pin_reg); 304 } 305 } 306 } 307 #else 308 #define amd_gpio_dbg_show NULL 309 #endif 310 311 static void amd_gpio_irq_enable(struct irq_data *d) 312 { 313 u32 pin_reg; 314 unsigned long flags; 315 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 316 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 317 318 spin_lock_irqsave(&gpio_dev->lock, flags); 319 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 320 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 321 pin_reg |= BIT(INTERRUPT_MASK_OFF); 322 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 323 spin_unlock_irqrestore(&gpio_dev->lock, flags); 324 } 325 326 static void amd_gpio_irq_disable(struct irq_data *d) 327 { 328 u32 pin_reg; 329 unsigned long flags; 330 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 331 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 332 333 spin_lock_irqsave(&gpio_dev->lock, flags); 334 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 335 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 336 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 337 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 338 spin_unlock_irqrestore(&gpio_dev->lock, flags); 339 } 340 341 static void amd_gpio_irq_mask(struct irq_data *d) 342 { 343 u32 pin_reg; 344 unsigned long flags; 345 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 346 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 347 348 spin_lock_irqsave(&gpio_dev->lock, flags); 349 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 350 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 351 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 352 spin_unlock_irqrestore(&gpio_dev->lock, flags); 353 } 354 355 static void amd_gpio_irq_unmask(struct irq_data *d) 356 { 357 u32 pin_reg; 358 unsigned long flags; 359 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 360 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 361 362 spin_lock_irqsave(&gpio_dev->lock, flags); 363 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 364 pin_reg |= BIT(INTERRUPT_MASK_OFF); 365 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 366 spin_unlock_irqrestore(&gpio_dev->lock, flags); 367 } 368 369 static void amd_gpio_irq_eoi(struct irq_data *d) 370 { 371 u32 reg; 372 unsigned long flags; 373 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 374 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 375 376 spin_lock_irqsave(&gpio_dev->lock, flags); 377 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 378 reg |= EOI_MASK; 379 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 380 spin_unlock_irqrestore(&gpio_dev->lock, flags); 381 } 382 383 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 384 { 385 int ret = 0; 386 u32 pin_reg; 387 unsigned long flags, irq_flags; 388 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 389 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 390 391 spin_lock_irqsave(&gpio_dev->lock, flags); 392 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 393 394 /* Ignore the settings coming from the client and 395 * read the values from the ACPI tables 396 * while setting the trigger type 397 */ 398 399 irq_flags = irq_get_trigger_type(d->irq); 400 if (irq_flags != IRQ_TYPE_NONE) 401 type = irq_flags; 402 403 switch (type & IRQ_TYPE_SENSE_MASK) { 404 case IRQ_TYPE_EDGE_RISING: 405 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 406 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 407 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 408 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 409 irq_set_handler_locked(d, handle_edge_irq); 410 break; 411 412 case IRQ_TYPE_EDGE_FALLING: 413 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 414 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 415 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 416 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 417 irq_set_handler_locked(d, handle_edge_irq); 418 break; 419 420 case IRQ_TYPE_EDGE_BOTH: 421 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 422 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 423 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 424 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 425 irq_set_handler_locked(d, handle_edge_irq); 426 break; 427 428 case IRQ_TYPE_LEVEL_HIGH: 429 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 430 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 431 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 432 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 433 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; 434 irq_set_handler_locked(d, handle_level_irq); 435 break; 436 437 case IRQ_TYPE_LEVEL_LOW: 438 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 439 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 440 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 441 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 442 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; 443 irq_set_handler_locked(d, handle_level_irq); 444 break; 445 446 case IRQ_TYPE_NONE: 447 break; 448 449 default: 450 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 451 ret = -EINVAL; 452 } 453 454 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 455 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 456 spin_unlock_irqrestore(&gpio_dev->lock, flags); 457 458 return ret; 459 } 460 461 static void amd_irq_ack(struct irq_data *d) 462 { 463 /* 464 * based on HW design,there is no need to ack HW 465 * before handle current irq. But this routine is 466 * necessary for handle_edge_irq 467 */ 468 } 469 470 static struct irq_chip amd_gpio_irqchip = { 471 .name = "amd_gpio", 472 .irq_ack = amd_irq_ack, 473 .irq_enable = amd_gpio_irq_enable, 474 .irq_disable = amd_gpio_irq_disable, 475 .irq_mask = amd_gpio_irq_mask, 476 .irq_unmask = amd_gpio_irq_unmask, 477 .irq_eoi = amd_gpio_irq_eoi, 478 .irq_set_type = amd_gpio_irq_set_type, 479 }; 480 481 static void amd_gpio_irq_handler(struct irq_desc *desc) 482 { 483 u32 i; 484 u32 off; 485 u32 reg; 486 u32 pin_reg; 487 u64 reg64; 488 int handled = 0; 489 unsigned int irq; 490 unsigned long flags; 491 struct irq_chip *chip = irq_desc_get_chip(desc); 492 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 493 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 494 495 chained_irq_enter(chip, desc); 496 /*enable GPIO interrupt again*/ 497 spin_lock_irqsave(&gpio_dev->lock, flags); 498 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 499 reg64 = reg; 500 reg64 = reg64 << 32; 501 502 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 503 reg64 |= reg; 504 spin_unlock_irqrestore(&gpio_dev->lock, flags); 505 506 /* 507 * first 46 bits indicates interrupt status. 508 * one bit represents four interrupt sources. 509 */ 510 for (off = 0; off < 46 ; off++) { 511 if (reg64 & BIT(off)) { 512 for (i = 0; i < 4; i++) { 513 pin_reg = readl(gpio_dev->base + 514 (off * 4 + i) * 4); 515 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) || 516 (pin_reg & BIT(WAKE_STS_OFF))) { 517 irq = irq_find_mapping(gc->irqdomain, 518 off * 4 + i); 519 generic_handle_irq(irq); 520 writel(pin_reg, 521 gpio_dev->base 522 + (off * 4 + i) * 4); 523 handled++; 524 } 525 } 526 } 527 } 528 529 if (handled == 0) 530 handle_bad_irq(desc); 531 532 spin_lock_irqsave(&gpio_dev->lock, flags); 533 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 534 reg |= EOI_MASK; 535 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 536 spin_unlock_irqrestore(&gpio_dev->lock, flags); 537 538 chained_irq_exit(chip, desc); 539 } 540 541 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 542 { 543 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 544 545 return gpio_dev->ngroups; 546 } 547 548 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 549 unsigned group) 550 { 551 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 552 553 return gpio_dev->groups[group].name; 554 } 555 556 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 557 unsigned group, 558 const unsigned **pins, 559 unsigned *num_pins) 560 { 561 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 562 563 *pins = gpio_dev->groups[group].pins; 564 *num_pins = gpio_dev->groups[group].npins; 565 return 0; 566 } 567 568 static const struct pinctrl_ops amd_pinctrl_ops = { 569 .get_groups_count = amd_get_groups_count, 570 .get_group_name = amd_get_group_name, 571 .get_group_pins = amd_get_group_pins, 572 #ifdef CONFIG_OF 573 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 574 .dt_free_map = pinctrl_utils_free_map, 575 #endif 576 }; 577 578 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 579 unsigned int pin, 580 unsigned long *config) 581 { 582 u32 pin_reg; 583 unsigned arg; 584 unsigned long flags; 585 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 586 enum pin_config_param param = pinconf_to_config_param(*config); 587 588 spin_lock_irqsave(&gpio_dev->lock, flags); 589 pin_reg = readl(gpio_dev->base + pin*4); 590 spin_unlock_irqrestore(&gpio_dev->lock, flags); 591 switch (param) { 592 case PIN_CONFIG_INPUT_DEBOUNCE: 593 arg = pin_reg & DB_TMR_OUT_MASK; 594 break; 595 596 case PIN_CONFIG_BIAS_PULL_DOWN: 597 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 598 break; 599 600 case PIN_CONFIG_BIAS_PULL_UP: 601 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 602 break; 603 604 case PIN_CONFIG_DRIVE_STRENGTH: 605 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 606 break; 607 608 default: 609 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 610 param); 611 return -ENOTSUPP; 612 } 613 614 *config = pinconf_to_config_packed(param, arg); 615 616 return 0; 617 } 618 619 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 620 unsigned long *configs, unsigned num_configs) 621 { 622 int i; 623 u32 arg; 624 int ret = 0; 625 u32 pin_reg; 626 unsigned long flags; 627 enum pin_config_param param; 628 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 629 630 spin_lock_irqsave(&gpio_dev->lock, flags); 631 for (i = 0; i < num_configs; i++) { 632 param = pinconf_to_config_param(configs[i]); 633 arg = pinconf_to_config_argument(configs[i]); 634 pin_reg = readl(gpio_dev->base + pin*4); 635 636 switch (param) { 637 case PIN_CONFIG_INPUT_DEBOUNCE: 638 pin_reg &= ~DB_TMR_OUT_MASK; 639 pin_reg |= arg & DB_TMR_OUT_MASK; 640 break; 641 642 case PIN_CONFIG_BIAS_PULL_DOWN: 643 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 644 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 645 break; 646 647 case PIN_CONFIG_BIAS_PULL_UP: 648 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 649 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 650 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 651 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 652 break; 653 654 case PIN_CONFIG_DRIVE_STRENGTH: 655 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 656 << DRV_STRENGTH_SEL_OFF); 657 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 658 << DRV_STRENGTH_SEL_OFF; 659 break; 660 661 default: 662 dev_err(&gpio_dev->pdev->dev, 663 "Invalid config param %04x\n", param); 664 ret = -ENOTSUPP; 665 } 666 667 writel(pin_reg, gpio_dev->base + pin*4); 668 } 669 spin_unlock_irqrestore(&gpio_dev->lock, flags); 670 671 return ret; 672 } 673 674 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 675 unsigned int group, 676 unsigned long *config) 677 { 678 const unsigned *pins; 679 unsigned npins; 680 int ret; 681 682 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 683 if (ret) 684 return ret; 685 686 if (amd_pinconf_get(pctldev, pins[0], config)) 687 return -ENOTSUPP; 688 689 return 0; 690 } 691 692 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 693 unsigned group, unsigned long *configs, 694 unsigned num_configs) 695 { 696 const unsigned *pins; 697 unsigned npins; 698 int i, ret; 699 700 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 701 if (ret) 702 return ret; 703 for (i = 0; i < npins; i++) { 704 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 705 return -ENOTSUPP; 706 } 707 return 0; 708 } 709 710 static const struct pinconf_ops amd_pinconf_ops = { 711 .pin_config_get = amd_pinconf_get, 712 .pin_config_set = amd_pinconf_set, 713 .pin_config_group_get = amd_pinconf_group_get, 714 .pin_config_group_set = amd_pinconf_group_set, 715 }; 716 717 static struct pinctrl_desc amd_pinctrl_desc = { 718 .pins = kerncz_pins, 719 .npins = ARRAY_SIZE(kerncz_pins), 720 .pctlops = &amd_pinctrl_ops, 721 .confops = &amd_pinconf_ops, 722 .owner = THIS_MODULE, 723 }; 724 725 static int amd_gpio_probe(struct platform_device *pdev) 726 { 727 int ret = 0; 728 int irq_base; 729 struct resource *res; 730 struct amd_gpio *gpio_dev; 731 732 gpio_dev = devm_kzalloc(&pdev->dev, 733 sizeof(struct amd_gpio), GFP_KERNEL); 734 if (!gpio_dev) 735 return -ENOMEM; 736 737 spin_lock_init(&gpio_dev->lock); 738 739 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 740 if (!res) { 741 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 742 return -EINVAL; 743 } 744 745 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, 746 resource_size(res)); 747 if (!gpio_dev->base) 748 return -ENOMEM; 749 750 irq_base = platform_get_irq(pdev, 0); 751 if (irq_base < 0) { 752 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n"); 753 return -EINVAL; 754 } 755 756 gpio_dev->pdev = pdev; 757 gpio_dev->gc.direction_input = amd_gpio_direction_input; 758 gpio_dev->gc.direction_output = amd_gpio_direction_output; 759 gpio_dev->gc.get = amd_gpio_get_value; 760 gpio_dev->gc.set = amd_gpio_set_value; 761 gpio_dev->gc.set_debounce = amd_gpio_set_debounce; 762 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 763 764 gpio_dev->gc.base = 0; 765 gpio_dev->gc.label = pdev->name; 766 gpio_dev->gc.owner = THIS_MODULE; 767 gpio_dev->gc.parent = &pdev->dev; 768 gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS; 769 #if defined(CONFIG_OF_GPIO) 770 gpio_dev->gc.of_node = pdev->dev.of_node; 771 #endif 772 773 gpio_dev->groups = kerncz_groups; 774 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 775 776 amd_pinctrl_desc.name = dev_name(&pdev->dev); 777 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 778 gpio_dev); 779 if (IS_ERR(gpio_dev->pctrl)) { 780 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 781 return PTR_ERR(gpio_dev->pctrl); 782 } 783 784 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 785 if (ret) 786 return ret; 787 788 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 789 0, 0, TOTAL_NUMBER_OF_PINS); 790 if (ret) { 791 dev_err(&pdev->dev, "Failed to add pin range\n"); 792 goto out2; 793 } 794 795 ret = gpiochip_irqchip_add(&gpio_dev->gc, 796 &amd_gpio_irqchip, 797 0, 798 handle_simple_irq, 799 IRQ_TYPE_NONE); 800 if (ret) { 801 dev_err(&pdev->dev, "could not add irqchip\n"); 802 ret = -ENODEV; 803 goto out2; 804 } 805 806 gpiochip_set_chained_irqchip(&gpio_dev->gc, 807 &amd_gpio_irqchip, 808 irq_base, 809 amd_gpio_irq_handler); 810 811 platform_set_drvdata(pdev, gpio_dev); 812 813 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 814 return ret; 815 816 out2: 817 gpiochip_remove(&gpio_dev->gc); 818 819 return ret; 820 } 821 822 static int amd_gpio_remove(struct platform_device *pdev) 823 { 824 struct amd_gpio *gpio_dev; 825 826 gpio_dev = platform_get_drvdata(pdev); 827 828 gpiochip_remove(&gpio_dev->gc); 829 830 return 0; 831 } 832 833 static const struct acpi_device_id amd_gpio_acpi_match[] = { 834 { "AMD0030", 0 }, 835 { "AMDI0030", 0}, 836 { }, 837 }; 838 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 839 840 static struct platform_driver amd_gpio_driver = { 841 .driver = { 842 .name = "amd_gpio", 843 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 844 }, 845 .probe = amd_gpio_probe, 846 .remove = amd_gpio_remove, 847 }; 848 849 module_platform_driver(amd_gpio_driver); 850 851 MODULE_LICENSE("GPL v2"); 852 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 853 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 854