1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 */ 10 11 #include <linux/err.h> 12 #include <linux/bug.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/compiler.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/log2.h> 20 #include <linux/io.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/slab.h> 23 #include <linux/platform_device.h> 24 #include <linux/mutex.h> 25 #include <linux/acpi.h> 26 #include <linux/seq_file.h> 27 #include <linux/interrupt.h> 28 #include <linux/list.h> 29 #include <linux/bitops.h> 30 #include <linux/pinctrl/pinconf.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/pinctrl/pinmux.h> 33 #include <linux/string_choices.h> 34 #include <linux/suspend.h> 35 36 #include "core.h" 37 #include "pinctrl-utils.h" 38 #include "pinctrl-amd.h" 39 40 #ifdef CONFIG_SUSPEND 41 static struct amd_gpio *pinctrl_dev; 42 #endif 43 44 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 45 { 46 unsigned long flags; 47 u32 pin_reg; 48 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 49 50 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 51 pin_reg = readl(gpio_dev->base + offset * 4); 52 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 53 54 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 55 return GPIO_LINE_DIRECTION_OUT; 56 57 return GPIO_LINE_DIRECTION_IN; 58 } 59 60 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 61 { 62 unsigned long flags; 63 u32 pin_reg; 64 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 65 66 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 67 pin_reg = readl(gpio_dev->base + offset * 4); 68 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 69 writel(pin_reg, gpio_dev->base + offset * 4); 70 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 71 72 return 0; 73 } 74 75 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 76 int value) 77 { 78 u32 pin_reg; 79 unsigned long flags; 80 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 81 82 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 83 pin_reg = readl(gpio_dev->base + offset * 4); 84 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 85 if (value) 86 pin_reg |= BIT(OUTPUT_VALUE_OFF); 87 else 88 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 89 writel(pin_reg, gpio_dev->base + offset * 4); 90 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 91 92 return 0; 93 } 94 95 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 96 { 97 u32 pin_reg; 98 unsigned long flags; 99 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 100 101 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 102 pin_reg = readl(gpio_dev->base + offset * 4); 103 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 104 105 return !!(pin_reg & BIT(PIN_STS_OFF)); 106 } 107 108 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 109 { 110 u32 pin_reg; 111 unsigned long flags; 112 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 113 114 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 115 pin_reg = readl(gpio_dev->base + offset * 4); 116 if (value) 117 pin_reg |= BIT(OUTPUT_VALUE_OFF); 118 else 119 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 120 writel(pin_reg, gpio_dev->base + offset * 4); 121 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 122 } 123 124 static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset, 125 unsigned int debounce) 126 { 127 u32 time; 128 u32 pin_reg; 129 int ret = 0; 130 131 /* Use special handling for Pin0 debounce */ 132 if (offset == 0) { 133 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 134 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) 135 debounce = 0; 136 } 137 138 pin_reg = readl(gpio_dev->base + offset * 4); 139 140 if (debounce) { 141 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 142 pin_reg &= ~DB_TMR_OUT_MASK; 143 /* 144 Debounce Debounce Timer Max 145 TmrLarge TmrOutUnit Unit Debounce 146 Time 147 0 0 61 usec (2 RtcClk) 976 usec 148 0 1 244 usec (8 RtcClk) 3.9 msec 149 1 0 15.6 msec (512 RtcClk) 250 msec 150 1 1 62.5 msec (2048 RtcClk) 1 sec 151 */ 152 153 if (debounce < 61) { 154 pin_reg |= 1; 155 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 157 } else if (debounce < 976) { 158 time = debounce / 61; 159 pin_reg |= time & DB_TMR_OUT_MASK; 160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 161 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 162 } else if (debounce < 3900) { 163 time = debounce / 244; 164 pin_reg |= time & DB_TMR_OUT_MASK; 165 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 166 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 167 } else if (debounce < 250000) { 168 time = debounce / 15625; 169 pin_reg |= time & DB_TMR_OUT_MASK; 170 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 171 pin_reg |= BIT(DB_TMR_LARGE_OFF); 172 } else if (debounce < 1000000) { 173 time = debounce / 62500; 174 pin_reg |= time & DB_TMR_OUT_MASK; 175 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 176 pin_reg |= BIT(DB_TMR_LARGE_OFF); 177 } else { 178 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 179 ret = -EINVAL; 180 } 181 } else { 182 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 183 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 184 pin_reg &= ~DB_TMR_OUT_MASK; 185 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 186 } 187 writel(pin_reg, gpio_dev->base + offset * 4); 188 189 return ret; 190 } 191 192 #ifdef CONFIG_DEBUG_FS 193 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 194 { 195 u32 pin_reg; 196 u32 db_cntrl; 197 unsigned long flags; 198 unsigned int bank, i, pin_num; 199 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 200 201 bool tmr_out_unit; 202 bool tmr_large; 203 204 char *level_trig; 205 char *active_level; 206 char *interrupt_mask; 207 char *wake_cntrl0; 208 char *wake_cntrl1; 209 char *wake_cntrl2; 210 char *pin_sts; 211 char *interrupt_sts; 212 char *wake_sts; 213 char *orientation; 214 char debounce_value[40]; 215 char *debounce_enable; 216 char *wake_cntrlz; 217 218 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG)); 219 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 220 unsigned int time = 0; 221 unsigned int unit = 0; 222 223 switch (bank) { 224 case 0: 225 i = 0; 226 pin_num = AMD_GPIO_PINS_BANK0; 227 break; 228 case 1: 229 i = 64; 230 pin_num = AMD_GPIO_PINS_BANK1 + i; 231 break; 232 case 2: 233 i = 128; 234 pin_num = AMD_GPIO_PINS_BANK2 + i; 235 break; 236 case 3: 237 i = 192; 238 pin_num = AMD_GPIO_PINS_BANK3 + i; 239 break; 240 default: 241 /* Illegal bank number, ignore */ 242 continue; 243 } 244 seq_printf(s, "GPIO bank%d\n", bank); 245 seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n"); 246 for (; i < pin_num; i++) { 247 seq_printf(s, "#%d\t", i); 248 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 249 pin_reg = readl(gpio_dev->base + i * 4); 250 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 251 252 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 253 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 254 ACTIVE_LEVEL_MASK; 255 256 if (level == ACTIVE_LEVEL_HIGH) 257 active_level = "↑"; 258 else if (level == ACTIVE_LEVEL_LOW) 259 active_level = "↓"; 260 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 261 level == ACTIVE_LEVEL_BOTH) 262 active_level = "b"; 263 else 264 active_level = "?"; 265 266 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 267 level_trig = "level"; 268 else 269 level_trig = " edge"; 270 271 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 272 interrupt_mask = "��"; 273 else 274 interrupt_mask = "��"; 275 276 if (pin_reg & BIT(INTERRUPT_STS_OFF)) 277 interrupt_sts = "��"; 278 else 279 interrupt_sts = " "; 280 281 seq_printf(s, "%s %s| %s| %s|", 282 interrupt_sts, 283 interrupt_mask, 284 active_level, 285 level_trig); 286 } else 287 seq_puts(s, " ∅| | |"); 288 289 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 290 wake_cntrl0 = "⏰"; 291 else 292 wake_cntrl0 = " "; 293 seq_printf(s, " %s| ", wake_cntrl0); 294 295 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 296 wake_cntrl1 = "⏰"; 297 else 298 wake_cntrl1 = " "; 299 seq_printf(s, "%s|", wake_cntrl1); 300 301 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 302 wake_cntrl2 = "⏰"; 303 else 304 wake_cntrl2 = " "; 305 seq_printf(s, " %s|", wake_cntrl2); 306 307 if (pin_reg & BIT(WAKECNTRL_Z_OFF)) 308 wake_cntrlz = "⏰"; 309 else 310 wake_cntrlz = " "; 311 seq_printf(s, "%s|", wake_cntrlz); 312 313 if (pin_reg & BIT(WAKE_STS_OFF)) 314 wake_sts = "��"; 315 else 316 wake_sts = " "; 317 seq_printf(s, " %s|", wake_sts); 318 319 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 320 seq_puts(s, " ↑ |"); 321 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) { 322 seq_puts(s, " ↓ |"); 323 } else { 324 seq_puts(s, " |"); 325 } 326 327 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 328 pin_sts = "output"; 329 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 330 orientation = "↑"; 331 else 332 orientation = "↓"; 333 } else { 334 pin_sts = "input "; 335 if (pin_reg & BIT(PIN_STS_OFF)) 336 orientation = "↑"; 337 else 338 orientation = "↓"; 339 } 340 seq_printf(s, "%s %s|", pin_sts, orientation); 341 342 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 343 if (db_cntrl) { 344 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 345 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 346 time = pin_reg & DB_TMR_OUT_MASK; 347 if (tmr_large) { 348 if (tmr_out_unit) 349 unit = 62500; 350 else 351 unit = 15625; 352 } else { 353 if (tmr_out_unit) 354 unit = 244; 355 else 356 unit = 61; 357 } 358 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 359 debounce_enable = "b"; 360 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 361 debounce_enable = "↓"; 362 else 363 debounce_enable = "↑"; 364 snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit); 365 seq_printf(s, "%s (�� %sus)|", debounce_enable, debounce_value); 366 } else { 367 seq_puts(s, " |"); 368 } 369 seq_printf(s, "0x%x\n", pin_reg); 370 } 371 } 372 } 373 #else 374 #define amd_gpio_dbg_show NULL 375 #endif 376 377 static void amd_gpio_irq_enable(struct irq_data *d) 378 { 379 u32 pin_reg; 380 unsigned long flags; 381 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 382 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 383 384 gpiochip_enable_irq(gc, d->hwirq); 385 386 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 387 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 388 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 389 pin_reg |= BIT(INTERRUPT_MASK_OFF); 390 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 391 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 392 } 393 394 static void amd_gpio_irq_disable(struct irq_data *d) 395 { 396 u32 pin_reg; 397 unsigned long flags; 398 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 399 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 400 401 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 402 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 403 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 404 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 405 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 406 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 407 408 gpiochip_disable_irq(gc, d->hwirq); 409 } 410 411 static void amd_gpio_irq_mask(struct irq_data *d) 412 { 413 u32 pin_reg; 414 unsigned long flags; 415 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 416 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 417 418 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 419 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 420 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 421 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 422 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 423 } 424 425 static void amd_gpio_irq_unmask(struct irq_data *d) 426 { 427 u32 pin_reg; 428 unsigned long flags; 429 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 430 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 431 432 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 433 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 434 pin_reg |= BIT(INTERRUPT_MASK_OFF); 435 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 436 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 437 } 438 439 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 440 { 441 u32 pin_reg; 442 unsigned long flags; 443 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 444 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 445 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 446 int err; 447 448 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 449 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 450 451 if (on) 452 pin_reg |= wake_mask; 453 else 454 pin_reg &= ~wake_mask; 455 456 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 457 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 458 459 if (on) 460 err = enable_irq_wake(gpio_dev->irq); 461 else 462 err = disable_irq_wake(gpio_dev->irq); 463 464 if (err) 465 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", 466 str_enable_disable(on)); 467 468 return 0; 469 } 470 471 static void amd_gpio_irq_eoi(struct irq_data *d) 472 { 473 u32 reg; 474 unsigned long flags; 475 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 476 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 477 478 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 479 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 480 reg |= EOI_MASK; 481 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 482 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 483 } 484 485 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 486 { 487 int ret = 0; 488 u32 pin_reg, pin_reg_irq_en, mask; 489 unsigned long flags; 490 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 491 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 492 493 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 494 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 495 496 switch (type & IRQ_TYPE_SENSE_MASK) { 497 case IRQ_TYPE_EDGE_RISING: 498 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 499 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 500 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 501 irq_set_handler_locked(d, handle_edge_irq); 502 break; 503 504 case IRQ_TYPE_EDGE_FALLING: 505 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 506 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 507 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 508 irq_set_handler_locked(d, handle_edge_irq); 509 break; 510 511 case IRQ_TYPE_EDGE_BOTH: 512 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 513 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 514 pin_reg |= BOTH_EDGES << ACTIVE_LEVEL_OFF; 515 irq_set_handler_locked(d, handle_edge_irq); 516 break; 517 518 case IRQ_TYPE_LEVEL_HIGH: 519 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 520 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 521 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 522 irq_set_handler_locked(d, handle_level_irq); 523 break; 524 525 case IRQ_TYPE_LEVEL_LOW: 526 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 527 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 528 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 529 irq_set_handler_locked(d, handle_level_irq); 530 break; 531 532 case IRQ_TYPE_NONE: 533 break; 534 535 default: 536 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 537 ret = -EINVAL; 538 } 539 540 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 541 /* 542 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 543 * debounce registers of any GPIO will block wake/interrupt status 544 * generation for *all* GPIOs for a length of time that depends on 545 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 546 * INTERRUPT_ENABLE bit will read as 0. 547 * 548 * We temporarily enable irq for the GPIO whose configuration is 549 * changing, and then wait for it to read back as 1 to know when 550 * debounce has settled and then disable the irq again. 551 * We do this polling with the spinlock held to ensure other GPIO 552 * access routines do not read an incorrect value for the irq enable 553 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 554 * spurious irqs, and disable the irq again after polling. 555 */ 556 mask = BIT(INTERRUPT_ENABLE_OFF); 557 pin_reg_irq_en = pin_reg; 558 pin_reg_irq_en |= mask; 559 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 560 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 561 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 562 continue; 563 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 564 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 565 566 return ret; 567 } 568 569 static void amd_irq_ack(struct irq_data *d) 570 { 571 /* 572 * based on HW design,there is no need to ack HW 573 * before handle current irq. But this routine is 574 * necessary for handle_edge_irq 575 */ 576 } 577 578 static const struct irq_chip amd_gpio_irqchip = { 579 .name = "amd_gpio", 580 .irq_ack = amd_irq_ack, 581 .irq_enable = amd_gpio_irq_enable, 582 .irq_disable = amd_gpio_irq_disable, 583 .irq_mask = amd_gpio_irq_mask, 584 .irq_unmask = amd_gpio_irq_unmask, 585 .irq_set_wake = amd_gpio_irq_set_wake, 586 .irq_eoi = amd_gpio_irq_eoi, 587 .irq_set_type = amd_gpio_irq_set_type, 588 /* 589 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 590 * also generates an IRQ. We need the IRQ so the irq_handler can clear 591 * the wake event. Otherwise the wake event will never clear and 592 * prevent the system from suspending. 593 */ 594 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE, 595 GPIOCHIP_IRQ_RESOURCE_HELPERS, 596 }; 597 598 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 599 600 static bool do_amd_gpio_irq_handler(int irq, void *dev_id) 601 { 602 struct amd_gpio *gpio_dev = dev_id; 603 struct gpio_chip *gc = &gpio_dev->gc; 604 unsigned int i, irqnr; 605 unsigned long flags; 606 u32 __iomem *regs; 607 bool ret = false; 608 u32 regval; 609 u64 status, mask; 610 611 /* Read the wake status */ 612 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 613 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 614 status <<= 32; 615 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 616 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 617 618 /* Bit 0-45 contain the relevant status bits */ 619 status &= (1ULL << 46) - 1; 620 regs = gpio_dev->base; 621 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 622 if (!(status & mask)) 623 continue; 624 status &= ~mask; 625 626 /* Each status bit covers four pins */ 627 for (i = 0; i < 4; i++) { 628 regval = readl(regs + i); 629 630 if (regval & PIN_IRQ_PENDING) 631 pm_pr_dbg("GPIO %d is active: 0x%x", 632 irqnr + i, regval); 633 634 /* caused wake on resume context for shared IRQ */ 635 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) 636 return true; 637 638 if (!(regval & PIN_IRQ_PENDING) || 639 !(regval & BIT(INTERRUPT_MASK_OFF))) 640 continue; 641 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i); 642 643 /* Clear interrupt. 644 * We must read the pin register again, in case the 645 * value was changed while executing 646 * generic_handle_domain_irq() above. 647 * If the line is not an irq, disable it in order to 648 * avoid a system hang caused by an interrupt storm. 649 */ 650 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 651 regval = readl(regs + i); 652 if (!gpiochip_line_is_irq(gc, irqnr + i)) { 653 regval &= ~BIT(INTERRUPT_MASK_OFF); 654 dev_dbg(&gpio_dev->pdev->dev, 655 "Disabling spurious GPIO IRQ %d\n", 656 irqnr + i); 657 } else { 658 ret = true; 659 } 660 writel(regval, regs + i); 661 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 662 } 663 } 664 /* did not cause wake on resume context for shared IRQ */ 665 if (irq < 0) 666 return false; 667 668 /* Signal EOI to the GPIO unit */ 669 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 670 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 671 regval |= EOI_MASK; 672 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 673 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 674 675 return ret; 676 } 677 678 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 679 { 680 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id)); 681 } 682 683 static bool __maybe_unused amd_gpio_check_wake(void *dev_id) 684 { 685 return do_amd_gpio_irq_handler(-1, dev_id); 686 } 687 688 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 689 { 690 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 691 692 return gpio_dev->ngroups; 693 } 694 695 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 696 unsigned group) 697 { 698 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 699 700 return gpio_dev->groups[group].name; 701 } 702 703 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 704 unsigned group, 705 const unsigned **pins, 706 unsigned *num_pins) 707 { 708 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 709 710 *pins = gpio_dev->groups[group].pins; 711 *num_pins = gpio_dev->groups[group].npins; 712 return 0; 713 } 714 715 static const struct pinctrl_ops amd_pinctrl_ops = { 716 .get_groups_count = amd_get_groups_count, 717 .get_group_name = amd_get_group_name, 718 .get_group_pins = amd_get_group_pins, 719 #ifdef CONFIG_OF 720 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 721 .dt_free_map = pinctrl_utils_free_map, 722 #endif 723 }; 724 725 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 726 unsigned int pin, 727 unsigned long *config) 728 { 729 u32 pin_reg; 730 unsigned arg; 731 unsigned long flags; 732 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 733 enum pin_config_param param = pinconf_to_config_param(*config); 734 735 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 736 pin_reg = readl(gpio_dev->base + pin*4); 737 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 738 switch (param) { 739 case PIN_CONFIG_INPUT_DEBOUNCE: 740 arg = pin_reg & DB_TMR_OUT_MASK; 741 break; 742 743 case PIN_CONFIG_BIAS_PULL_DOWN: 744 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 745 break; 746 747 case PIN_CONFIG_BIAS_PULL_UP: 748 arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0); 749 break; 750 751 case PIN_CONFIG_DRIVE_STRENGTH: 752 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 753 break; 754 755 default: 756 dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 757 param); 758 return -ENOTSUPP; 759 } 760 761 *config = pinconf_to_config_packed(param, arg); 762 763 return 0; 764 } 765 766 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 767 unsigned long *configs, unsigned int num_configs) 768 { 769 int i; 770 u32 arg; 771 int ret = 0; 772 u32 pin_reg; 773 unsigned long flags; 774 enum pin_config_param param; 775 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 776 777 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 778 for (i = 0; i < num_configs; i++) { 779 param = pinconf_to_config_param(configs[i]); 780 arg = pinconf_to_config_argument(configs[i]); 781 pin_reg = readl(gpio_dev->base + pin*4); 782 783 switch (param) { 784 case PIN_CONFIG_INPUT_DEBOUNCE: 785 ret = amd_gpio_set_debounce(gpio_dev, pin, arg); 786 goto out_unlock; 787 788 case PIN_CONFIG_BIAS_PULL_DOWN: 789 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 790 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 791 break; 792 793 case PIN_CONFIG_BIAS_PULL_UP: 794 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 795 pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF; 796 break; 797 798 case PIN_CONFIG_DRIVE_STRENGTH: 799 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 800 << DRV_STRENGTH_SEL_OFF); 801 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 802 << DRV_STRENGTH_SEL_OFF; 803 break; 804 805 default: 806 dev_dbg(&gpio_dev->pdev->dev, 807 "Invalid config param %04x\n", param); 808 ret = -ENOTSUPP; 809 } 810 811 writel(pin_reg, gpio_dev->base + pin*4); 812 } 813 out_unlock: 814 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 815 816 return ret; 817 } 818 819 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 820 unsigned int group, 821 unsigned long *config) 822 { 823 const unsigned *pins; 824 unsigned npins; 825 int ret; 826 827 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 828 if (ret) 829 return ret; 830 831 if (amd_pinconf_get(pctldev, pins[0], config)) 832 return -ENOTSUPP; 833 834 return 0; 835 } 836 837 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 838 unsigned group, unsigned long *configs, 839 unsigned num_configs) 840 { 841 const unsigned *pins; 842 unsigned npins; 843 int i, ret; 844 845 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 846 if (ret) 847 return ret; 848 for (i = 0; i < npins; i++) { 849 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 850 return -ENOTSUPP; 851 } 852 return 0; 853 } 854 855 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin, 856 unsigned long config) 857 { 858 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 859 860 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1); 861 } 862 863 static const struct pinconf_ops amd_pinconf_ops = { 864 .pin_config_get = amd_pinconf_get, 865 .pin_config_set = amd_pinconf_set, 866 .pin_config_group_get = amd_pinconf_group_get, 867 .pin_config_group_set = amd_pinconf_group_set, 868 }; 869 870 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 871 { 872 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 873 unsigned long flags; 874 u32 pin_reg, mask; 875 int i; 876 877 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 878 BIT(WAKE_CNTRL_OFF_S4); 879 880 for (i = 0; i < desc->npins; i++) { 881 int pin = desc->pins[i].number; 882 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 883 884 if (!pd) 885 continue; 886 887 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 888 889 pin_reg = readl(gpio_dev->base + pin * 4); 890 pin_reg &= ~mask; 891 writel(pin_reg, gpio_dev->base + pin * 4); 892 893 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 894 } 895 } 896 897 #if defined(CONFIG_SUSPEND) && defined(CONFIG_ACPI) 898 static void amd_gpio_check_pending(void) 899 { 900 struct amd_gpio *gpio_dev = pinctrl_dev; 901 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 902 int i; 903 904 if (!pm_debug_messages_on) 905 return; 906 907 for (i = 0; i < desc->npins; i++) { 908 int pin = desc->pins[i].number; 909 u32 tmp; 910 911 tmp = readl(gpio_dev->base + pin * 4); 912 if (tmp & PIN_IRQ_PENDING) 913 pm_pr_dbg("%s: GPIO %d is active: 0x%x.\n", __func__, pin, tmp); 914 } 915 } 916 917 static struct acpi_s2idle_dev_ops pinctrl_amd_s2idle_dev_ops = { 918 .check = amd_gpio_check_pending, 919 }; 920 921 static void amd_gpio_register_s2idle_ops(void) 922 { 923 acpi_register_lps0_dev(&pinctrl_amd_s2idle_dev_ops); 924 } 925 926 static void amd_gpio_unregister_s2idle_ops(void) 927 { 928 acpi_unregister_lps0_dev(&pinctrl_amd_s2idle_dev_ops); 929 } 930 #else 931 static inline void amd_gpio_register_s2idle_ops(void) {} 932 static inline void amd_gpio_unregister_s2idle_ops(void) {} 933 #endif 934 935 #ifdef CONFIG_PM_SLEEP 936 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 937 { 938 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 939 940 if (!pd) 941 return false; 942 943 /* 944 * Only restore the pin if it is actually in use by the kernel (or 945 * by userspace). 946 */ 947 if (pd->mux_owner || pd->gpio_owner || 948 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 949 return true; 950 951 return false; 952 } 953 954 static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend) 955 { 956 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 957 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 958 unsigned long flags; 959 int i; 960 u32 wake_mask = is_suspend ? WAKE_SOURCE_SUSPEND : WAKE_SOURCE_HIBERNATE; 961 962 for (i = 0; i < desc->npins; i++) { 963 int pin = desc->pins[i].number; 964 965 if (!amd_gpio_should_save(gpio_dev, pin)) 966 continue; 967 968 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 969 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; 970 971 /* mask any interrupts not intended to be a wake source */ 972 if (!(gpio_dev->saved_regs[i] & wake_mask)) { 973 writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF), 974 gpio_dev->base + pin * 4); 975 pm_pr_dbg("Disabling GPIO #%d interrupt for %s.\n", 976 pin, is_suspend ? "suspend" : "hibernate"); 977 } 978 979 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 980 } 981 982 return 0; 983 } 984 985 static int amd_gpio_suspend(struct device *dev) 986 { 987 #ifdef CONFIG_SUSPEND 988 pinctrl_dev = dev_get_drvdata(dev); 989 #endif 990 return amd_gpio_suspend_hibernate_common(dev, true); 991 } 992 993 static int amd_gpio_hibernate(struct device *dev) 994 { 995 return amd_gpio_suspend_hibernate_common(dev, false); 996 } 997 998 static int amd_gpio_resume(struct device *dev) 999 { 1000 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 1001 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 1002 unsigned long flags; 1003 int i; 1004 1005 for (i = 0; i < desc->npins; i++) { 1006 int pin = desc->pins[i].number; 1007 1008 if (!amd_gpio_should_save(gpio_dev, pin)) 1009 continue; 1010 1011 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 1012 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; 1013 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); 1014 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 1015 } 1016 1017 return 0; 1018 } 1019 1020 static const struct dev_pm_ops amd_gpio_pm_ops = { 1021 .suspend_late = amd_gpio_suspend, 1022 .resume_early = amd_gpio_resume, 1023 .freeze_late = amd_gpio_hibernate, 1024 .thaw_early = amd_gpio_resume, 1025 .poweroff_late = amd_gpio_hibernate, 1026 .restore_early = amd_gpio_resume, 1027 }; 1028 #endif 1029 1030 static int amd_get_functions_count(struct pinctrl_dev *pctldev) 1031 { 1032 return ARRAY_SIZE(pmx_functions); 1033 } 1034 1035 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector) 1036 { 1037 return pmx_functions[selector].name; 1038 } 1039 1040 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, 1041 const char * const **groups, 1042 unsigned int * const num_groups) 1043 { 1044 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 1045 1046 if (!gpio_dev->iomux_base) { 1047 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); 1048 return -EINVAL; 1049 } 1050 1051 *groups = pmx_functions[selector].groups; 1052 *num_groups = pmx_functions[selector].ngroups; 1053 return 0; 1054 } 1055 1056 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group) 1057 { 1058 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 1059 struct device *dev = &gpio_dev->pdev->dev; 1060 struct pin_desc *pd; 1061 int ind, index; 1062 1063 if (!gpio_dev->iomux_base) 1064 return -EINVAL; 1065 1066 for (index = 0; index < NSELECTS; index++) { 1067 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index])) 1068 continue; 1069 1070 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) == 1071 FUNCTION_INVALID) { 1072 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1073 pmx_functions[function].index); 1074 return -EINVAL; 1075 } 1076 1077 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index); 1078 1079 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) & 1080 FUNCTION_MASK)) { 1081 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1082 pmx_functions[function].index); 1083 return -EINVAL; 1084 } 1085 1086 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { 1087 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F"))) 1088 continue; 1089 1090 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); 1091 pd->mux_owner = gpio_dev->groups[group].name; 1092 } 1093 break; 1094 } 1095 1096 return 0; 1097 } 1098 1099 static const struct pinmux_ops amd_pmxops = { 1100 .get_functions_count = amd_get_functions_count, 1101 .get_function_name = amd_get_fname, 1102 .get_function_groups = amd_get_groups, 1103 .set_mux = amd_set_mux, 1104 }; 1105 1106 static struct pinctrl_desc amd_pinctrl_desc = { 1107 .pins = kerncz_pins, 1108 .npins = ARRAY_SIZE(kerncz_pins), 1109 .pctlops = &amd_pinctrl_ops, 1110 .pmxops = &amd_pmxops, 1111 .confops = &amd_pinconf_ops, 1112 .owner = THIS_MODULE, 1113 }; 1114 1115 static void amd_get_iomux_res(struct amd_gpio *gpio_dev) 1116 { 1117 struct pinctrl_desc *desc = &amd_pinctrl_desc; 1118 struct device *dev = &gpio_dev->pdev->dev; 1119 int index; 1120 1121 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux"); 1122 if (index < 0) { 1123 dev_dbg(dev, "iomux not supported\n"); 1124 goto out_no_pinmux; 1125 } 1126 1127 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index); 1128 if (IS_ERR(gpio_dev->iomux_base)) { 1129 dev_dbg(dev, "iomux not supported %d io resource\n", index); 1130 goto out_no_pinmux; 1131 } 1132 1133 return; 1134 1135 out_no_pinmux: 1136 desc->pmxops = NULL; 1137 } 1138 1139 static int amd_gpio_probe(struct platform_device *pdev) 1140 { 1141 int ret = 0; 1142 struct resource *res; 1143 struct amd_gpio *gpio_dev; 1144 struct gpio_irq_chip *girq; 1145 1146 gpio_dev = devm_kzalloc(&pdev->dev, 1147 sizeof(struct amd_gpio), GFP_KERNEL); 1148 if (!gpio_dev) 1149 return -ENOMEM; 1150 1151 raw_spin_lock_init(&gpio_dev->lock); 1152 1153 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1154 if (IS_ERR(gpio_dev->base)) { 1155 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 1156 return PTR_ERR(gpio_dev->base); 1157 } 1158 1159 gpio_dev->irq = platform_get_irq(pdev, 0); 1160 if (gpio_dev->irq < 0) 1161 return gpio_dev->irq; 1162 1163 #ifdef CONFIG_SUSPEND 1164 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 1165 sizeof(*gpio_dev->saved_regs), 1166 GFP_KERNEL); 1167 if (!gpio_dev->saved_regs) 1168 return -ENOMEM; 1169 #endif 1170 1171 gpio_dev->pdev = pdev; 1172 gpio_dev->gc.get_direction = amd_gpio_get_direction; 1173 gpio_dev->gc.direction_input = amd_gpio_direction_input; 1174 gpio_dev->gc.direction_output = amd_gpio_direction_output; 1175 gpio_dev->gc.get = amd_gpio_get_value; 1176 gpio_dev->gc.set = amd_gpio_set_value; 1177 gpio_dev->gc.set_config = amd_gpio_set_config; 1178 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 1179 1180 gpio_dev->gc.base = -1; 1181 gpio_dev->gc.label = pdev->name; 1182 gpio_dev->gc.owner = THIS_MODULE; 1183 gpio_dev->gc.parent = &pdev->dev; 1184 gpio_dev->gc.ngpio = resource_size(res) / 4; 1185 1186 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 1187 gpio_dev->groups = kerncz_groups; 1188 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 1189 1190 amd_pinctrl_desc.name = dev_name(&pdev->dev); 1191 amd_get_iomux_res(gpio_dev); 1192 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 1193 gpio_dev); 1194 if (IS_ERR(gpio_dev->pctrl)) { 1195 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1196 return PTR_ERR(gpio_dev->pctrl); 1197 } 1198 1199 /* Disable and mask interrupts */ 1200 amd_gpio_irq_init(gpio_dev); 1201 1202 girq = &gpio_dev->gc.irq; 1203 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); 1204 /* This will let us handle the parent IRQ in the driver */ 1205 girq->parent_handler = NULL; 1206 girq->num_parents = 0; 1207 girq->parents = NULL; 1208 girq->default_type = IRQ_TYPE_NONE; 1209 girq->handler = handle_simple_irq; 1210 1211 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 1212 if (ret) 1213 return ret; 1214 1215 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 1216 0, 0, gpio_dev->gc.ngpio); 1217 if (ret) { 1218 dev_err(&pdev->dev, "Failed to add pin range\n"); 1219 goto out2; 1220 } 1221 1222 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, 1223 IRQF_SHARED | IRQF_COND_ONESHOT, KBUILD_MODNAME, gpio_dev); 1224 if (ret) 1225 goto out2; 1226 1227 platform_set_drvdata(pdev, gpio_dev); 1228 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); 1229 amd_gpio_register_s2idle_ops(); 1230 1231 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1232 return ret; 1233 1234 out2: 1235 gpiochip_remove(&gpio_dev->gc); 1236 1237 return ret; 1238 } 1239 1240 static void amd_gpio_remove(struct platform_device *pdev) 1241 { 1242 struct amd_gpio *gpio_dev; 1243 1244 gpio_dev = platform_get_drvdata(pdev); 1245 1246 gpiochip_remove(&gpio_dev->gc); 1247 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); 1248 amd_gpio_unregister_s2idle_ops(); 1249 } 1250 1251 #ifdef CONFIG_ACPI 1252 static const struct acpi_device_id amd_gpio_acpi_match[] = { 1253 { "AMD0030", 0 }, 1254 { "AMDI0030", 0}, 1255 { "AMDI0031", 0}, 1256 { }, 1257 }; 1258 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1259 #endif 1260 1261 static struct platform_driver amd_gpio_driver = { 1262 .driver = { 1263 .name = "amd_gpio", 1264 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1265 #ifdef CONFIG_PM_SLEEP 1266 .pm = &amd_gpio_pm_ops, 1267 #endif 1268 }, 1269 .probe = amd_gpio_probe, 1270 .remove = amd_gpio_remove, 1271 }; 1272 1273 module_platform_driver(amd_gpio_driver); 1274 1275 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1276 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1277