1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 */ 10 11 #include <linux/err.h> 12 #include <linux/bug.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/compiler.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/log2.h> 20 #include <linux/io.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/slab.h> 23 #include <linux/platform_device.h> 24 #include <linux/mutex.h> 25 #include <linux/acpi.h> 26 #include <linux/seq_file.h> 27 #include <linux/interrupt.h> 28 #include <linux/list.h> 29 #include <linux/bitops.h> 30 #include <linux/pinctrl/pinconf.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/pinctrl/pinmux.h> 33 #include <linux/string_choices.h> 34 #include <linux/suspend.h> 35 36 #include "core.h" 37 #include "pinctrl-utils.h" 38 #include "pinctrl-amd.h" 39 40 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 41 { 42 unsigned long flags; 43 u32 pin_reg; 44 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 45 46 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 47 pin_reg = readl(gpio_dev->base + offset * 4); 48 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 49 50 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 51 return GPIO_LINE_DIRECTION_OUT; 52 53 return GPIO_LINE_DIRECTION_IN; 54 } 55 56 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 57 { 58 unsigned long flags; 59 u32 pin_reg; 60 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 61 62 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 63 pin_reg = readl(gpio_dev->base + offset * 4); 64 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 65 writel(pin_reg, gpio_dev->base + offset * 4); 66 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 67 68 return 0; 69 } 70 71 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 72 int value) 73 { 74 u32 pin_reg; 75 unsigned long flags; 76 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 77 78 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 79 pin_reg = readl(gpio_dev->base + offset * 4); 80 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 81 if (value) 82 pin_reg |= BIT(OUTPUT_VALUE_OFF); 83 else 84 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 85 writel(pin_reg, gpio_dev->base + offset * 4); 86 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 87 88 return 0; 89 } 90 91 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 92 { 93 u32 pin_reg; 94 unsigned long flags; 95 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 96 97 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 98 pin_reg = readl(gpio_dev->base + offset * 4); 99 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 100 101 return !!(pin_reg & BIT(PIN_STS_OFF)); 102 } 103 104 static int amd_gpio_set_value(struct gpio_chip *gc, unsigned int offset, 105 int value) 106 { 107 u32 pin_reg; 108 unsigned long flags; 109 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 110 111 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 112 pin_reg = readl(gpio_dev->base + offset * 4); 113 if (value) 114 pin_reg |= BIT(OUTPUT_VALUE_OFF); 115 else 116 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 117 writel(pin_reg, gpio_dev->base + offset * 4); 118 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 119 120 return 0; 121 } 122 123 static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset, 124 unsigned int debounce) 125 { 126 u32 time; 127 u32 pin_reg; 128 int ret = 0; 129 130 /* Use special handling for Pin0 debounce */ 131 if (offset == 0) { 132 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 133 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) 134 debounce = 0; 135 } 136 137 pin_reg = readl(gpio_dev->base + offset * 4); 138 139 if (debounce) { 140 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 141 pin_reg &= ~DB_TMR_OUT_MASK; 142 /* 143 Debounce Debounce Timer Max 144 TmrLarge TmrOutUnit Unit Debounce 145 Time 146 0 0 61 usec (2 RtcClk) 976 usec 147 0 1 244 usec (8 RtcClk) 3.9 msec 148 1 0 15.6 msec (512 RtcClk) 250 msec 149 1 1 62.5 msec (2048 RtcClk) 1 sec 150 */ 151 152 if (debounce < 61) { 153 pin_reg |= 1; 154 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 155 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 156 } else if (debounce < 976) { 157 time = debounce / 61; 158 pin_reg |= time & DB_TMR_OUT_MASK; 159 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 160 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 161 } else if (debounce < 3900) { 162 time = debounce / 244; 163 pin_reg |= time & DB_TMR_OUT_MASK; 164 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 165 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 166 } else if (debounce < 250000) { 167 time = debounce / 15625; 168 pin_reg |= time & DB_TMR_OUT_MASK; 169 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 170 pin_reg |= BIT(DB_TMR_LARGE_OFF); 171 } else if (debounce < 1000000) { 172 time = debounce / 62500; 173 pin_reg |= time & DB_TMR_OUT_MASK; 174 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 175 pin_reg |= BIT(DB_TMR_LARGE_OFF); 176 } else { 177 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 178 ret = -EINVAL; 179 } 180 } else { 181 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 182 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 183 pin_reg &= ~DB_TMR_OUT_MASK; 184 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 185 } 186 writel(pin_reg, gpio_dev->base + offset * 4); 187 188 return ret; 189 } 190 191 #ifdef CONFIG_DEBUG_FS 192 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 193 { 194 u32 pin_reg; 195 u32 db_cntrl; 196 unsigned long flags; 197 unsigned int bank, i, pin_num; 198 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 199 200 bool tmr_out_unit; 201 bool tmr_large; 202 203 char *level_trig; 204 char *active_level; 205 char *interrupt_mask; 206 char *wake_cntrl0; 207 char *wake_cntrl1; 208 char *wake_cntrl2; 209 char *pin_sts; 210 char *interrupt_sts; 211 char *wake_sts; 212 char *orientation; 213 char debounce_value[40]; 214 char *debounce_enable; 215 char *wake_cntrlz; 216 217 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG)); 218 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 219 unsigned int time = 0; 220 unsigned int unit = 0; 221 222 switch (bank) { 223 case 0: 224 i = 0; 225 pin_num = AMD_GPIO_PINS_BANK0; 226 break; 227 case 1: 228 i = 64; 229 pin_num = AMD_GPIO_PINS_BANK1 + i; 230 break; 231 case 2: 232 i = 128; 233 pin_num = AMD_GPIO_PINS_BANK2 + i; 234 break; 235 case 3: 236 i = 192; 237 pin_num = AMD_GPIO_PINS_BANK3 + i; 238 break; 239 default: 240 /* Illegal bank number, ignore */ 241 continue; 242 } 243 seq_printf(s, "GPIO bank%d\n", bank); 244 seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n"); 245 for (; i < pin_num; i++) { 246 seq_printf(s, "#%d\t", i); 247 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 248 pin_reg = readl(gpio_dev->base + i * 4); 249 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 250 251 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 252 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 253 ACTIVE_LEVEL_MASK; 254 255 if (level == ACTIVE_LEVEL_HIGH) 256 active_level = "↑"; 257 else if (level == ACTIVE_LEVEL_LOW) 258 active_level = "↓"; 259 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 260 level == ACTIVE_LEVEL_BOTH) 261 active_level = "b"; 262 else 263 active_level = "?"; 264 265 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 266 level_trig = "level"; 267 else 268 level_trig = " edge"; 269 270 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 271 interrupt_mask = "��"; 272 else 273 interrupt_mask = "��"; 274 275 if (pin_reg & BIT(INTERRUPT_STS_OFF)) 276 interrupt_sts = "��"; 277 else 278 interrupt_sts = " "; 279 280 seq_printf(s, "%s %s| %s| %s|", 281 interrupt_sts, 282 interrupt_mask, 283 active_level, 284 level_trig); 285 } else 286 seq_puts(s, " ∅| | |"); 287 288 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 289 wake_cntrl0 = "⏰"; 290 else 291 wake_cntrl0 = " "; 292 seq_printf(s, " %s| ", wake_cntrl0); 293 294 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 295 wake_cntrl1 = "⏰"; 296 else 297 wake_cntrl1 = " "; 298 seq_printf(s, "%s|", wake_cntrl1); 299 300 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 301 wake_cntrl2 = "⏰"; 302 else 303 wake_cntrl2 = " "; 304 seq_printf(s, " %s|", wake_cntrl2); 305 306 if (pin_reg & BIT(WAKECNTRL_Z_OFF)) 307 wake_cntrlz = "⏰"; 308 else 309 wake_cntrlz = " "; 310 seq_printf(s, "%s|", wake_cntrlz); 311 312 if (pin_reg & BIT(WAKE_STS_OFF)) 313 wake_sts = "��"; 314 else 315 wake_sts = " "; 316 seq_printf(s, " %s|", wake_sts); 317 318 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 319 seq_puts(s, " ↑ |"); 320 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) { 321 seq_puts(s, " ↓ |"); 322 } else { 323 seq_puts(s, " |"); 324 } 325 326 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 327 pin_sts = "output"; 328 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 329 orientation = "↑"; 330 else 331 orientation = "↓"; 332 } else { 333 pin_sts = "input "; 334 if (pin_reg & BIT(PIN_STS_OFF)) 335 orientation = "↑"; 336 else 337 orientation = "↓"; 338 } 339 seq_printf(s, "%s %s|", pin_sts, orientation); 340 341 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 342 if (db_cntrl) { 343 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 344 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 345 time = pin_reg & DB_TMR_OUT_MASK; 346 if (tmr_large) { 347 if (tmr_out_unit) 348 unit = 62500; 349 else 350 unit = 15625; 351 } else { 352 if (tmr_out_unit) 353 unit = 244; 354 else 355 unit = 61; 356 } 357 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 358 debounce_enable = "b"; 359 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 360 debounce_enable = "↓"; 361 else 362 debounce_enable = "↑"; 363 snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit); 364 seq_printf(s, "%s (�� %sus)|", debounce_enable, debounce_value); 365 } else { 366 seq_puts(s, " |"); 367 } 368 seq_printf(s, "0x%x\n", pin_reg); 369 } 370 } 371 } 372 #else 373 #define amd_gpio_dbg_show NULL 374 #endif 375 376 static void amd_gpio_irq_enable(struct irq_data *d) 377 { 378 u32 pin_reg; 379 unsigned long flags; 380 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 381 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 382 383 gpiochip_enable_irq(gc, d->hwirq); 384 385 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 386 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 387 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 388 pin_reg |= BIT(INTERRUPT_MASK_OFF); 389 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 390 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 391 } 392 393 static void amd_gpio_irq_disable(struct irq_data *d) 394 { 395 u32 pin_reg; 396 unsigned long flags; 397 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 398 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 399 400 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 401 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 402 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 403 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 404 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 405 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 406 407 gpiochip_disable_irq(gc, d->hwirq); 408 } 409 410 static void amd_gpio_irq_mask(struct irq_data *d) 411 { 412 u32 pin_reg; 413 unsigned long flags; 414 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 415 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 416 417 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 418 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 419 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 420 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 421 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 422 } 423 424 static void amd_gpio_irq_unmask(struct irq_data *d) 425 { 426 u32 pin_reg; 427 unsigned long flags; 428 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 429 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 430 431 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 432 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 433 pin_reg |= BIT(INTERRUPT_MASK_OFF); 434 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 435 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 436 } 437 438 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 439 { 440 u32 pin_reg; 441 unsigned long flags; 442 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 443 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 444 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 445 int err; 446 447 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 448 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 449 450 if (on) 451 pin_reg |= wake_mask; 452 else 453 pin_reg &= ~wake_mask; 454 455 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 456 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 457 458 if (on) 459 err = enable_irq_wake(gpio_dev->irq); 460 else 461 err = disable_irq_wake(gpio_dev->irq); 462 463 if (err) 464 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", 465 str_enable_disable(on)); 466 467 return 0; 468 } 469 470 static void amd_gpio_irq_eoi(struct irq_data *d) 471 { 472 u32 reg; 473 unsigned long flags; 474 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 475 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 476 477 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 478 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 479 reg |= EOI_MASK; 480 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 481 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 482 } 483 484 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 485 { 486 int ret = 0; 487 u32 pin_reg, pin_reg_irq_en, mask; 488 unsigned long flags; 489 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 490 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 491 492 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 493 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 494 495 switch (type & IRQ_TYPE_SENSE_MASK) { 496 case IRQ_TYPE_EDGE_RISING: 497 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 498 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 499 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 500 irq_set_handler_locked(d, handle_edge_irq); 501 break; 502 503 case IRQ_TYPE_EDGE_FALLING: 504 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 505 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 506 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 507 irq_set_handler_locked(d, handle_edge_irq); 508 break; 509 510 case IRQ_TYPE_EDGE_BOTH: 511 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 512 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 513 pin_reg |= BOTH_EDGES << ACTIVE_LEVEL_OFF; 514 irq_set_handler_locked(d, handle_edge_irq); 515 break; 516 517 case IRQ_TYPE_LEVEL_HIGH: 518 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 519 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 520 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 521 irq_set_handler_locked(d, handle_level_irq); 522 break; 523 524 case IRQ_TYPE_LEVEL_LOW: 525 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 526 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 527 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 528 irq_set_handler_locked(d, handle_level_irq); 529 break; 530 531 case IRQ_TYPE_NONE: 532 break; 533 534 default: 535 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 536 ret = -EINVAL; 537 } 538 539 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 540 /* 541 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 542 * debounce registers of any GPIO will block wake/interrupt status 543 * generation for *all* GPIOs for a length of time that depends on 544 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 545 * INTERRUPT_ENABLE bit will read as 0. 546 * 547 * We temporarily enable irq for the GPIO whose configuration is 548 * changing, and then wait for it to read back as 1 to know when 549 * debounce has settled and then disable the irq again. 550 * We do this polling with the spinlock held to ensure other GPIO 551 * access routines do not read an incorrect value for the irq enable 552 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 553 * spurious irqs, and disable the irq again after polling. 554 */ 555 mask = BIT(INTERRUPT_ENABLE_OFF); 556 pin_reg_irq_en = pin_reg; 557 pin_reg_irq_en |= mask; 558 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 559 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 560 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 561 continue; 562 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 563 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 564 565 return ret; 566 } 567 568 static void amd_irq_ack(struct irq_data *d) 569 { 570 /* 571 * based on HW design,there is no need to ack HW 572 * before handle current irq. But this routine is 573 * necessary for handle_edge_irq 574 */ 575 } 576 577 static const struct irq_chip amd_gpio_irqchip = { 578 .name = "amd_gpio", 579 .irq_ack = amd_irq_ack, 580 .irq_enable = amd_gpio_irq_enable, 581 .irq_disable = amd_gpio_irq_disable, 582 .irq_mask = amd_gpio_irq_mask, 583 .irq_unmask = amd_gpio_irq_unmask, 584 .irq_set_wake = amd_gpio_irq_set_wake, 585 .irq_eoi = amd_gpio_irq_eoi, 586 .irq_set_type = amd_gpio_irq_set_type, 587 /* 588 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 589 * also generates an IRQ. We need the IRQ so the irq_handler can clear 590 * the wake event. Otherwise the wake event will never clear and 591 * prevent the system from suspending. 592 */ 593 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE, 594 GPIOCHIP_IRQ_RESOURCE_HELPERS, 595 }; 596 597 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 598 599 static bool do_amd_gpio_irq_handler(int irq, void *dev_id) 600 { 601 struct amd_gpio *gpio_dev = dev_id; 602 struct gpio_chip *gc = &gpio_dev->gc; 603 unsigned int i, irqnr; 604 unsigned long flags; 605 u32 __iomem *regs; 606 bool ret = false; 607 u32 regval; 608 u64 status, mask; 609 610 /* Read the wake status */ 611 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 612 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 613 status <<= 32; 614 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 615 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 616 617 /* Bit 0-45 contain the relevant status bits */ 618 status &= (1ULL << 46) - 1; 619 regs = gpio_dev->base; 620 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 621 if (!(status & mask)) 622 continue; 623 status &= ~mask; 624 625 /* Each status bit covers four pins */ 626 for (i = 0; i < 4; i++) { 627 regval = readl(regs + i); 628 629 if (regval & PIN_IRQ_PENDING) 630 pm_pr_dbg("GPIO %d is active: 0x%x", 631 irqnr + i, regval); 632 633 /* caused wake on resume context for shared IRQ */ 634 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) 635 return true; 636 637 if (!(regval & PIN_IRQ_PENDING) || 638 !(regval & BIT(INTERRUPT_MASK_OFF))) 639 continue; 640 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i); 641 642 /* Clear interrupt. 643 * We must read the pin register again, in case the 644 * value was changed while executing 645 * generic_handle_domain_irq() above. 646 * If the line is not an irq, disable it in order to 647 * avoid a system hang caused by an interrupt storm. 648 */ 649 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 650 regval = readl(regs + i); 651 if (!gpiochip_line_is_irq(gc, irqnr + i)) { 652 regval &= ~BIT(INTERRUPT_MASK_OFF); 653 dev_dbg(&gpio_dev->pdev->dev, 654 "Disabling spurious GPIO IRQ %d\n", 655 irqnr + i); 656 } else { 657 ret = true; 658 } 659 writel(regval, regs + i); 660 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 661 } 662 } 663 /* did not cause wake on resume context for shared IRQ */ 664 if (irq < 0) 665 return false; 666 667 /* Signal EOI to the GPIO unit */ 668 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 669 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 670 regval |= EOI_MASK; 671 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 672 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 673 674 return ret; 675 } 676 677 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 678 { 679 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id)); 680 } 681 682 static bool __maybe_unused amd_gpio_check_wake(void *dev_id) 683 { 684 return do_amd_gpio_irq_handler(-1, dev_id); 685 } 686 687 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 688 { 689 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 690 691 return gpio_dev->ngroups; 692 } 693 694 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 695 unsigned group) 696 { 697 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 698 699 return gpio_dev->groups[group].name; 700 } 701 702 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 703 unsigned group, 704 const unsigned **pins, 705 unsigned *num_pins) 706 { 707 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 708 709 *pins = gpio_dev->groups[group].pins; 710 *num_pins = gpio_dev->groups[group].npins; 711 return 0; 712 } 713 714 static const struct pinctrl_ops amd_pinctrl_ops = { 715 .get_groups_count = amd_get_groups_count, 716 .get_group_name = amd_get_group_name, 717 .get_group_pins = amd_get_group_pins, 718 #ifdef CONFIG_OF 719 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 720 .dt_free_map = pinctrl_utils_free_map, 721 #endif 722 }; 723 724 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 725 unsigned int pin, 726 unsigned long *config) 727 { 728 u32 pin_reg; 729 unsigned arg; 730 unsigned long flags; 731 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 732 enum pin_config_param param = pinconf_to_config_param(*config); 733 734 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 735 pin_reg = readl(gpio_dev->base + pin*4); 736 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 737 switch (param) { 738 case PIN_CONFIG_INPUT_DEBOUNCE: 739 arg = pin_reg & DB_TMR_OUT_MASK; 740 break; 741 742 case PIN_CONFIG_BIAS_PULL_DOWN: 743 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 744 break; 745 746 case PIN_CONFIG_BIAS_PULL_UP: 747 arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0); 748 break; 749 750 case PIN_CONFIG_DRIVE_STRENGTH: 751 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 752 break; 753 754 default: 755 dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 756 param); 757 return -ENOTSUPP; 758 } 759 760 *config = pinconf_to_config_packed(param, arg); 761 762 return 0; 763 } 764 765 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 766 unsigned long *configs, unsigned int num_configs) 767 { 768 int i; 769 u32 arg; 770 int ret = 0; 771 u32 pin_reg; 772 unsigned long flags; 773 enum pin_config_param param; 774 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 775 776 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 777 for (i = 0; i < num_configs; i++) { 778 param = pinconf_to_config_param(configs[i]); 779 arg = pinconf_to_config_argument(configs[i]); 780 pin_reg = readl(gpio_dev->base + pin*4); 781 782 switch (param) { 783 case PIN_CONFIG_INPUT_DEBOUNCE: 784 ret = amd_gpio_set_debounce(gpio_dev, pin, arg); 785 goto out_unlock; 786 787 case PIN_CONFIG_BIAS_PULL_DOWN: 788 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 789 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 790 break; 791 792 case PIN_CONFIG_BIAS_PULL_UP: 793 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 794 pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF; 795 break; 796 797 case PIN_CONFIG_DRIVE_STRENGTH: 798 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 799 << DRV_STRENGTH_SEL_OFF); 800 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 801 << DRV_STRENGTH_SEL_OFF; 802 break; 803 804 default: 805 dev_dbg(&gpio_dev->pdev->dev, 806 "Invalid config param %04x\n", param); 807 ret = -ENOTSUPP; 808 } 809 810 writel(pin_reg, gpio_dev->base + pin*4); 811 } 812 out_unlock: 813 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 814 815 return ret; 816 } 817 818 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 819 unsigned int group, 820 unsigned long *config) 821 { 822 const unsigned *pins; 823 unsigned npins; 824 int ret; 825 826 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 827 if (ret) 828 return ret; 829 830 if (amd_pinconf_get(pctldev, pins[0], config)) 831 return -ENOTSUPP; 832 833 return 0; 834 } 835 836 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 837 unsigned group, unsigned long *configs, 838 unsigned num_configs) 839 { 840 const unsigned *pins; 841 unsigned npins; 842 int i, ret; 843 844 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 845 if (ret) 846 return ret; 847 for (i = 0; i < npins; i++) { 848 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 849 return -ENOTSUPP; 850 } 851 return 0; 852 } 853 854 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin, 855 unsigned long config) 856 { 857 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 858 859 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1); 860 } 861 862 static const struct pinconf_ops amd_pinconf_ops = { 863 .pin_config_get = amd_pinconf_get, 864 .pin_config_set = amd_pinconf_set, 865 .pin_config_group_get = amd_pinconf_group_get, 866 .pin_config_group_set = amd_pinconf_group_set, 867 }; 868 869 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 870 { 871 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 872 unsigned long flags; 873 u32 pin_reg, mask; 874 int i; 875 876 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 877 BIT(WAKE_CNTRL_OFF_S4); 878 879 for (i = 0; i < desc->npins; i++) { 880 int pin = desc->pins[i].number; 881 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 882 883 if (!pd) 884 continue; 885 886 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 887 888 pin_reg = readl(gpio_dev->base + pin * 4); 889 pin_reg &= ~mask; 890 writel(pin_reg, gpio_dev->base + pin * 4); 891 892 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 893 } 894 } 895 896 #ifdef CONFIG_PM_SLEEP 897 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 898 { 899 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 900 901 if (!pd) 902 return false; 903 904 /* 905 * Only restore the pin if it is actually in use by the kernel (or 906 * by userspace). 907 */ 908 if (pd->mux_owner || pd->gpio_owner || 909 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 910 return true; 911 912 return false; 913 } 914 915 static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend) 916 { 917 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 918 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 919 unsigned long flags; 920 int i; 921 u32 wake_mask = is_suspend ? WAKE_SOURCE_SUSPEND : WAKE_SOURCE_HIBERNATE; 922 923 for (i = 0; i < desc->npins; i++) { 924 int pin = desc->pins[i].number; 925 926 if (!amd_gpio_should_save(gpio_dev, pin)) 927 continue; 928 929 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 930 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; 931 932 /* mask any interrupts not intended to be a wake source */ 933 if (!(gpio_dev->saved_regs[i] & wake_mask)) { 934 writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF), 935 gpio_dev->base + pin * 4); 936 pm_pr_dbg("Disabling GPIO #%d interrupt for %s.\n", 937 pin, is_suspend ? "suspend" : "hibernate"); 938 } 939 940 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 941 } 942 943 return 0; 944 } 945 946 static int amd_gpio_suspend(struct device *dev) 947 { 948 return amd_gpio_suspend_hibernate_common(dev, true); 949 } 950 951 static int amd_gpio_hibernate(struct device *dev) 952 { 953 return amd_gpio_suspend_hibernate_common(dev, false); 954 } 955 956 static int amd_gpio_resume(struct device *dev) 957 { 958 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 959 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 960 unsigned long flags; 961 int i; 962 963 for (i = 0; i < desc->npins; i++) { 964 int pin = desc->pins[i].number; 965 966 if (!amd_gpio_should_save(gpio_dev, pin)) 967 continue; 968 969 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 970 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; 971 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); 972 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 973 } 974 975 return 0; 976 } 977 978 static const struct dev_pm_ops amd_gpio_pm_ops = { 979 .suspend_late = amd_gpio_suspend, 980 .resume_early = amd_gpio_resume, 981 .freeze_late = amd_gpio_hibernate, 982 .thaw_early = amd_gpio_resume, 983 .poweroff_late = amd_gpio_hibernate, 984 .restore_early = amd_gpio_resume, 985 }; 986 #endif 987 988 static int amd_get_functions_count(struct pinctrl_dev *pctldev) 989 { 990 return ARRAY_SIZE(pmx_functions); 991 } 992 993 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector) 994 { 995 return pmx_functions[selector].name; 996 } 997 998 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, 999 const char * const **groups, 1000 unsigned int * const num_groups) 1001 { 1002 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 1003 1004 if (!gpio_dev->iomux_base) { 1005 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); 1006 return -EINVAL; 1007 } 1008 1009 *groups = pmx_functions[selector].groups; 1010 *num_groups = pmx_functions[selector].ngroups; 1011 return 0; 1012 } 1013 1014 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group) 1015 { 1016 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 1017 struct device *dev = &gpio_dev->pdev->dev; 1018 struct pin_desc *pd; 1019 int ind, index; 1020 1021 if (!gpio_dev->iomux_base) 1022 return -EINVAL; 1023 1024 for (index = 0; index < NSELECTS; index++) { 1025 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index])) 1026 continue; 1027 1028 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) == 1029 FUNCTION_INVALID) { 1030 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1031 pmx_functions[function].index); 1032 return -EINVAL; 1033 } 1034 1035 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index); 1036 1037 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) & 1038 FUNCTION_MASK)) { 1039 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1040 pmx_functions[function].index); 1041 return -EINVAL; 1042 } 1043 1044 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { 1045 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F"))) 1046 continue; 1047 1048 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); 1049 pd->mux_owner = gpio_dev->groups[group].name; 1050 } 1051 break; 1052 } 1053 1054 return 0; 1055 } 1056 1057 static const struct pinmux_ops amd_pmxops = { 1058 .get_functions_count = amd_get_functions_count, 1059 .get_function_name = amd_get_fname, 1060 .get_function_groups = amd_get_groups, 1061 .set_mux = amd_set_mux, 1062 }; 1063 1064 static struct pinctrl_desc amd_pinctrl_desc = { 1065 .pins = kerncz_pins, 1066 .npins = ARRAY_SIZE(kerncz_pins), 1067 .pctlops = &amd_pinctrl_ops, 1068 .pmxops = &amd_pmxops, 1069 .confops = &amd_pinconf_ops, 1070 .owner = THIS_MODULE, 1071 }; 1072 1073 static void amd_get_iomux_res(struct amd_gpio *gpio_dev) 1074 { 1075 struct pinctrl_desc *desc = &amd_pinctrl_desc; 1076 struct device *dev = &gpio_dev->pdev->dev; 1077 int index; 1078 1079 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux"); 1080 if (index < 0) { 1081 dev_dbg(dev, "iomux not supported\n"); 1082 goto out_no_pinmux; 1083 } 1084 1085 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index); 1086 if (IS_ERR(gpio_dev->iomux_base)) { 1087 dev_dbg(dev, "iomux not supported %d io resource\n", index); 1088 goto out_no_pinmux; 1089 } 1090 1091 return; 1092 1093 out_no_pinmux: 1094 desc->pmxops = NULL; 1095 } 1096 1097 static int amd_gpio_probe(struct platform_device *pdev) 1098 { 1099 int ret = 0; 1100 struct resource *res; 1101 struct amd_gpio *gpio_dev; 1102 struct gpio_irq_chip *girq; 1103 1104 gpio_dev = devm_kzalloc(&pdev->dev, 1105 sizeof(struct amd_gpio), GFP_KERNEL); 1106 if (!gpio_dev) 1107 return -ENOMEM; 1108 1109 raw_spin_lock_init(&gpio_dev->lock); 1110 1111 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1112 if (IS_ERR(gpio_dev->base)) { 1113 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 1114 return PTR_ERR(gpio_dev->base); 1115 } 1116 1117 gpio_dev->irq = platform_get_irq(pdev, 0); 1118 if (gpio_dev->irq < 0) 1119 return gpio_dev->irq; 1120 1121 #ifdef CONFIG_PM_SLEEP 1122 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 1123 sizeof(*gpio_dev->saved_regs), 1124 GFP_KERNEL); 1125 if (!gpio_dev->saved_regs) 1126 return -ENOMEM; 1127 #endif 1128 1129 gpio_dev->pdev = pdev; 1130 gpio_dev->gc.get_direction = amd_gpio_get_direction; 1131 gpio_dev->gc.direction_input = amd_gpio_direction_input; 1132 gpio_dev->gc.direction_output = amd_gpio_direction_output; 1133 gpio_dev->gc.get = amd_gpio_get_value; 1134 gpio_dev->gc.set_rv = amd_gpio_set_value; 1135 gpio_dev->gc.set_config = amd_gpio_set_config; 1136 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 1137 1138 gpio_dev->gc.base = -1; 1139 gpio_dev->gc.label = pdev->name; 1140 gpio_dev->gc.owner = THIS_MODULE; 1141 gpio_dev->gc.parent = &pdev->dev; 1142 gpio_dev->gc.ngpio = resource_size(res) / 4; 1143 1144 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 1145 gpio_dev->groups = kerncz_groups; 1146 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 1147 1148 amd_pinctrl_desc.name = dev_name(&pdev->dev); 1149 amd_get_iomux_res(gpio_dev); 1150 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 1151 gpio_dev); 1152 if (IS_ERR(gpio_dev->pctrl)) { 1153 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1154 return PTR_ERR(gpio_dev->pctrl); 1155 } 1156 1157 /* Disable and mask interrupts */ 1158 amd_gpio_irq_init(gpio_dev); 1159 1160 girq = &gpio_dev->gc.irq; 1161 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); 1162 /* This will let us handle the parent IRQ in the driver */ 1163 girq->parent_handler = NULL; 1164 girq->num_parents = 0; 1165 girq->parents = NULL; 1166 girq->default_type = IRQ_TYPE_NONE; 1167 girq->handler = handle_simple_irq; 1168 1169 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 1170 if (ret) 1171 return ret; 1172 1173 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 1174 0, 0, gpio_dev->gc.ngpio); 1175 if (ret) { 1176 dev_err(&pdev->dev, "Failed to add pin range\n"); 1177 goto out2; 1178 } 1179 1180 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, 1181 IRQF_SHARED | IRQF_COND_ONESHOT, KBUILD_MODNAME, gpio_dev); 1182 if (ret) 1183 goto out2; 1184 1185 platform_set_drvdata(pdev, gpio_dev); 1186 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); 1187 1188 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1189 return ret; 1190 1191 out2: 1192 gpiochip_remove(&gpio_dev->gc); 1193 1194 return ret; 1195 } 1196 1197 static void amd_gpio_remove(struct platform_device *pdev) 1198 { 1199 struct amd_gpio *gpio_dev; 1200 1201 gpio_dev = platform_get_drvdata(pdev); 1202 1203 gpiochip_remove(&gpio_dev->gc); 1204 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); 1205 } 1206 1207 #ifdef CONFIG_ACPI 1208 static const struct acpi_device_id amd_gpio_acpi_match[] = { 1209 { "AMD0030", 0 }, 1210 { "AMDI0030", 0}, 1211 { "AMDI0031", 0}, 1212 { }, 1213 }; 1214 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1215 #endif 1216 1217 static struct platform_driver amd_gpio_driver = { 1218 .driver = { 1219 .name = "amd_gpio", 1220 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1221 #ifdef CONFIG_PM_SLEEP 1222 .pm = &amd_gpio_pm_ops, 1223 #endif 1224 }, 1225 .probe = amd_gpio_probe, 1226 .remove = amd_gpio_remove, 1227 }; 1228 1229 module_platform_driver(amd_gpio_driver); 1230 1231 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1232 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1233