1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Core driver for the S32 CC (Common Chassis) pin controller 4 * 5 * Copyright 2017-2022 NXP 6 * Copyright (C) 2022 SUSE LLC 7 * Copyright 2015-2016 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/err.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/pinctrl/machine.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinctrl.h> 21 #include <linux/pinctrl/pinmux.h> 22 #include <linux/regmap.h> 23 #include <linux/seq_file.h> 24 #include <linux/slab.h> 25 26 #include "../core.h" 27 #include "../pinconf.h" 28 #include "../pinctrl-utils.h" 29 #include "pinctrl-s32.h" 30 31 #define S32_PIN_ID_SHIFT 4 32 #define S32_PIN_ID_MASK GENMASK(31, S32_PIN_ID_SHIFT) 33 34 #define S32_MSCR_SSS_MASK GENMASK(2, 0) 35 #define S32_MSCR_PUS BIT(12) 36 #define S32_MSCR_PUE BIT(13) 37 #define S32_MSCR_SRE(X) (((X) & GENMASK(3, 0)) << 14) 38 #define S32_MSCR_IBE BIT(19) 39 #define S32_MSCR_ODE BIT(20) 40 #define S32_MSCR_OBE BIT(21) 41 42 static struct regmap_config s32_regmap_config = { 43 .reg_bits = 32, 44 .val_bits = 32, 45 .reg_stride = 4, 46 }; 47 48 static u32 get_pin_no(u32 pinmux) 49 { 50 return (pinmux & S32_PIN_ID_MASK) >> S32_PIN_ID_SHIFT; 51 } 52 53 static u32 get_pin_func(u32 pinmux) 54 { 55 return pinmux & GENMASK(3, 0); 56 } 57 58 struct s32_pinctrl_mem_region { 59 struct regmap *map; 60 const struct s32_pin_range *pin_range; 61 char name[8]; 62 }; 63 64 /* 65 * Holds pin configuration for GPIO's. 66 * @pin_id: Pin ID for this GPIO 67 * @config: Pin settings 68 * @list: Linked list entry for each gpio pin 69 */ 70 struct gpio_pin_config { 71 unsigned int pin_id; 72 unsigned int config; 73 struct list_head list; 74 }; 75 76 /* 77 * Pad config save/restore for power suspend/resume. 78 */ 79 struct s32_pinctrl_context { 80 unsigned int *pads; 81 }; 82 83 /* 84 * @dev: a pointer back to containing device 85 * @pctl: a pointer to the pinctrl device structure 86 * @regions: reserved memory regions with start/end pin 87 * @info: structure containing information about the pin 88 * @gpio_configs: Saved configurations for GPIO pins 89 * @gpiop_configs_lock: lock for the `gpio_configs` list 90 * @s32_pinctrl_context: Configuration saved over system sleep 91 */ 92 struct s32_pinctrl { 93 struct device *dev; 94 struct pinctrl_dev *pctl; 95 struct s32_pinctrl_mem_region *regions; 96 struct s32_pinctrl_soc_info *info; 97 struct list_head gpio_configs; 98 spinlock_t gpio_configs_lock; 99 #ifdef CONFIG_PM_SLEEP 100 struct s32_pinctrl_context saved_context; 101 #endif 102 }; 103 104 static struct s32_pinctrl_mem_region * 105 s32_get_region(struct pinctrl_dev *pctldev, unsigned int pin) 106 { 107 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 108 const struct s32_pin_range *pin_range; 109 unsigned int mem_regions = ipctl->info->soc_data->mem_regions; 110 unsigned int i; 111 112 for (i = 0; i < mem_regions; i++) { 113 pin_range = ipctl->regions[i].pin_range; 114 if (pin >= pin_range->start && pin <= pin_range->end) 115 return &ipctl->regions[i]; 116 } 117 118 return NULL; 119 } 120 121 static inline int s32_check_pin(struct pinctrl_dev *pctldev, 122 unsigned int pin) 123 { 124 return s32_get_region(pctldev, pin) ? 0 : -EINVAL; 125 } 126 127 static inline int s32_regmap_read(struct pinctrl_dev *pctldev, 128 unsigned int pin, unsigned int *val) 129 { 130 struct s32_pinctrl_mem_region *region; 131 unsigned int offset; 132 133 region = s32_get_region(pctldev, pin); 134 if (!region) 135 return -EINVAL; 136 137 offset = (pin - region->pin_range->start) * 138 regmap_get_reg_stride(region->map); 139 140 return regmap_read(region->map, offset, val); 141 } 142 143 static inline int s32_regmap_write(struct pinctrl_dev *pctldev, 144 unsigned int pin, 145 unsigned int val) 146 { 147 struct s32_pinctrl_mem_region *region; 148 unsigned int offset; 149 150 region = s32_get_region(pctldev, pin); 151 if (!region) 152 return -EINVAL; 153 154 offset = (pin - region->pin_range->start) * 155 regmap_get_reg_stride(region->map); 156 157 return regmap_write(region->map, offset, val); 158 159 } 160 161 static inline int s32_regmap_update(struct pinctrl_dev *pctldev, unsigned int pin, 162 unsigned int mask, unsigned int val) 163 { 164 struct s32_pinctrl_mem_region *region; 165 unsigned int offset; 166 167 region = s32_get_region(pctldev, pin); 168 if (!region) 169 return -EINVAL; 170 171 offset = (pin - region->pin_range->start) * 172 regmap_get_reg_stride(region->map); 173 174 return regmap_update_bits(region->map, offset, mask, val); 175 } 176 177 static int s32_get_groups_count(struct pinctrl_dev *pctldev) 178 { 179 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 180 const struct s32_pinctrl_soc_info *info = ipctl->info; 181 182 return info->ngroups; 183 } 184 185 static const char *s32_get_group_name(struct pinctrl_dev *pctldev, 186 unsigned int selector) 187 { 188 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 189 const struct s32_pinctrl_soc_info *info = ipctl->info; 190 191 return info->groups[selector].data.name; 192 } 193 194 static int s32_get_group_pins(struct pinctrl_dev *pctldev, 195 unsigned int selector, const unsigned int **pins, 196 unsigned int *npins) 197 { 198 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 199 const struct s32_pinctrl_soc_info *info = ipctl->info; 200 201 *pins = info->groups[selector].data.pins; 202 *npins = info->groups[selector].data.npins; 203 204 return 0; 205 } 206 207 static void s32_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 208 unsigned int offset) 209 { 210 seq_printf(s, "%s", dev_name(pctldev->dev)); 211 } 212 213 static int s32_dt_group_node_to_map(struct pinctrl_dev *pctldev, 214 struct device_node *np, 215 struct pinctrl_map **map, 216 unsigned int *reserved_maps, 217 unsigned int *num_maps, 218 const char *func_name) 219 { 220 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 221 struct device *dev = ipctl->dev; 222 unsigned long *cfgs = NULL; 223 unsigned int n_cfgs, reserve = 1; 224 int n_pins, ret; 225 226 n_pins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32)); 227 if (n_pins < 0) { 228 dev_warn(dev, "Can't find 'pinmux' property in node %pOFn\n", np); 229 } else if (!n_pins) { 230 return -EINVAL; 231 } 232 233 ret = pinconf_generic_parse_dt_config(np, pctldev, &cfgs, &n_cfgs); 234 if (ret) { 235 dev_err(dev, "%pOF: could not parse node property\n", np); 236 return ret; 237 } 238 239 if (n_cfgs) 240 reserve++; 241 242 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, 243 reserve); 244 if (ret < 0) 245 goto free_cfgs; 246 247 ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, 248 np->name, func_name); 249 if (ret < 0) 250 goto free_cfgs; 251 252 if (n_cfgs) { 253 ret = pinctrl_utils_add_map_configs(pctldev, map, reserved_maps, 254 num_maps, np->name, cfgs, n_cfgs, 255 PIN_MAP_TYPE_CONFIGS_GROUP); 256 if (ret < 0) 257 goto free_cfgs; 258 } 259 260 free_cfgs: 261 kfree(cfgs); 262 return ret; 263 } 264 265 static int s32_dt_node_to_map(struct pinctrl_dev *pctldev, 266 struct device_node *np_config, 267 struct pinctrl_map **map, 268 unsigned int *num_maps) 269 { 270 unsigned int reserved_maps; 271 int ret; 272 273 reserved_maps = 0; 274 *map = NULL; 275 *num_maps = 0; 276 277 for_each_available_child_of_node_scoped(np_config, np) { 278 ret = s32_dt_group_node_to_map(pctldev, np, map, 279 &reserved_maps, num_maps, 280 np_config->name); 281 if (ret < 0) { 282 pinctrl_utils_free_map(pctldev, *map, *num_maps); 283 return ret; 284 } 285 } 286 287 return 0; 288 } 289 290 static const struct pinctrl_ops s32_pctrl_ops = { 291 .get_groups_count = s32_get_groups_count, 292 .get_group_name = s32_get_group_name, 293 .get_group_pins = s32_get_group_pins, 294 .pin_dbg_show = s32_pin_dbg_show, 295 .dt_node_to_map = s32_dt_node_to_map, 296 .dt_free_map = pinctrl_utils_free_map, 297 }; 298 299 static int s32_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector, 300 unsigned int group) 301 { 302 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 303 const struct s32_pinctrl_soc_info *info = ipctl->info; 304 int i, ret; 305 struct s32_pin_group *grp; 306 307 /* 308 * Configure the mux mode for each pin in the group for a specific 309 * function. 310 */ 311 grp = &info->groups[group]; 312 313 dev_dbg(ipctl->dev, "set mux for function %s group %s\n", 314 info->functions[selector].name, grp->data.name); 315 316 /* Check beforehand so we don't have a partial config. */ 317 for (i = 0; i < grp->data.npins; i++) { 318 if (s32_check_pin(pctldev, grp->data.pins[i]) != 0) { 319 dev_err(info->dev, "invalid pin: %u in group: %u\n", 320 grp->data.pins[i], group); 321 return -EINVAL; 322 } 323 } 324 325 for (i = 0, ret = 0; i < grp->data.npins && !ret; i++) { 326 ret = s32_regmap_update(pctldev, grp->data.pins[i], 327 S32_MSCR_SSS_MASK, grp->pin_sss[i]); 328 if (ret) { 329 dev_err(info->dev, "Failed to set pin %u\n", 330 grp->data.pins[i]); 331 return ret; 332 } 333 } 334 335 return 0; 336 } 337 338 static int s32_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 339 { 340 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 341 const struct s32_pinctrl_soc_info *info = ipctl->info; 342 343 return info->nfunctions; 344 } 345 346 static const char *s32_pmx_get_func_name(struct pinctrl_dev *pctldev, 347 unsigned int selector) 348 { 349 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 350 const struct s32_pinctrl_soc_info *info = ipctl->info; 351 352 return info->functions[selector].name; 353 } 354 355 static int s32_pmx_get_groups(struct pinctrl_dev *pctldev, 356 unsigned int selector, 357 const char * const **groups, 358 unsigned int * const num_groups) 359 { 360 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 361 const struct s32_pinctrl_soc_info *info = ipctl->info; 362 363 *groups = info->functions[selector].groups; 364 *num_groups = info->functions[selector].ngroups; 365 366 return 0; 367 } 368 369 static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, 370 struct pinctrl_gpio_range *range, 371 unsigned int offset) 372 { 373 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 374 struct gpio_pin_config *gpio_pin; 375 unsigned int config; 376 unsigned long flags; 377 int ret; 378 379 ret = s32_regmap_read(pctldev, offset, &config); 380 if (ret) 381 return ret; 382 383 /* Save current configuration */ 384 gpio_pin = kmalloc(sizeof(*gpio_pin), GFP_KERNEL); 385 if (!gpio_pin) 386 return -ENOMEM; 387 388 gpio_pin->pin_id = offset; 389 gpio_pin->config = config; 390 391 spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); 392 list_add(&gpio_pin->list, &ipctl->gpio_configs); 393 spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); 394 395 /* GPIO pin means SSS = 0 */ 396 config &= ~S32_MSCR_SSS_MASK; 397 398 return s32_regmap_write(pctldev, offset, config); 399 } 400 401 static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 402 struct pinctrl_gpio_range *range, 403 unsigned int offset) 404 { 405 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 406 struct gpio_pin_config *gpio_pin, *tmp; 407 unsigned long flags; 408 int ret; 409 410 spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); 411 412 list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) { 413 if (gpio_pin->pin_id == offset) { 414 ret = s32_regmap_write(pctldev, gpio_pin->pin_id, 415 gpio_pin->config); 416 if (ret != 0) 417 goto unlock; 418 419 list_del(&gpio_pin->list); 420 kfree(gpio_pin); 421 break; 422 } 423 } 424 425 unlock: 426 spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); 427 } 428 429 static int s32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 430 struct pinctrl_gpio_range *range, 431 unsigned int offset, 432 bool input) 433 { 434 unsigned int config; 435 unsigned int mask = S32_MSCR_IBE | S32_MSCR_OBE; 436 437 if (input) { 438 /* Disable output buffer and enable input buffer */ 439 config = S32_MSCR_IBE; 440 } else { 441 /* Disable input buffer and enable output buffer */ 442 config = S32_MSCR_OBE; 443 } 444 445 return s32_regmap_update(pctldev, offset, mask, config); 446 } 447 448 static const struct pinmux_ops s32_pmx_ops = { 449 .get_functions_count = s32_pmx_get_funcs_count, 450 .get_function_name = s32_pmx_get_func_name, 451 .get_function_groups = s32_pmx_get_groups, 452 .set_mux = s32_pmx_set, 453 .gpio_request_enable = s32_pmx_gpio_request_enable, 454 .gpio_disable_free = s32_pmx_gpio_disable_free, 455 .gpio_set_direction = s32_pmx_gpio_set_direction, 456 }; 457 458 /* Set the reserved elements as -1 */ 459 static const int support_slew[] = {208, -1, -1, -1, 166, 150, 133, 83}; 460 461 static int s32_get_slew_regval(int arg) 462 { 463 unsigned int i; 464 465 /* Translate a real slew rate (MHz) to a register value */ 466 for (i = 0; i < ARRAY_SIZE(support_slew); i++) { 467 if (arg == support_slew[i]) 468 return i; 469 } 470 471 return -EINVAL; 472 } 473 474 static inline void s32_pin_set_pull(enum pin_config_param param, 475 unsigned int *mask, unsigned int *config) 476 { 477 switch (param) { 478 case PIN_CONFIG_BIAS_DISABLE: 479 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 480 *config &= ~(S32_MSCR_PUS | S32_MSCR_PUE); 481 break; 482 case PIN_CONFIG_BIAS_PULL_UP: 483 *config |= S32_MSCR_PUS | S32_MSCR_PUE; 484 break; 485 case PIN_CONFIG_BIAS_PULL_DOWN: 486 *config &= ~S32_MSCR_PUS; 487 *config |= S32_MSCR_PUE; 488 break; 489 default: 490 return; 491 } 492 493 *mask |= S32_MSCR_PUS | S32_MSCR_PUE; 494 } 495 496 static int s32_parse_pincfg(unsigned long pincfg, unsigned int *mask, 497 unsigned int *config) 498 { 499 enum pin_config_param param; 500 u32 arg; 501 int ret; 502 503 param = pinconf_to_config_param(pincfg); 504 arg = pinconf_to_config_argument(pincfg); 505 506 switch (param) { 507 /* All pins are persistent over suspend */ 508 case PIN_CONFIG_PERSIST_STATE: 509 return 0; 510 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 511 *config |= S32_MSCR_ODE; 512 *mask |= S32_MSCR_ODE; 513 break; 514 case PIN_CONFIG_OUTPUT_ENABLE: 515 if (arg) 516 *config |= S32_MSCR_OBE; 517 else 518 *config &= ~S32_MSCR_OBE; 519 *mask |= S32_MSCR_OBE; 520 break; 521 case PIN_CONFIG_INPUT_ENABLE: 522 if (arg) 523 *config |= S32_MSCR_IBE; 524 else 525 *config &= ~S32_MSCR_IBE; 526 *mask |= S32_MSCR_IBE; 527 break; 528 case PIN_CONFIG_SLEW_RATE: 529 ret = s32_get_slew_regval(arg); 530 if (ret < 0) 531 return ret; 532 *config |= S32_MSCR_SRE((u32)ret); 533 *mask |= S32_MSCR_SRE(~0); 534 break; 535 case PIN_CONFIG_BIAS_DISABLE: 536 case PIN_CONFIG_BIAS_PULL_UP: 537 case PIN_CONFIG_BIAS_PULL_DOWN: 538 s32_pin_set_pull(param, mask, config); 539 break; 540 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 541 *config &= ~(S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE); 542 *mask |= S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE; 543 s32_pin_set_pull(param, mask, config); 544 break; 545 default: 546 return -EOPNOTSUPP; 547 } 548 549 return 0; 550 } 551 552 static int s32_pinconf_mscr_update(struct pinctrl_dev *pctldev, 553 unsigned int pin_id, 554 unsigned long *configs, 555 unsigned int num_configs) 556 { 557 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 558 unsigned int config = 0, mask = 0; 559 int i, ret; 560 561 ret = s32_check_pin(pctldev, pin_id); 562 if (ret) 563 return ret; 564 565 dev_dbg(ipctl->dev, "pinconf set pin %s with %u configs\n", 566 pin_get_name(pctldev, pin_id), num_configs); 567 568 for (i = 0; i < num_configs; i++) { 569 ret = s32_parse_pincfg(configs[i], &mask, &config); 570 if (ret) 571 return ret; 572 } 573 574 if (!config && !mask) 575 return 0; 576 577 dev_dbg(ipctl->dev, "update: pin %u cfg 0x%x\n", pin_id, config); 578 579 return s32_regmap_update(pctldev, pin_id, mask, config); 580 } 581 582 static int s32_pinconf_get(struct pinctrl_dev *pctldev, 583 unsigned int pin_id, 584 unsigned long *config) 585 { 586 return s32_regmap_read(pctldev, pin_id, (unsigned int *)config); 587 } 588 589 static int s32_pinconf_set(struct pinctrl_dev *pctldev, 590 unsigned int pin_id, unsigned long *configs, 591 unsigned int num_configs) 592 { 593 return s32_pinconf_mscr_update(pctldev, pin_id, configs, 594 num_configs); 595 } 596 597 static int s32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int selector, 598 unsigned long *configs, unsigned int num_configs) 599 { 600 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 601 const struct s32_pinctrl_soc_info *info = ipctl->info; 602 struct s32_pin_group *grp; 603 int i, ret; 604 605 grp = &info->groups[selector]; 606 for (i = 0; i < grp->data.npins; i++) { 607 ret = s32_pinconf_mscr_update(pctldev, grp->data.pins[i], 608 configs, num_configs); 609 if (ret) 610 return ret; 611 } 612 613 return 0; 614 } 615 616 static void s32_pinconf_dbg_show(struct pinctrl_dev *pctldev, 617 struct seq_file *s, unsigned int pin_id) 618 { 619 unsigned int config; 620 int ret; 621 622 ret = s32_regmap_read(pctldev, pin_id, &config); 623 if (ret) 624 return; 625 626 seq_printf(s, "0x%x", config); 627 } 628 629 static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 630 struct seq_file *s, unsigned int selector) 631 { 632 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 633 const struct s32_pinctrl_soc_info *info = ipctl->info; 634 struct s32_pin_group *grp; 635 unsigned int config; 636 const char *name; 637 int i, ret; 638 639 seq_puts(s, "\n"); 640 grp = &info->groups[selector]; 641 for (i = 0; i < grp->data.npins; i++) { 642 name = pin_get_name(pctldev, grp->data.pins[i]); 643 ret = s32_regmap_read(pctldev, grp->data.pins[i], &config); 644 if (ret) 645 return; 646 seq_printf(s, "%s: 0x%x\n", name, config); 647 } 648 } 649 650 static const struct pinconf_ops s32_pinconf_ops = { 651 .pin_config_get = s32_pinconf_get, 652 .pin_config_set = s32_pinconf_set, 653 .pin_config_group_set = s32_pconf_group_set, 654 .pin_config_dbg_show = s32_pinconf_dbg_show, 655 .pin_config_group_dbg_show = s32_pinconf_group_dbg_show, 656 }; 657 658 #ifdef CONFIG_PM_SLEEP 659 static bool s32_pinctrl_should_save(struct s32_pinctrl *ipctl, 660 unsigned int pin) 661 { 662 const struct pin_desc *pd = pin_desc_get(ipctl->pctl, pin); 663 664 if (!pd) 665 return false; 666 667 /* 668 * Only restore the pin if it is actually in use by the kernel (or 669 * by userspace). 670 */ 671 if (pd->mux_owner || pd->gpio_owner) 672 return true; 673 674 return false; 675 } 676 677 int s32_pinctrl_suspend(struct device *dev) 678 { 679 struct platform_device *pdev = to_platform_device(dev); 680 struct s32_pinctrl *ipctl = platform_get_drvdata(pdev); 681 const struct pinctrl_pin_desc *pin; 682 const struct s32_pinctrl_soc_info *info = ipctl->info; 683 struct s32_pinctrl_context *saved_context = &ipctl->saved_context; 684 int i; 685 int ret; 686 unsigned int config; 687 688 for (i = 0; i < info->soc_data->npins; i++) { 689 pin = &info->soc_data->pins[i]; 690 691 if (!s32_pinctrl_should_save(ipctl, pin->number)) 692 continue; 693 694 ret = s32_regmap_read(ipctl->pctl, pin->number, &config); 695 if (ret) 696 return -EINVAL; 697 698 saved_context->pads[i] = config; 699 } 700 701 return 0; 702 } 703 704 int s32_pinctrl_resume(struct device *dev) 705 { 706 struct platform_device *pdev = to_platform_device(dev); 707 struct s32_pinctrl *ipctl = platform_get_drvdata(pdev); 708 const struct s32_pinctrl_soc_info *info = ipctl->info; 709 const struct pinctrl_pin_desc *pin; 710 struct s32_pinctrl_context *saved_context = &ipctl->saved_context; 711 int ret, i; 712 713 for (i = 0; i < info->soc_data->npins; i++) { 714 pin = &info->soc_data->pins[i]; 715 716 if (!s32_pinctrl_should_save(ipctl, pin->number)) 717 continue; 718 719 ret = s32_regmap_write(ipctl->pctl, pin->number, 720 saved_context->pads[i]); 721 if (ret) 722 return ret; 723 } 724 725 return 0; 726 } 727 #endif 728 729 static int s32_pinctrl_parse_groups(struct device_node *np, 730 struct s32_pin_group *grp, 731 struct s32_pinctrl_soc_info *info) 732 { 733 const __be32 *p; 734 struct device *dev; 735 struct property *prop; 736 unsigned int *pins, *sss; 737 int i, npins; 738 u32 pinmux; 739 740 dev = info->dev; 741 742 dev_dbg(dev, "group: %pOFn\n", np); 743 744 /* Initialise group */ 745 grp->data.name = np->name; 746 747 npins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32)); 748 if (npins < 0) { 749 dev_err(dev, "Failed to read 'pinmux' property in node %s.\n", 750 grp->data.name); 751 return -EINVAL; 752 } 753 if (!npins) { 754 dev_err(dev, "The group %s has no pins.\n", grp->data.name); 755 return -EINVAL; 756 } 757 758 grp->data.npins = npins; 759 760 pins = devm_kcalloc(info->dev, npins, sizeof(*pins), GFP_KERNEL); 761 sss = devm_kcalloc(info->dev, npins, sizeof(*sss), GFP_KERNEL); 762 if (!pins || !sss) 763 return -ENOMEM; 764 765 i = 0; 766 of_property_for_each_u32(np, "pinmux", prop, p, pinmux) { 767 pins[i] = get_pin_no(pinmux); 768 sss[i] = get_pin_func(pinmux); 769 770 dev_dbg(info->dev, "pin: 0x%x, sss: 0x%x", pins[i], sss[i]); 771 i++; 772 } 773 774 grp->data.pins = pins; 775 grp->pin_sss = sss; 776 777 return 0; 778 } 779 780 static int s32_pinctrl_parse_functions(struct device_node *np, 781 struct s32_pinctrl_soc_info *info, 782 u32 index) 783 { 784 struct pinfunction *func; 785 struct s32_pin_group *grp; 786 const char **groups; 787 u32 i = 0; 788 int ret = 0; 789 790 dev_dbg(info->dev, "parse function(%u): %pOFn\n", index, np); 791 792 func = &info->functions[index]; 793 794 /* Initialise function */ 795 func->name = np->name; 796 func->ngroups = of_get_child_count(np); 797 if (func->ngroups == 0) { 798 dev_err(info->dev, "no groups defined in %pOF\n", np); 799 return -EINVAL; 800 } 801 802 groups = devm_kcalloc(info->dev, func->ngroups, 803 sizeof(*func->groups), GFP_KERNEL); 804 if (!groups) 805 return -ENOMEM; 806 807 for_each_child_of_node_scoped(np, child) { 808 groups[i] = child->name; 809 grp = &info->groups[info->grp_index++]; 810 ret = s32_pinctrl_parse_groups(child, grp, info); 811 if (ret) 812 return ret; 813 i++; 814 } 815 816 func->groups = groups; 817 818 return 0; 819 } 820 821 static int s32_pinctrl_probe_dt(struct platform_device *pdev, 822 struct s32_pinctrl *ipctl) 823 { 824 struct s32_pinctrl_soc_info *info = ipctl->info; 825 struct device_node *np = pdev->dev.of_node; 826 struct resource *res; 827 struct regmap *map; 828 void __iomem *base; 829 unsigned int mem_regions = info->soc_data->mem_regions; 830 int ret; 831 u32 nfuncs = 0; 832 u32 i = 0; 833 834 if (!np) 835 return -ENODEV; 836 837 if (mem_regions == 0 || mem_regions >= 10000) { 838 dev_err(&pdev->dev, "mem_regions is invalid: %u\n", mem_regions); 839 return -EINVAL; 840 } 841 842 ipctl->regions = devm_kcalloc(&pdev->dev, mem_regions, 843 sizeof(*ipctl->regions), GFP_KERNEL); 844 if (!ipctl->regions) 845 return -ENOMEM; 846 847 for (i = 0; i < mem_regions; i++) { 848 base = devm_platform_get_and_ioremap_resource(pdev, i, &res); 849 if (IS_ERR(base)) 850 return PTR_ERR(base); 851 852 snprintf(ipctl->regions[i].name, 853 sizeof(ipctl->regions[i].name), "map%u", i); 854 855 s32_regmap_config.name = ipctl->regions[i].name; 856 s32_regmap_config.max_register = resource_size(res) - 857 s32_regmap_config.reg_stride; 858 859 map = devm_regmap_init_mmio(&pdev->dev, base, 860 &s32_regmap_config); 861 if (IS_ERR(map)) { 862 dev_err(&pdev->dev, "Failed to init regmap[%u]\n", i); 863 return PTR_ERR(map); 864 } 865 866 ipctl->regions[i].map = map; 867 ipctl->regions[i].pin_range = &info->soc_data->mem_pin_ranges[i]; 868 } 869 870 nfuncs = of_get_child_count(np); 871 if (nfuncs <= 0) { 872 dev_err(&pdev->dev, "no functions defined\n"); 873 return -EINVAL; 874 } 875 876 info->nfunctions = nfuncs; 877 info->functions = devm_kcalloc(&pdev->dev, nfuncs, 878 sizeof(*info->functions), GFP_KERNEL); 879 if (!info->functions) 880 return -ENOMEM; 881 882 info->ngroups = 0; 883 for_each_child_of_node_scoped(np, child) 884 info->ngroups += of_get_child_count(child); 885 886 info->groups = devm_kcalloc(&pdev->dev, info->ngroups, 887 sizeof(*info->groups), GFP_KERNEL); 888 if (!info->groups) 889 return -ENOMEM; 890 891 i = 0; 892 for_each_child_of_node_scoped(np, child) { 893 ret = s32_pinctrl_parse_functions(child, info, i++); 894 if (ret) 895 return ret; 896 } 897 898 return 0; 899 } 900 901 int s32_pinctrl_probe(struct platform_device *pdev, 902 const struct s32_pinctrl_soc_data *soc_data) 903 { 904 struct s32_pinctrl *ipctl; 905 int ret; 906 struct pinctrl_desc *s32_pinctrl_desc; 907 struct s32_pinctrl_soc_info *info; 908 #ifdef CONFIG_PM_SLEEP 909 struct s32_pinctrl_context *saved_context; 910 #endif 911 912 if (!soc_data || !soc_data->pins || !soc_data->npins) { 913 dev_err(&pdev->dev, "wrong pinctrl info\n"); 914 return -EINVAL; 915 } 916 917 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 918 if (!info) 919 return -ENOMEM; 920 921 info->soc_data = soc_data; 922 info->dev = &pdev->dev; 923 924 /* Create state holders etc for this driver */ 925 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 926 if (!ipctl) 927 return -ENOMEM; 928 929 ipctl->info = info; 930 ipctl->dev = info->dev; 931 platform_set_drvdata(pdev, ipctl); 932 933 INIT_LIST_HEAD(&ipctl->gpio_configs); 934 spin_lock_init(&ipctl->gpio_configs_lock); 935 936 s32_pinctrl_desc = 937 devm_kmalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL); 938 if (!s32_pinctrl_desc) 939 return -ENOMEM; 940 941 s32_pinctrl_desc->name = dev_name(&pdev->dev); 942 s32_pinctrl_desc->pins = info->soc_data->pins; 943 s32_pinctrl_desc->npins = info->soc_data->npins; 944 s32_pinctrl_desc->pctlops = &s32_pctrl_ops; 945 s32_pinctrl_desc->pmxops = &s32_pmx_ops; 946 s32_pinctrl_desc->confops = &s32_pinconf_ops; 947 s32_pinctrl_desc->owner = THIS_MODULE; 948 949 ret = s32_pinctrl_probe_dt(pdev, ipctl); 950 if (ret) { 951 dev_err(&pdev->dev, "fail to probe dt properties\n"); 952 return ret; 953 } 954 955 ipctl->pctl = devm_pinctrl_register(&pdev->dev, s32_pinctrl_desc, 956 ipctl); 957 if (IS_ERR(ipctl->pctl)) 958 return dev_err_probe(&pdev->dev, PTR_ERR(ipctl->pctl), 959 "could not register s32 pinctrl driver\n"); 960 961 #ifdef CONFIG_PM_SLEEP 962 saved_context = &ipctl->saved_context; 963 saved_context->pads = 964 devm_kcalloc(&pdev->dev, info->soc_data->npins, 965 sizeof(*saved_context->pads), 966 GFP_KERNEL); 967 if (!saved_context->pads) 968 return -ENOMEM; 969 #endif 970 971 dev_info(&pdev->dev, "initialized s32 pinctrl driver\n"); 972 973 return 0; 974 } 975