1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Core driver for the S32 CC (Common Chassis) pin controller 4 * 5 * Copyright 2017-2022,2024-2025 NXP 6 * Copyright (C) 2022 SUSE LLC 7 * Copyright 2015-2016 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/err.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/pinctrl/machine.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinctrl.h> 21 #include <linux/pinctrl/pinmux.h> 22 #include <linux/regmap.h> 23 #include <linux/seq_file.h> 24 #include <linux/slab.h> 25 26 #include "../core.h" 27 #include "../pinconf.h" 28 #include "../pinctrl-utils.h" 29 #include "pinctrl-s32.h" 30 31 #define S32_PIN_ID_SHIFT 4 32 #define S32_PIN_ID_MASK GENMASK(31, S32_PIN_ID_SHIFT) 33 34 #define S32_MSCR_SSS_MASK GENMASK(2, 0) 35 #define S32_MSCR_PUS BIT(12) 36 #define S32_MSCR_PUE BIT(13) 37 #define S32_MSCR_SRE(X) (((X) & GENMASK(3, 0)) << 14) 38 #define S32_MSCR_IBE BIT(19) 39 #define S32_MSCR_ODE BIT(20) 40 #define S32_MSCR_OBE BIT(21) 41 42 enum s32_write_type { 43 S32_PINCONF_UPDATE_ONLY, 44 S32_PINCONF_OVERWRITE, 45 }; 46 47 static struct regmap_config s32_regmap_config = { 48 .reg_bits = 32, 49 .val_bits = 32, 50 .reg_stride = 4, 51 }; 52 53 static u32 get_pin_no(u32 pinmux) 54 { 55 return (pinmux & S32_PIN_ID_MASK) >> S32_PIN_ID_SHIFT; 56 } 57 58 static u32 get_pin_func(u32 pinmux) 59 { 60 return pinmux & GENMASK(3, 0); 61 } 62 63 /* 64 * struct s32_pinctrl_mem_region - memory region for a set of SIUL2 registers 65 * @map: regmap used for this range 66 * @pin_range: the pins controlled by these registers 67 * @name: name of the current range 68 */ 69 struct s32_pinctrl_mem_region { 70 struct regmap *map; 71 const struct s32_pin_range *pin_range; 72 char name[8]; 73 }; 74 75 /* 76 * struct gpio_pin_config - holds pin configuration for GPIO's 77 * @pin_id: Pin ID for this GPIO 78 * @config: Pin settings 79 * @list: Linked list entry for each gpio pin 80 */ 81 struct gpio_pin_config { 82 unsigned int pin_id; 83 unsigned int config; 84 struct list_head list; 85 }; 86 87 /* 88 * struct s32_pinctrl_context - pad config save/restore for suspend/resume 89 * @pads: saved values for the pads 90 */ 91 struct s32_pinctrl_context { 92 unsigned int *pads; 93 }; 94 95 /* 96 * struct s32_pinctrl - private driver data 97 * @dev: a pointer back to containing device 98 * @pctl: a pointer to the pinctrl device structure 99 * @regions: reserved memory regions with start/end pin 100 * @info: structure containing information about the pin 101 * @gpio_configs: saved configurations for GPIO pins 102 * @gpio_configs_lock: lock for the `gpio_configs` list 103 * @saved_context: configuration saved over system sleep 104 */ 105 struct s32_pinctrl { 106 struct device *dev; 107 struct pinctrl_dev *pctl; 108 struct s32_pinctrl_mem_region *regions; 109 struct s32_pinctrl_soc_info *info; 110 struct list_head gpio_configs; 111 spinlock_t gpio_configs_lock; 112 #ifdef CONFIG_PM_SLEEP 113 struct s32_pinctrl_context saved_context; 114 #endif 115 }; 116 117 static struct s32_pinctrl_mem_region * 118 s32_get_region(struct pinctrl_dev *pctldev, unsigned int pin) 119 { 120 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 121 const struct s32_pin_range *pin_range; 122 unsigned int mem_regions = ipctl->info->soc_data->mem_regions; 123 unsigned int i; 124 125 for (i = 0; i < mem_regions; i++) { 126 pin_range = ipctl->regions[i].pin_range; 127 if (pin >= pin_range->start && pin <= pin_range->end) 128 return &ipctl->regions[i]; 129 } 130 131 return NULL; 132 } 133 134 static int s32_check_pin(struct pinctrl_dev *pctldev, 135 unsigned int pin) 136 { 137 return s32_get_region(pctldev, pin) ? 0 : -EINVAL; 138 } 139 140 static int s32_regmap_read(struct pinctrl_dev *pctldev, 141 unsigned int pin, unsigned int *val) 142 { 143 struct s32_pinctrl_mem_region *region; 144 unsigned int offset; 145 146 region = s32_get_region(pctldev, pin); 147 if (!region) 148 return -EINVAL; 149 150 offset = (pin - region->pin_range->start) * 151 regmap_get_reg_stride(region->map); 152 153 return regmap_read(region->map, offset, val); 154 } 155 156 static int s32_regmap_write(struct pinctrl_dev *pctldev, 157 unsigned int pin, 158 unsigned int val) 159 { 160 struct s32_pinctrl_mem_region *region; 161 unsigned int offset; 162 163 region = s32_get_region(pctldev, pin); 164 if (!region) 165 return -EINVAL; 166 167 offset = (pin - region->pin_range->start) * 168 regmap_get_reg_stride(region->map); 169 170 return regmap_write(region->map, offset, val); 171 172 } 173 174 static int s32_regmap_update(struct pinctrl_dev *pctldev, unsigned int pin, 175 unsigned int mask, unsigned int val) 176 { 177 struct s32_pinctrl_mem_region *region; 178 unsigned int offset; 179 180 region = s32_get_region(pctldev, pin); 181 if (!region) 182 return -EINVAL; 183 184 offset = (pin - region->pin_range->start) * 185 regmap_get_reg_stride(region->map); 186 187 return regmap_update_bits(region->map, offset, mask, val); 188 } 189 190 static int s32_get_groups_count(struct pinctrl_dev *pctldev) 191 { 192 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 193 const struct s32_pinctrl_soc_info *info = ipctl->info; 194 195 return info->ngroups; 196 } 197 198 static const char *s32_get_group_name(struct pinctrl_dev *pctldev, 199 unsigned int selector) 200 { 201 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 202 const struct s32_pinctrl_soc_info *info = ipctl->info; 203 204 return info->groups[selector].data.name; 205 } 206 207 static int s32_get_group_pins(struct pinctrl_dev *pctldev, 208 unsigned int selector, const unsigned int **pins, 209 unsigned int *npins) 210 { 211 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 212 const struct s32_pinctrl_soc_info *info = ipctl->info; 213 214 *pins = info->groups[selector].data.pins; 215 *npins = info->groups[selector].data.npins; 216 217 return 0; 218 } 219 220 static void s32_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 221 unsigned int offset) 222 { 223 seq_printf(s, "%s", dev_name(pctldev->dev)); 224 } 225 226 static int s32_dt_group_node_to_map(struct pinctrl_dev *pctldev, 227 struct device_node *np, 228 struct pinctrl_map **map, 229 unsigned int *reserved_maps, 230 unsigned int *num_maps, 231 const char *func_name) 232 { 233 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 234 struct device *dev = ipctl->dev; 235 unsigned long *cfgs = NULL; 236 unsigned int n_cfgs, reserve = 1; 237 int n_pins, ret; 238 239 n_pins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32)); 240 if (n_pins < 0) { 241 dev_warn(dev, "Can't find 'pinmux' property in node %pOFn\n", np); 242 } else if (!n_pins) { 243 return -EINVAL; 244 } 245 246 ret = pinconf_generic_parse_dt_config(np, pctldev, &cfgs, &n_cfgs); 247 if (ret) 248 return dev_err_probe(dev, ret, 249 "%pOF: could not parse node property\n", 250 np); 251 252 if (n_cfgs) 253 reserve++; 254 255 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, 256 reserve); 257 if (ret < 0) 258 goto free_cfgs; 259 260 ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, 261 np->name, func_name); 262 if (ret < 0) 263 goto free_cfgs; 264 265 if (n_cfgs) { 266 ret = pinctrl_utils_add_map_configs(pctldev, map, reserved_maps, 267 num_maps, np->name, cfgs, n_cfgs, 268 PIN_MAP_TYPE_CONFIGS_GROUP); 269 if (ret < 0) 270 goto free_cfgs; 271 } 272 273 free_cfgs: 274 kfree(cfgs); 275 return ret; 276 } 277 278 static int s32_dt_node_to_map(struct pinctrl_dev *pctldev, 279 struct device_node *np_config, 280 struct pinctrl_map **map, 281 unsigned int *num_maps) 282 { 283 unsigned int reserved_maps; 284 int ret; 285 286 reserved_maps = 0; 287 *map = NULL; 288 *num_maps = 0; 289 290 for_each_available_child_of_node_scoped(np_config, np) { 291 ret = s32_dt_group_node_to_map(pctldev, np, map, 292 &reserved_maps, num_maps, 293 np_config->name); 294 if (ret < 0) { 295 pinctrl_utils_free_map(pctldev, *map, *num_maps); 296 return ret; 297 } 298 } 299 300 return 0; 301 } 302 303 static const struct pinctrl_ops s32_pctrl_ops = { 304 .get_groups_count = s32_get_groups_count, 305 .get_group_name = s32_get_group_name, 306 .get_group_pins = s32_get_group_pins, 307 .pin_dbg_show = s32_pin_dbg_show, 308 .dt_node_to_map = s32_dt_node_to_map, 309 .dt_free_map = pinctrl_utils_free_map, 310 }; 311 312 static int s32_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector, 313 unsigned int group) 314 { 315 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 316 const struct s32_pinctrl_soc_info *info = ipctl->info; 317 int i, ret; 318 struct s32_pin_group *grp; 319 320 /* 321 * Configure the mux mode for each pin in the group for a specific 322 * function. 323 */ 324 grp = &info->groups[group]; 325 326 dev_dbg(ipctl->dev, "set mux for function %s group %s\n", 327 info->functions[selector].name, grp->data.name); 328 329 /* Check beforehand so we don't have a partial config. */ 330 for (i = 0; i < grp->data.npins; i++) { 331 if (s32_check_pin(pctldev, grp->data.pins[i]) != 0) { 332 dev_err(info->dev, "invalid pin: %u in group: %u\n", 333 grp->data.pins[i], group); 334 return -EINVAL; 335 } 336 } 337 338 for (i = 0, ret = 0; i < grp->data.npins && !ret; i++) { 339 ret = s32_regmap_update(pctldev, grp->data.pins[i], 340 S32_MSCR_SSS_MASK, grp->pin_sss[i]); 341 if (ret) { 342 dev_err(info->dev, "Failed to set pin %u\n", 343 grp->data.pins[i]); 344 return ret; 345 } 346 } 347 348 return 0; 349 } 350 351 static int s32_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 352 { 353 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 354 const struct s32_pinctrl_soc_info *info = ipctl->info; 355 356 return info->nfunctions; 357 } 358 359 static const char *s32_pmx_get_func_name(struct pinctrl_dev *pctldev, 360 unsigned int selector) 361 { 362 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 363 const struct s32_pinctrl_soc_info *info = ipctl->info; 364 365 return info->functions[selector].name; 366 } 367 368 static int s32_pmx_get_groups(struct pinctrl_dev *pctldev, 369 unsigned int selector, 370 const char * const **groups, 371 unsigned int * const num_groups) 372 { 373 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 374 const struct s32_pinctrl_soc_info *info = ipctl->info; 375 376 *groups = info->functions[selector].groups; 377 *num_groups = info->functions[selector].ngroups; 378 379 return 0; 380 } 381 382 static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, 383 struct pinctrl_gpio_range *range, 384 unsigned int offset) 385 { 386 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 387 struct gpio_pin_config *gpio_pin; 388 unsigned int config; 389 unsigned long flags; 390 int ret; 391 392 ret = s32_regmap_read(pctldev, offset, &config); 393 if (ret) 394 return ret; 395 396 /* Save current configuration */ 397 gpio_pin = kmalloc_obj(*gpio_pin); 398 if (!gpio_pin) 399 return -ENOMEM; 400 401 gpio_pin->pin_id = offset; 402 gpio_pin->config = config; 403 INIT_LIST_HEAD(&gpio_pin->list); 404 405 spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); 406 list_add(&gpio_pin->list, &ipctl->gpio_configs); 407 spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); 408 409 /* GPIO pin means SSS = 0 */ 410 config &= ~S32_MSCR_SSS_MASK; 411 412 return s32_regmap_write(pctldev, offset, config); 413 } 414 415 static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 416 struct pinctrl_gpio_range *range, 417 unsigned int offset) 418 { 419 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 420 struct gpio_pin_config *gpio_pin, *tmp; 421 unsigned long flags; 422 int ret; 423 424 spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); 425 426 list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) { 427 if (gpio_pin->pin_id == offset) { 428 ret = s32_regmap_write(pctldev, gpio_pin->pin_id, 429 gpio_pin->config); 430 if (ret != 0) 431 goto unlock; 432 433 list_del(&gpio_pin->list); 434 kfree(gpio_pin); 435 break; 436 } 437 } 438 439 unlock: 440 spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); 441 } 442 443 static int s32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 444 struct pinctrl_gpio_range *range, 445 unsigned int offset, 446 bool input) 447 { 448 /* Always enable IBE for GPIOs. This allows us to read the 449 * actual line value and compare it with the one set. 450 */ 451 unsigned int config = S32_MSCR_IBE; 452 unsigned int mask = S32_MSCR_IBE | S32_MSCR_OBE; 453 454 /* Enable output buffer */ 455 if (!input) 456 config |= S32_MSCR_OBE; 457 458 return s32_regmap_update(pctldev, offset, mask, config); 459 } 460 461 static const struct pinmux_ops s32_pmx_ops = { 462 .get_functions_count = s32_pmx_get_funcs_count, 463 .get_function_name = s32_pmx_get_func_name, 464 .get_function_groups = s32_pmx_get_groups, 465 .set_mux = s32_pmx_set, 466 .gpio_request_enable = s32_pmx_gpio_request_enable, 467 .gpio_disable_free = s32_pmx_gpio_disable_free, 468 .gpio_set_direction = s32_pmx_gpio_set_direction, 469 }; 470 471 /* Set the reserved elements as -1 */ 472 static const int support_slew[] = {208, -1, -1, -1, 166, 150, 133, 83}; 473 474 static int s32_get_slew_regval(int arg) 475 { 476 unsigned int i; 477 478 /* Translate a real slew rate (MHz) to a register value */ 479 for (i = 0; i < ARRAY_SIZE(support_slew); i++) { 480 if (arg == support_slew[i]) 481 return i; 482 } 483 484 return -EINVAL; 485 } 486 487 static void s32_pin_set_pull(enum pin_config_param param, 488 unsigned int *mask, unsigned int *config) 489 { 490 switch (param) { 491 case PIN_CONFIG_BIAS_DISABLE: 492 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 493 *config &= ~(S32_MSCR_PUS | S32_MSCR_PUE); 494 break; 495 case PIN_CONFIG_BIAS_PULL_UP: 496 *config |= S32_MSCR_PUS | S32_MSCR_PUE; 497 break; 498 case PIN_CONFIG_BIAS_PULL_DOWN: 499 *config &= ~S32_MSCR_PUS; 500 *config |= S32_MSCR_PUE; 501 break; 502 default: 503 return; 504 } 505 506 *mask |= S32_MSCR_PUS | S32_MSCR_PUE; 507 } 508 509 static int s32_parse_pincfg(unsigned long pincfg, unsigned int *mask, 510 unsigned int *config) 511 { 512 enum pin_config_param param; 513 u32 arg; 514 int ret; 515 516 param = pinconf_to_config_param(pincfg); 517 arg = pinconf_to_config_argument(pincfg); 518 519 switch (param) { 520 /* All pins are persistent over suspend */ 521 case PIN_CONFIG_PERSIST_STATE: 522 return 0; 523 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 524 *config |= S32_MSCR_ODE; 525 *mask |= S32_MSCR_ODE; 526 break; 527 case PIN_CONFIG_DRIVE_PUSH_PULL: 528 *config &= ~S32_MSCR_ODE; 529 *mask |= S32_MSCR_ODE; 530 break; 531 case PIN_CONFIG_OUTPUT_ENABLE: 532 if (arg) 533 *config |= S32_MSCR_OBE; 534 else 535 *config &= ~S32_MSCR_OBE; 536 *mask |= S32_MSCR_OBE; 537 break; 538 case PIN_CONFIG_INPUT_ENABLE: 539 if (arg) 540 *config |= S32_MSCR_IBE; 541 else 542 *config &= ~S32_MSCR_IBE; 543 *mask |= S32_MSCR_IBE; 544 break; 545 case PIN_CONFIG_SLEW_RATE: 546 ret = s32_get_slew_regval(arg); 547 if (ret < 0) 548 return ret; 549 *config |= S32_MSCR_SRE((u32)ret); 550 *mask |= S32_MSCR_SRE(~0); 551 break; 552 case PIN_CONFIG_BIAS_DISABLE: 553 case PIN_CONFIG_BIAS_PULL_UP: 554 case PIN_CONFIG_BIAS_PULL_DOWN: 555 s32_pin_set_pull(param, mask, config); 556 break; 557 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 558 *config &= ~(S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE); 559 *mask |= S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE; 560 s32_pin_set_pull(param, mask, config); 561 break; 562 default: 563 return -EOPNOTSUPP; 564 } 565 566 return 0; 567 } 568 569 static int s32_pinconf_mscr_write(struct pinctrl_dev *pctldev, 570 unsigned int pin_id, 571 unsigned long *configs, 572 unsigned int num_configs, 573 enum s32_write_type write_type) 574 { 575 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 576 unsigned int config = 0, mask = 0; 577 int i, ret; 578 579 ret = s32_check_pin(pctldev, pin_id); 580 if (ret) 581 return ret; 582 583 dev_dbg(ipctl->dev, "pinconf set pin %s with %u configs\n", 584 pin_get_name(pctldev, pin_id), num_configs); 585 586 for (i = 0; i < num_configs; i++) { 587 ret = s32_parse_pincfg(configs[i], &mask, &config); 588 if (ret) 589 return ret; 590 } 591 592 /* If the MSCR configuration has to be written, 593 * the SSS field should not be touched. 594 */ 595 if (write_type == S32_PINCONF_OVERWRITE) 596 mask = (unsigned int)~S32_MSCR_SSS_MASK; 597 598 if (!config && !mask) 599 return 0; 600 601 if (write_type == S32_PINCONF_OVERWRITE) 602 dev_dbg(ipctl->dev, "set: pin %u cfg 0x%x\n", pin_id, config); 603 else 604 dev_dbg(ipctl->dev, "update: pin %u cfg 0x%x\n", pin_id, 605 config); 606 607 return s32_regmap_update(pctldev, pin_id, mask, config); 608 } 609 610 static int s32_pinconf_get(struct pinctrl_dev *pctldev, 611 unsigned int pin_id, 612 unsigned long *config) 613 { 614 return s32_regmap_read(pctldev, pin_id, (unsigned int *)config); 615 } 616 617 static int s32_pinconf_set(struct pinctrl_dev *pctldev, 618 unsigned int pin_id, unsigned long *configs, 619 unsigned int num_configs) 620 { 621 return s32_pinconf_mscr_write(pctldev, pin_id, configs, 622 num_configs, S32_PINCONF_UPDATE_ONLY); 623 } 624 625 static int s32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int selector, 626 unsigned long *configs, unsigned int num_configs) 627 { 628 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 629 const struct s32_pinctrl_soc_info *info = ipctl->info; 630 struct s32_pin_group *grp; 631 int i, ret; 632 633 grp = &info->groups[selector]; 634 for (i = 0; i < grp->data.npins; i++) { 635 ret = s32_pinconf_mscr_write(pctldev, grp->data.pins[i], 636 configs, num_configs, S32_PINCONF_OVERWRITE); 637 if (ret) 638 return ret; 639 } 640 641 return 0; 642 } 643 644 static void s32_pinconf_dbg_show(struct pinctrl_dev *pctldev, 645 struct seq_file *s, unsigned int pin_id) 646 { 647 unsigned int config; 648 int ret; 649 650 ret = s32_regmap_read(pctldev, pin_id, &config); 651 if (ret) 652 return; 653 654 seq_printf(s, "0x%x", config); 655 } 656 657 static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 658 struct seq_file *s, unsigned int selector) 659 { 660 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 661 const struct s32_pinctrl_soc_info *info = ipctl->info; 662 struct s32_pin_group *grp; 663 unsigned int config; 664 const char *name; 665 int i, ret; 666 667 seq_puts(s, "\n"); 668 grp = &info->groups[selector]; 669 for (i = 0; i < grp->data.npins; i++) { 670 name = pin_get_name(pctldev, grp->data.pins[i]); 671 ret = s32_regmap_read(pctldev, grp->data.pins[i], &config); 672 if (ret) 673 return; 674 seq_printf(s, "%s: 0x%x\n", name, config); 675 } 676 } 677 678 static const struct pinconf_ops s32_pinconf_ops = { 679 .pin_config_get = s32_pinconf_get, 680 .pin_config_set = s32_pinconf_set, 681 .pin_config_group_set = s32_pconf_group_set, 682 .pin_config_dbg_show = s32_pinconf_dbg_show, 683 .pin_config_group_dbg_show = s32_pinconf_group_dbg_show, 684 }; 685 686 #ifdef CONFIG_PM_SLEEP 687 static bool s32_pinctrl_should_save(struct s32_pinctrl *ipctl, 688 unsigned int pin) 689 { 690 const struct pin_desc *pd = pin_desc_get(ipctl->pctl, pin); 691 692 if (!pd) 693 return false; 694 695 /* 696 * Only restore the pin if it is actually in use by the kernel (or 697 * by userspace). 698 */ 699 if (pd->mux_owner || pd->gpio_owner) 700 return true; 701 702 return false; 703 } 704 705 int s32_pinctrl_suspend(struct device *dev) 706 { 707 struct platform_device *pdev = to_platform_device(dev); 708 struct s32_pinctrl *ipctl = platform_get_drvdata(pdev); 709 const struct pinctrl_pin_desc *pin; 710 const struct s32_pinctrl_soc_info *info = ipctl->info; 711 struct s32_pinctrl_context *saved_context = &ipctl->saved_context; 712 int i; 713 int ret; 714 unsigned int config; 715 716 for (i = 0; i < info->soc_data->npins; i++) { 717 pin = &info->soc_data->pins[i]; 718 719 if (!s32_pinctrl_should_save(ipctl, pin->number)) 720 continue; 721 722 ret = s32_regmap_read(ipctl->pctl, pin->number, &config); 723 if (ret) 724 return -EINVAL; 725 726 saved_context->pads[i] = config; 727 } 728 729 return 0; 730 } 731 732 int s32_pinctrl_resume(struct device *dev) 733 { 734 struct platform_device *pdev = to_platform_device(dev); 735 struct s32_pinctrl *ipctl = platform_get_drvdata(pdev); 736 const struct s32_pinctrl_soc_info *info = ipctl->info; 737 const struct pinctrl_pin_desc *pin; 738 struct s32_pinctrl_context *saved_context = &ipctl->saved_context; 739 int ret, i; 740 741 for (i = 0; i < info->soc_data->npins; i++) { 742 pin = &info->soc_data->pins[i]; 743 744 if (!s32_pinctrl_should_save(ipctl, pin->number)) 745 continue; 746 747 ret = s32_regmap_write(ipctl->pctl, pin->number, 748 saved_context->pads[i]); 749 if (ret) 750 return ret; 751 } 752 753 return 0; 754 } 755 #endif 756 757 static int s32_pinctrl_parse_groups(struct device_node *np, 758 struct s32_pin_group *grp, 759 struct s32_pinctrl_soc_info *info) 760 { 761 struct device *dev; 762 unsigned int *pins, *sss; 763 int i, npins; 764 u32 pinmux; 765 766 dev = info->dev; 767 768 dev_dbg(dev, "group: %pOFn\n", np); 769 770 /* Initialise group */ 771 grp->data.name = np->name; 772 773 npins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32)); 774 if (npins < 0) 775 return dev_err_probe(dev, -EINVAL, 776 "Failed to read 'pinmux' in node %s\n", 777 grp->data.name); 778 779 if (!npins) 780 return dev_err_probe(dev, -EINVAL, 781 "The group %s has no pins\n", 782 grp->data.name); 783 784 grp->data.npins = npins; 785 786 pins = devm_kcalloc(info->dev, npins, sizeof(*pins), GFP_KERNEL); 787 sss = devm_kcalloc(info->dev, npins, sizeof(*sss), GFP_KERNEL); 788 if (!pins || !sss) 789 return -ENOMEM; 790 791 i = 0; 792 of_property_for_each_u32(np, "pinmux", pinmux) { 793 pins[i] = get_pin_no(pinmux); 794 sss[i] = get_pin_func(pinmux); 795 796 dev_dbg(info->dev, "pin: 0x%x, sss: 0x%x", pins[i], sss[i]); 797 i++; 798 } 799 800 grp->data.pins = pins; 801 grp->pin_sss = sss; 802 803 return 0; 804 } 805 806 static int s32_pinctrl_parse_functions(struct device_node *np, 807 struct s32_pinctrl_soc_info *info, 808 u32 index) 809 { 810 struct pinfunction *func; 811 struct s32_pin_group *grp; 812 const char **groups; 813 u32 i = 0; 814 int ret = 0; 815 816 dev_dbg(info->dev, "parse function(%u): %pOFn\n", index, np); 817 818 func = &info->functions[index]; 819 820 /* Initialise function */ 821 func->name = np->name; 822 func->ngroups = of_get_child_count(np); 823 if (func->ngroups == 0) 824 return dev_err_probe(info->dev, -EINVAL, 825 "No groups defined in %pOF\n", np); 826 827 groups = devm_kcalloc(info->dev, func->ngroups, 828 sizeof(*func->groups), GFP_KERNEL); 829 if (!groups) 830 return -ENOMEM; 831 832 for_each_child_of_node_scoped(np, child) { 833 groups[i] = child->name; 834 grp = &info->groups[info->grp_index++]; 835 ret = s32_pinctrl_parse_groups(child, grp, info); 836 if (ret) 837 return ret; 838 i++; 839 } 840 841 func->groups = groups; 842 843 return 0; 844 } 845 846 static int s32_pinctrl_probe_dt(struct platform_device *pdev, 847 struct s32_pinctrl *ipctl) 848 { 849 struct s32_pinctrl_soc_info *info = ipctl->info; 850 struct device_node *np = pdev->dev.of_node; 851 struct resource *res; 852 struct regmap *map; 853 void __iomem *base; 854 unsigned int mem_regions = info->soc_data->mem_regions; 855 int ret; 856 u32 nfuncs = 0; 857 u32 i = 0; 858 859 if (!np) 860 return -ENODEV; 861 862 if (mem_regions == 0 || mem_regions >= 10000) { 863 dev_err(&pdev->dev, "mem_regions is invalid: %u\n", mem_regions); 864 return -EINVAL; 865 } 866 867 ipctl->regions = devm_kcalloc(&pdev->dev, mem_regions, 868 sizeof(*ipctl->regions), GFP_KERNEL); 869 if (!ipctl->regions) 870 return -ENOMEM; 871 872 for (i = 0; i < mem_regions; i++) { 873 base = devm_platform_get_and_ioremap_resource(pdev, i, &res); 874 if (IS_ERR(base)) 875 return PTR_ERR(base); 876 877 snprintf(ipctl->regions[i].name, 878 sizeof(ipctl->regions[i].name), "map%u", i); 879 880 s32_regmap_config.name = ipctl->regions[i].name; 881 s32_regmap_config.max_register = resource_size(res) - 882 s32_regmap_config.reg_stride; 883 884 map = devm_regmap_init_mmio(&pdev->dev, base, 885 &s32_regmap_config); 886 if (IS_ERR(map)) { 887 dev_err(&pdev->dev, "Failed to init regmap[%u]\n", i); 888 return PTR_ERR(map); 889 } 890 891 ipctl->regions[i].map = map; 892 ipctl->regions[i].pin_range = &info->soc_data->mem_pin_ranges[i]; 893 } 894 895 nfuncs = of_get_child_count(np); 896 if (nfuncs <= 0) 897 return dev_err_probe(&pdev->dev, -EINVAL, 898 "No functions defined\n"); 899 900 info->nfunctions = nfuncs; 901 info->functions = devm_kcalloc(&pdev->dev, nfuncs, 902 sizeof(*info->functions), GFP_KERNEL); 903 if (!info->functions) 904 return -ENOMEM; 905 906 info->ngroups = 0; 907 for_each_child_of_node_scoped(np, child) 908 info->ngroups += of_get_child_count(child); 909 910 info->groups = devm_kcalloc(&pdev->dev, info->ngroups, 911 sizeof(*info->groups), GFP_KERNEL); 912 if (!info->groups) 913 return -ENOMEM; 914 915 i = 0; 916 for_each_child_of_node_scoped(np, child) { 917 ret = s32_pinctrl_parse_functions(child, info, i++); 918 if (ret) 919 return ret; 920 } 921 922 return 0; 923 } 924 925 int s32_pinctrl_probe(struct platform_device *pdev, 926 const struct s32_pinctrl_soc_data *soc_data) 927 { 928 #ifdef CONFIG_PM_SLEEP 929 struct s32_pinctrl_context *saved_context; 930 #endif 931 struct pinctrl_desc *s32_pinctrl_desc; 932 struct s32_pinctrl_soc_info *info; 933 struct s32_pinctrl *ipctl; 934 int ret; 935 936 if (!soc_data || !soc_data->pins || !soc_data->npins) 937 return dev_err_probe(&pdev->dev, -EINVAL, 938 "Wrong pinctrl info\n"); 939 940 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 941 if (!info) 942 return -ENOMEM; 943 944 info->soc_data = soc_data; 945 info->dev = &pdev->dev; 946 947 /* Create state holders etc for this driver */ 948 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 949 if (!ipctl) 950 return -ENOMEM; 951 952 ipctl->info = info; 953 ipctl->dev = info->dev; 954 platform_set_drvdata(pdev, ipctl); 955 956 INIT_LIST_HEAD(&ipctl->gpio_configs); 957 spin_lock_init(&ipctl->gpio_configs_lock); 958 959 s32_pinctrl_desc = 960 devm_kzalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL); 961 if (!s32_pinctrl_desc) 962 return -ENOMEM; 963 964 s32_pinctrl_desc->name = dev_name(&pdev->dev); 965 s32_pinctrl_desc->pins = info->soc_data->pins; 966 s32_pinctrl_desc->npins = info->soc_data->npins; 967 s32_pinctrl_desc->pctlops = &s32_pctrl_ops; 968 s32_pinctrl_desc->pmxops = &s32_pmx_ops; 969 s32_pinctrl_desc->confops = &s32_pinconf_ops; 970 s32_pinctrl_desc->owner = THIS_MODULE; 971 972 ret = s32_pinctrl_probe_dt(pdev, ipctl); 973 if (ret) 974 return dev_err_probe(&pdev->dev, ret, 975 "Fail to probe dt properties\n"); 976 977 ret = devm_pinctrl_register_and_init(&pdev->dev, s32_pinctrl_desc, 978 ipctl, &ipctl->pctl); 979 if (ret) 980 return dev_err_probe(&pdev->dev, ret, 981 "Could not register s32 pinctrl driver\n"); 982 983 #ifdef CONFIG_PM_SLEEP 984 saved_context = &ipctl->saved_context; 985 saved_context->pads = 986 devm_kcalloc(&pdev->dev, info->soc_data->npins, 987 sizeof(*saved_context->pads), 988 GFP_KERNEL); 989 if (!saved_context->pads) 990 return -ENOMEM; 991 #endif 992 993 ret = pinctrl_enable(ipctl->pctl); 994 if (ret) 995 return dev_err_probe(&pdev->dev, ret, 996 "Failed to enable pinctrl\n"); 997 998 dev_info(&pdev->dev, "Initialized S32 pinctrl driver\n"); 999 1000 return 0; 1001 } 1002