1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2016-2018 Nuvoton Technology corporation. 3 // Copyright (c) 2016, Dell Inc 4 // Copyright (c) 2021-2022 Jonathan Neuschäfer 5 // 6 // This driver uses the following registers: 7 // - Pin mux registers, in the GCR (general control registers) block 8 // - GPIO registers, specific to each GPIO bank 9 // - GPIO event (interrupt) registers, located centrally in the GPIO register 10 // block, shared between all GPIO banks 11 12 #include <linux/device.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/gpio/generic.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/platform_device.h> 21 #include <linux/property.h> 22 #include <linux/regmap.h> 23 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinmux.h> 28 29 #include "../core.h" 30 31 /* GCR registers */ 32 #define WPCM450_GCR_MFSEL1 0x0c 33 #define WPCM450_GCR_MFSEL2 0x10 34 #define WPCM450_GCR_NONE 0 35 36 /* GPIO event (interrupt) registers */ 37 #define WPCM450_GPEVTYPE 0x00 38 #define WPCM450_GPEVPOL 0x04 39 #define WPCM450_GPEVDBNC 0x08 40 #define WPCM450_GPEVEN 0x0c 41 #define WPCM450_GPEVST 0x10 42 43 #define WPCM450_NUM_BANKS 8 44 #define WPCM450_NUM_GPIOS 128 45 #define WPCM450_NUM_GPIO_IRQS 4 46 47 struct wpcm450_pinctrl; 48 struct wpcm450_bank; 49 50 struct wpcm450_gpio { 51 struct gpio_generic_chip chip; 52 struct wpcm450_pinctrl *pctrl; 53 const struct wpcm450_bank *bank; 54 }; 55 56 struct wpcm450_pinctrl { 57 struct pinctrl_dev *pctldev; 58 struct device *dev; 59 struct irq_domain *domain; 60 struct regmap *gcr_regmap; 61 void __iomem *gpio_base; 62 struct wpcm450_gpio gpio_bank[WPCM450_NUM_BANKS]; 63 unsigned long both_edges; 64 65 /* 66 * This spin lock protects registers and struct wpcm450_pinctrl fields 67 * against concurrent access. 68 */ 69 raw_spinlock_t lock; 70 }; 71 72 struct wpcm450_bank { 73 /* Range of GPIOs in this port */ 74 u8 base; 75 u8 length; 76 77 /* Register offsets (0 = register doesn't exist in this port) */ 78 u8 cfg0, cfg1, cfg2; 79 u8 blink; 80 u8 dataout, datain; 81 82 /* Interrupt bit mapping */ 83 u8 first_irq_bit; /* First bit in GPEVST that belongs to this bank */ 84 u8 num_irqs; /* Number of IRQ-capable GPIOs in this bank */ 85 u8 first_irq_gpio; /* First IRQ-capable GPIO in this bank */ 86 }; 87 88 static const struct wpcm450_bank wpcm450_banks[WPCM450_NUM_BANKS] = { 89 /* range cfg0 cfg1 cfg2 blink out in IRQ map */ 90 { 0, 16, 0x14, 0x18, 0, 0, 0x1c, 0x20, 0, 16, 0 }, 91 { 16, 16, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38, 16, 2, 8 }, 92 { 32, 16, 0x3c, 0x40, 0x44, 0, 0x48, 0x4c, 0, 0, 0 }, 93 { 48, 16, 0x50, 0x54, 0x58, 0, 0x5c, 0x60, 0, 0, 0 }, 94 { 64, 16, 0x64, 0x68, 0x6c, 0, 0x70, 0x74, 0, 0, 0 }, 95 { 80, 16, 0x78, 0x7c, 0x80, 0, 0x84, 0x88, 0, 0, 0 }, 96 { 96, 18, 0, 0, 0, 0, 0, 0x8c, 0, 0, 0 }, 97 { 114, 14, 0x90, 0x94, 0x98, 0, 0x9c, 0xa0, 0, 0, 0 }, 98 }; 99 100 static int wpcm450_gpio_irq_bitnum(struct wpcm450_gpio *gpio, struct irq_data *d) 101 { 102 const struct wpcm450_bank *bank = gpio->bank; 103 int hwirq = irqd_to_hwirq(d); 104 105 if (hwirq < bank->first_irq_gpio) 106 return -EINVAL; 107 108 if (hwirq - bank->first_irq_gpio >= bank->num_irqs) 109 return -EINVAL; 110 111 return hwirq - bank->first_irq_gpio + bank->first_irq_bit; 112 } 113 114 static int wpcm450_irq_bitnum_to_gpio(struct wpcm450_gpio *gpio, int bitnum) 115 { 116 const struct wpcm450_bank *bank = gpio->bank; 117 118 if (bitnum < bank->first_irq_bit) 119 return -EINVAL; 120 121 if (bitnum - bank->first_irq_bit > bank->num_irqs) 122 return -EINVAL; 123 124 return bitnum - bank->first_irq_bit + bank->first_irq_gpio; 125 } 126 127 static void wpcm450_gpio_irq_ack(struct irq_data *d) 128 { 129 struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 130 struct wpcm450_pinctrl *pctrl = gpio->pctrl; 131 unsigned long flags; 132 int bit; 133 134 bit = wpcm450_gpio_irq_bitnum(gpio, d); 135 if (bit < 0) 136 return; 137 138 raw_spin_lock_irqsave(&pctrl->lock, flags); 139 iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST); 140 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 141 } 142 143 static void wpcm450_gpio_irq_mask(struct irq_data *d) 144 { 145 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 146 struct wpcm450_gpio *gpio = gpiochip_get_data(gc); 147 struct wpcm450_pinctrl *pctrl = gpio->pctrl; 148 unsigned long flags; 149 unsigned long even; 150 int bit; 151 152 bit = wpcm450_gpio_irq_bitnum(gpio, d); 153 if (bit < 0) 154 return; 155 156 raw_spin_lock_irqsave(&pctrl->lock, flags); 157 even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN); 158 __assign_bit(bit, &even, 0); 159 iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN); 160 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 161 162 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 163 } 164 165 static void wpcm450_gpio_irq_unmask(struct irq_data *d) 166 { 167 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 168 struct wpcm450_gpio *gpio = gpiochip_get_data(gc); 169 struct wpcm450_pinctrl *pctrl = gpio->pctrl; 170 unsigned long flags; 171 unsigned long even; 172 int bit; 173 174 bit = wpcm450_gpio_irq_bitnum(gpio, d); 175 if (bit < 0) 176 return; 177 178 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 179 180 raw_spin_lock_irqsave(&pctrl->lock, flags); 181 even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN); 182 __assign_bit(bit, &even, 1); 183 iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN); 184 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 185 } 186 187 /* 188 * FIXME: This is an implementation of the gpio_chip->get() function, for use 189 * in wpcm450_gpio_fix_evpol(). It was implemented back when gpio-mmio used a 190 * regular spinlock internally, while wpcm450_gpio_fix_evpol() needed to work 191 * in contexts with a raw spinlock held. Since then, the gpio generic chip has 192 * been switched to using a raw spinlock so this should be converted to using 193 * the locking interfaces provided in linux/gpio/gneneric.h. 194 */ 195 static int wpcm450_gpio_get(struct wpcm450_gpio *gpio, int offset) 196 { 197 void __iomem *reg = gpio->pctrl->gpio_base + gpio->bank->datain; 198 unsigned long flags; 199 u32 level; 200 201 raw_spin_lock_irqsave(&gpio->pctrl->lock, flags); 202 level = !!(ioread32(reg) & BIT(offset)); 203 raw_spin_unlock_irqrestore(&gpio->pctrl->lock, flags); 204 205 return level; 206 } 207 208 /* 209 * Since the GPIO controller does not support dual-edge triggered interrupts 210 * (IRQ_TYPE_EDGE_BOTH), they are emulated using rising/falling edge triggered 211 * interrupts. wpcm450_gpio_fix_evpol sets the interrupt polarity for the 212 * specified emulated dual-edge triggered interrupts, so that the next edge can 213 * be detected. 214 */ 215 static void wpcm450_gpio_fix_evpol(struct wpcm450_gpio *gpio, unsigned long all) 216 { 217 struct wpcm450_pinctrl *pctrl = gpio->pctrl; 218 unsigned int bit; 219 220 for_each_set_bit(bit, &all, 32) { 221 int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit); 222 unsigned long evpol; 223 unsigned long flags; 224 int level; 225 226 do { 227 level = wpcm450_gpio_get(gpio, offset); 228 229 /* Switch event polarity to the opposite of the current level */ 230 raw_spin_lock_irqsave(&pctrl->lock, flags); 231 evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL); 232 __assign_bit(bit, &evpol, !level); 233 iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL); 234 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 235 236 } while (wpcm450_gpio_get(gpio, offset) != level); 237 } 238 } 239 240 static int wpcm450_gpio_set_irq_type(struct irq_data *d, unsigned int flow_type) 241 { 242 struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 243 struct wpcm450_pinctrl *pctrl = gpio->pctrl; 244 unsigned long evtype, evpol; 245 unsigned long flags; 246 int ret = 0; 247 int bit; 248 249 bit = wpcm450_gpio_irq_bitnum(gpio, d); 250 if (bit < 0) 251 return bit; 252 253 irq_set_handler_locked(d, handle_level_irq); 254 255 raw_spin_lock_irqsave(&pctrl->lock, flags); 256 evtype = ioread32(pctrl->gpio_base + WPCM450_GPEVTYPE); 257 evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL); 258 __assign_bit(bit, &pctrl->both_edges, 0); 259 switch (flow_type) { 260 case IRQ_TYPE_LEVEL_LOW: 261 __assign_bit(bit, &evtype, 1); 262 __assign_bit(bit, &evpol, 0); 263 break; 264 case IRQ_TYPE_LEVEL_HIGH: 265 __assign_bit(bit, &evtype, 1); 266 __assign_bit(bit, &evpol, 1); 267 break; 268 case IRQ_TYPE_EDGE_FALLING: 269 __assign_bit(bit, &evtype, 0); 270 __assign_bit(bit, &evpol, 0); 271 break; 272 case IRQ_TYPE_EDGE_RISING: 273 __assign_bit(bit, &evtype, 0); 274 __assign_bit(bit, &evpol, 1); 275 break; 276 case IRQ_TYPE_EDGE_BOTH: 277 __assign_bit(bit, &evtype, 0); 278 __assign_bit(bit, &pctrl->both_edges, 1); 279 break; 280 default: 281 ret = -EINVAL; 282 } 283 iowrite32(evtype, pctrl->gpio_base + WPCM450_GPEVTYPE); 284 iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL); 285 286 /* clear the event status for good measure */ 287 iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST); 288 289 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 290 291 /* fix event polarity after clearing event status */ 292 wpcm450_gpio_fix_evpol(gpio, BIT(bit)); 293 294 return ret; 295 } 296 297 static const struct irq_chip wpcm450_gpio_irqchip = { 298 .name = "WPCM450-GPIO-IRQ", 299 .irq_ack = wpcm450_gpio_irq_ack, 300 .irq_unmask = wpcm450_gpio_irq_unmask, 301 .irq_mask = wpcm450_gpio_irq_mask, 302 .irq_set_type = wpcm450_gpio_set_irq_type, 303 .flags = IRQCHIP_IMMUTABLE, 304 GPIOCHIP_IRQ_RESOURCE_HELPERS, 305 }; 306 307 static void wpcm450_gpio_irqhandler(struct irq_desc *desc) 308 { 309 struct wpcm450_gpio *gpio = gpiochip_get_data(irq_desc_get_handler_data(desc)); 310 struct wpcm450_pinctrl *pctrl = gpio->pctrl; 311 struct irq_chip *chip = irq_desc_get_chip(desc); 312 unsigned long pending; 313 unsigned long flags; 314 unsigned long ours; 315 unsigned int bit; 316 317 ours = GENMASK(gpio->bank->num_irqs - 1, 0) << gpio->bank->first_irq_bit; 318 319 raw_spin_lock_irqsave(&pctrl->lock, flags); 320 321 pending = ioread32(pctrl->gpio_base + WPCM450_GPEVST); 322 pending &= ioread32(pctrl->gpio_base + WPCM450_GPEVEN); 323 pending &= ours; 324 325 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 326 327 if (pending & pctrl->both_edges) 328 wpcm450_gpio_fix_evpol(gpio, pending & pctrl->both_edges); 329 330 chained_irq_enter(chip, desc); 331 for_each_set_bit(bit, &pending, 32) { 332 int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit); 333 334 generic_handle_domain_irq(gpio->chip.gc.irq.domain, offset); 335 } 336 chained_irq_exit(chip, desc); 337 } 338 339 static int smb0_pins[] = { 115, 114 }; 340 static int smb1_pins[] = { 117, 116 }; 341 static int smb2_pins[] = { 119, 118 }; 342 static int smb3_pins[] = { 30, 31 }; 343 static int smb4_pins[] = { 28, 29 }; 344 static int smb5_pins[] = { 26, 27 }; 345 346 static int scs1_pins[] = { 32 }; 347 static int scs2_pins[] = { 33 }; 348 static int scs3_pins[] = { 34 }; 349 350 static int bsp_pins[] = { 41, 42 }; 351 static int hsp1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 }; 352 static int hsp2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 }; 353 354 static int r1err_pins[] = { 56 }; 355 static int r1md_pins[] = { 57, 58 }; 356 static int rmii2_pins[] = { 84, 85, 86, 87, 88, 89 }; 357 static int r2err_pins[] = { 90 }; 358 static int r2md_pins[] = { 91, 92 }; 359 360 static int kbcc_pins[] = { 94, 93 }; 361 static int clko_pins[] = { 96 }; 362 static int smi_pins[] = { 97 }; 363 static int uinc_pins[] = { 19 }; 364 static int mben_pins[] = {}; 365 366 static int gspi_pins[] = { 12, 13, 14, 15 }; 367 static int sspi_pins[] = { 12, 13, 14, 15 }; 368 369 static int xcs1_pins[] = { 35 }; 370 static int xcs2_pins[] = { 36 }; 371 372 static int sdio_pins[] = { 7, 22, 43, 44, 45, 46, 47, 60 }; 373 374 static int fi0_pins[] = { 64 }; 375 static int fi1_pins[] = { 65 }; 376 static int fi2_pins[] = { 66 }; 377 static int fi3_pins[] = { 67 }; 378 static int fi4_pins[] = { 68 }; 379 static int fi5_pins[] = { 69 }; 380 static int fi6_pins[] = { 70 }; 381 static int fi7_pins[] = { 71 }; 382 static int fi8_pins[] = { 72 }; 383 static int fi9_pins[] = { 73 }; 384 static int fi10_pins[] = { 74 }; 385 static int fi11_pins[] = { 75 }; 386 static int fi12_pins[] = { 76 }; 387 static int fi13_pins[] = { 77 }; 388 static int fi14_pins[] = { 78 }; 389 static int fi15_pins[] = { 79 }; 390 391 static int pwm0_pins[] = { 80 }; 392 static int pwm1_pins[] = { 81 }; 393 static int pwm2_pins[] = { 82 }; 394 static int pwm3_pins[] = { 83 }; 395 static int pwm4_pins[] = { 20 }; 396 static int pwm5_pins[] = { 21 }; 397 static int pwm6_pins[] = { 16 }; 398 static int pwm7_pins[] = { 17 }; 399 400 static int hg0_pins[] = { 20 }; 401 static int hg1_pins[] = { 21 }; 402 static int hg2_pins[] = { 22 }; 403 static int hg3_pins[] = { 23 }; 404 static int hg4_pins[] = { 24 }; 405 static int hg5_pins[] = { 25 }; 406 static int hg6_pins[] = { 59 }; 407 static int hg7_pins[] = { 60 }; 408 409 #define WPCM450_GRPS \ 410 WPCM450_GRP(smb3), \ 411 WPCM450_GRP(smb4), \ 412 WPCM450_GRP(smb5), \ 413 WPCM450_GRP(scs1), \ 414 WPCM450_GRP(scs2), \ 415 WPCM450_GRP(scs3), \ 416 WPCM450_GRP(smb0), \ 417 WPCM450_GRP(smb1), \ 418 WPCM450_GRP(smb2), \ 419 WPCM450_GRP(bsp), \ 420 WPCM450_GRP(hsp1), \ 421 WPCM450_GRP(hsp2), \ 422 WPCM450_GRP(r1err), \ 423 WPCM450_GRP(r1md), \ 424 WPCM450_GRP(rmii2), \ 425 WPCM450_GRP(r2err), \ 426 WPCM450_GRP(r2md), \ 427 WPCM450_GRP(kbcc), \ 428 WPCM450_GRP(clko), \ 429 WPCM450_GRP(smi), \ 430 WPCM450_GRP(uinc), \ 431 WPCM450_GRP(gspi), \ 432 WPCM450_GRP(mben), \ 433 WPCM450_GRP(xcs2), \ 434 WPCM450_GRP(xcs1), \ 435 WPCM450_GRP(sdio), \ 436 WPCM450_GRP(sspi), \ 437 WPCM450_GRP(fi0), \ 438 WPCM450_GRP(fi1), \ 439 WPCM450_GRP(fi2), \ 440 WPCM450_GRP(fi3), \ 441 WPCM450_GRP(fi4), \ 442 WPCM450_GRP(fi5), \ 443 WPCM450_GRP(fi6), \ 444 WPCM450_GRP(fi7), \ 445 WPCM450_GRP(fi8), \ 446 WPCM450_GRP(fi9), \ 447 WPCM450_GRP(fi10), \ 448 WPCM450_GRP(fi11), \ 449 WPCM450_GRP(fi12), \ 450 WPCM450_GRP(fi13), \ 451 WPCM450_GRP(fi14), \ 452 WPCM450_GRP(fi15), \ 453 WPCM450_GRP(pwm0), \ 454 WPCM450_GRP(pwm1), \ 455 WPCM450_GRP(pwm2), \ 456 WPCM450_GRP(pwm3), \ 457 WPCM450_GRP(pwm4), \ 458 WPCM450_GRP(pwm5), \ 459 WPCM450_GRP(pwm6), \ 460 WPCM450_GRP(pwm7), \ 461 WPCM450_GRP(hg0), \ 462 WPCM450_GRP(hg1), \ 463 WPCM450_GRP(hg2), \ 464 WPCM450_GRP(hg3), \ 465 WPCM450_GRP(hg4), \ 466 WPCM450_GRP(hg5), \ 467 WPCM450_GRP(hg6), \ 468 WPCM450_GRP(hg7), \ 469 470 enum { 471 #define WPCM450_GRP(x) fn_ ## x 472 WPCM450_GRPS 473 /* add placeholder for none/gpio */ 474 WPCM450_GRP(gpio), 475 WPCM450_GRP(none), 476 #undef WPCM450_GRP 477 }; 478 479 static const struct pingroup wpcm450_groups[] = { 480 #define WPCM450_GRP(x) PINCTRL_PINGROUP(#x, x ## _pins, ARRAY_SIZE(x ## _pins)) 481 WPCM450_GRPS 482 #undef WPCM450_GRP 483 }; 484 485 #define WPCM450_SFUNC(a) WPCM450_FUNC(a, #a) 486 #define WPCM450_FUNC(a, b...) static const char *a ## _grp[] = { b } 487 488 WPCM450_SFUNC(smb3); 489 WPCM450_SFUNC(smb4); 490 WPCM450_SFUNC(smb5); 491 WPCM450_SFUNC(scs1); 492 WPCM450_SFUNC(scs2); 493 WPCM450_SFUNC(scs3); 494 WPCM450_SFUNC(smb0); 495 WPCM450_SFUNC(smb1); 496 WPCM450_SFUNC(smb2); 497 WPCM450_SFUNC(bsp); 498 WPCM450_SFUNC(hsp1); 499 WPCM450_SFUNC(hsp2); 500 WPCM450_SFUNC(r1err); 501 WPCM450_SFUNC(r1md); 502 WPCM450_SFUNC(rmii2); 503 WPCM450_SFUNC(r2err); 504 WPCM450_SFUNC(r2md); 505 WPCM450_SFUNC(kbcc); 506 WPCM450_SFUNC(clko); 507 WPCM450_SFUNC(smi); 508 WPCM450_SFUNC(uinc); 509 WPCM450_SFUNC(gspi); 510 WPCM450_SFUNC(mben); 511 WPCM450_SFUNC(xcs2); 512 WPCM450_SFUNC(xcs1); 513 WPCM450_SFUNC(sdio); 514 WPCM450_SFUNC(sspi); 515 WPCM450_SFUNC(fi0); 516 WPCM450_SFUNC(fi1); 517 WPCM450_SFUNC(fi2); 518 WPCM450_SFUNC(fi3); 519 WPCM450_SFUNC(fi4); 520 WPCM450_SFUNC(fi5); 521 WPCM450_SFUNC(fi6); 522 WPCM450_SFUNC(fi7); 523 WPCM450_SFUNC(fi8); 524 WPCM450_SFUNC(fi9); 525 WPCM450_SFUNC(fi10); 526 WPCM450_SFUNC(fi11); 527 WPCM450_SFUNC(fi12); 528 WPCM450_SFUNC(fi13); 529 WPCM450_SFUNC(fi14); 530 WPCM450_SFUNC(fi15); 531 WPCM450_SFUNC(pwm0); 532 WPCM450_SFUNC(pwm1); 533 WPCM450_SFUNC(pwm2); 534 WPCM450_SFUNC(pwm3); 535 WPCM450_SFUNC(pwm4); 536 WPCM450_SFUNC(pwm5); 537 WPCM450_SFUNC(pwm6); 538 WPCM450_SFUNC(pwm7); 539 WPCM450_SFUNC(hg0); 540 WPCM450_SFUNC(hg1); 541 WPCM450_SFUNC(hg2); 542 WPCM450_SFUNC(hg3); 543 WPCM450_SFUNC(hg4); 544 WPCM450_SFUNC(hg5); 545 WPCM450_SFUNC(hg6); 546 WPCM450_SFUNC(hg7); 547 548 #define WPCM450_GRP(x) #x 549 WPCM450_FUNC(gpio, WPCM450_GRPS); 550 #undef WPCM450_GRP 551 552 /* Function names */ 553 static struct pinfunction wpcm450_funcs[] = { 554 #define WPCM450_MKFUNC(nm) PINCTRL_PINFUNCTION(#nm, nm ## _grp, ARRAY_SIZE(nm ## _grp)) 555 WPCM450_MKFUNC(smb3), 556 WPCM450_MKFUNC(smb4), 557 WPCM450_MKFUNC(smb5), 558 WPCM450_MKFUNC(scs1), 559 WPCM450_MKFUNC(scs2), 560 WPCM450_MKFUNC(scs3), 561 WPCM450_MKFUNC(smb0), 562 WPCM450_MKFUNC(smb1), 563 WPCM450_MKFUNC(smb2), 564 WPCM450_MKFUNC(bsp), 565 WPCM450_MKFUNC(hsp1), 566 WPCM450_MKFUNC(hsp2), 567 WPCM450_MKFUNC(r1err), 568 WPCM450_MKFUNC(r1md), 569 WPCM450_MKFUNC(rmii2), 570 WPCM450_MKFUNC(r2err), 571 WPCM450_MKFUNC(r2md), 572 WPCM450_MKFUNC(kbcc), 573 WPCM450_MKFUNC(clko), 574 WPCM450_MKFUNC(smi), 575 WPCM450_MKFUNC(uinc), 576 WPCM450_MKFUNC(gspi), 577 WPCM450_MKFUNC(mben), 578 WPCM450_MKFUNC(xcs2), 579 WPCM450_MKFUNC(xcs1), 580 WPCM450_MKFUNC(sdio), 581 WPCM450_MKFUNC(sspi), 582 WPCM450_MKFUNC(fi0), 583 WPCM450_MKFUNC(fi1), 584 WPCM450_MKFUNC(fi2), 585 WPCM450_MKFUNC(fi3), 586 WPCM450_MKFUNC(fi4), 587 WPCM450_MKFUNC(fi5), 588 WPCM450_MKFUNC(fi6), 589 WPCM450_MKFUNC(fi7), 590 WPCM450_MKFUNC(fi8), 591 WPCM450_MKFUNC(fi9), 592 WPCM450_MKFUNC(fi10), 593 WPCM450_MKFUNC(fi11), 594 WPCM450_MKFUNC(fi12), 595 WPCM450_MKFUNC(fi13), 596 WPCM450_MKFUNC(fi14), 597 WPCM450_MKFUNC(fi15), 598 WPCM450_MKFUNC(pwm0), 599 WPCM450_MKFUNC(pwm1), 600 WPCM450_MKFUNC(pwm2), 601 WPCM450_MKFUNC(pwm3), 602 WPCM450_MKFUNC(pwm4), 603 WPCM450_MKFUNC(pwm5), 604 WPCM450_MKFUNC(pwm6), 605 WPCM450_MKFUNC(pwm7), 606 WPCM450_MKFUNC(hg0), 607 WPCM450_MKFUNC(hg1), 608 WPCM450_MKFUNC(hg2), 609 WPCM450_MKFUNC(hg3), 610 WPCM450_MKFUNC(hg4), 611 WPCM450_MKFUNC(hg5), 612 WPCM450_MKFUNC(hg6), 613 WPCM450_MKFUNC(hg7), 614 WPCM450_MKFUNC(gpio), 615 #undef WPCM450_MKFUNC 616 }; 617 618 #define WPCM450_PINCFG(a, b, c, d, e, f, g) \ 619 [a] = { .fn0 = fn_ ## b, .reg0 = WPCM450_GCR_ ## c, .bit0 = d, \ 620 .fn1 = fn_ ## e, .reg1 = WPCM450_GCR_ ## f, .bit1 = g } 621 622 struct wpcm450_pincfg { 623 int fn0, reg0, bit0; 624 int fn1, reg1, bit1; 625 }; 626 627 /* Add this value to bit0 or bit1 to indicate that the MFSEL bit is inverted */ 628 #define INV BIT(5) 629 630 static const struct wpcm450_pincfg pincfg[] = { 631 /* PIN FUNCTION 1 FUNCTION 2 */ 632 WPCM450_PINCFG(0, none, NONE, 0, none, NONE, 0), 633 WPCM450_PINCFG(1, none, NONE, 0, none, NONE, 0), 634 WPCM450_PINCFG(2, none, NONE, 0, none, NONE, 0), 635 WPCM450_PINCFG(3, none, NONE, 0, none, NONE, 0), 636 WPCM450_PINCFG(4, none, NONE, 0, none, NONE, 0), 637 WPCM450_PINCFG(5, none, NONE, 0, none, NONE, 0), 638 WPCM450_PINCFG(6, none, NONE, 0, none, NONE, 0), 639 WPCM450_PINCFG(7, none, NONE, 0, sdio, MFSEL1, 30), 640 WPCM450_PINCFG(8, none, NONE, 0, none, NONE, 0), 641 WPCM450_PINCFG(9, none, NONE, 0, none, NONE, 0), 642 WPCM450_PINCFG(10, none, NONE, 0, none, NONE, 0), 643 WPCM450_PINCFG(11, none, NONE, 0, none, NONE, 0), 644 WPCM450_PINCFG(12, gspi, MFSEL1, 24, sspi, MFSEL1, 31), 645 WPCM450_PINCFG(13, gspi, MFSEL1, 24, sspi, MFSEL1, 31), 646 WPCM450_PINCFG(14, gspi, MFSEL1, 24, sspi, MFSEL1, 31), 647 WPCM450_PINCFG(15, gspi, MFSEL1, 24, sspi, MFSEL1, 31), 648 WPCM450_PINCFG(16, none, NONE, 0, pwm6, MFSEL2, 22), 649 WPCM450_PINCFG(17, none, NONE, 0, pwm7, MFSEL2, 23), 650 WPCM450_PINCFG(18, none, NONE, 0, none, NONE, 0), 651 WPCM450_PINCFG(19, uinc, MFSEL1, 23, none, NONE, 0), 652 WPCM450_PINCFG(20, hg0, MFSEL2, 24, pwm4, MFSEL2, 20), 653 WPCM450_PINCFG(21, hg1, MFSEL2, 25, pwm5, MFSEL2, 21), 654 WPCM450_PINCFG(22, hg2, MFSEL2, 26, none, NONE, 0), 655 WPCM450_PINCFG(23, hg3, MFSEL2, 27, none, NONE, 0), 656 WPCM450_PINCFG(24, hg4, MFSEL2, 28, none, NONE, 0), 657 WPCM450_PINCFG(25, hg5, MFSEL2, 29, none, NONE, 0), 658 WPCM450_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0), 659 WPCM450_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0), 660 WPCM450_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0), 661 WPCM450_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0), 662 WPCM450_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0), 663 WPCM450_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0), 664 665 WPCM450_PINCFG(32, scs1, MFSEL1, 3, none, NONE, 0), 666 WPCM450_PINCFG(33, scs2, MFSEL1, 4, none, NONE, 0), 667 WPCM450_PINCFG(34, scs3, MFSEL1, 5 | INV, none, NONE, 0), 668 WPCM450_PINCFG(35, xcs1, MFSEL1, 29, none, NONE, 0), 669 WPCM450_PINCFG(36, xcs2, MFSEL1, 28, none, NONE, 0), 670 WPCM450_PINCFG(37, none, NONE, 0, none, NONE, 0), /* DVO */ 671 WPCM450_PINCFG(38, none, NONE, 0, none, NONE, 0), /* DVO */ 672 WPCM450_PINCFG(39, none, NONE, 0, none, NONE, 0), /* DVO */ 673 WPCM450_PINCFG(40, none, NONE, 0, none, NONE, 0), /* DVO */ 674 WPCM450_PINCFG(41, bsp, MFSEL1, 9, none, NONE, 0), 675 WPCM450_PINCFG(42, bsp, MFSEL1, 9, none, NONE, 0), 676 WPCM450_PINCFG(43, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), 677 WPCM450_PINCFG(44, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), 678 WPCM450_PINCFG(45, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), 679 WPCM450_PINCFG(46, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), 680 WPCM450_PINCFG(47, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), 681 WPCM450_PINCFG(48, hsp2, MFSEL1, 11, none, NONE, 0), 682 WPCM450_PINCFG(49, hsp2, MFSEL1, 11, none, NONE, 0), 683 WPCM450_PINCFG(50, hsp2, MFSEL1, 11, none, NONE, 0), 684 WPCM450_PINCFG(51, hsp2, MFSEL1, 11, none, NONE, 0), 685 WPCM450_PINCFG(52, hsp2, MFSEL1, 11, none, NONE, 0), 686 WPCM450_PINCFG(53, hsp2, MFSEL1, 11, none, NONE, 0), 687 WPCM450_PINCFG(54, hsp2, MFSEL1, 11, none, NONE, 0), 688 WPCM450_PINCFG(55, hsp2, MFSEL1, 11, none, NONE, 0), 689 WPCM450_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0), 690 WPCM450_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0), 691 WPCM450_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0), 692 WPCM450_PINCFG(59, hg6, MFSEL2, 30, none, NONE, 0), 693 WPCM450_PINCFG(60, hg7, MFSEL2, 31, sdio, MFSEL1, 30), 694 WPCM450_PINCFG(61, hsp1, MFSEL1, 10, none, NONE, 0), 695 WPCM450_PINCFG(62, hsp1, MFSEL1, 10, none, NONE, 0), 696 WPCM450_PINCFG(63, hsp1, MFSEL1, 10, none, NONE, 0), 697 698 WPCM450_PINCFG(64, fi0, MFSEL2, 0, none, NONE, 0), 699 WPCM450_PINCFG(65, fi1, MFSEL2, 1, none, NONE, 0), 700 WPCM450_PINCFG(66, fi2, MFSEL2, 2, none, NONE, 0), 701 WPCM450_PINCFG(67, fi3, MFSEL2, 3, none, NONE, 0), 702 WPCM450_PINCFG(68, fi4, MFSEL2, 4, none, NONE, 0), 703 WPCM450_PINCFG(69, fi5, MFSEL2, 5, none, NONE, 0), 704 WPCM450_PINCFG(70, fi6, MFSEL2, 6, none, NONE, 0), 705 WPCM450_PINCFG(71, fi7, MFSEL2, 7, none, NONE, 0), 706 WPCM450_PINCFG(72, fi8, MFSEL2, 8, none, NONE, 0), 707 WPCM450_PINCFG(73, fi9, MFSEL2, 9, none, NONE, 0), 708 WPCM450_PINCFG(74, fi10, MFSEL2, 10, none, NONE, 0), 709 WPCM450_PINCFG(75, fi11, MFSEL2, 11, none, NONE, 0), 710 WPCM450_PINCFG(76, fi12, MFSEL2, 12, none, NONE, 0), 711 WPCM450_PINCFG(77, fi13, MFSEL2, 13, none, NONE, 0), 712 WPCM450_PINCFG(78, fi14, MFSEL2, 14, none, NONE, 0), 713 WPCM450_PINCFG(79, fi15, MFSEL2, 15, none, NONE, 0), 714 WPCM450_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0), 715 WPCM450_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0), 716 WPCM450_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0), 717 WPCM450_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0), 718 WPCM450_PINCFG(84, rmii2, MFSEL1, 14, none, NONE, 0), 719 WPCM450_PINCFG(85, rmii2, MFSEL1, 14, none, NONE, 0), 720 WPCM450_PINCFG(86, rmii2, MFSEL1, 14, none, NONE, 0), 721 WPCM450_PINCFG(87, rmii2, MFSEL1, 14, none, NONE, 0), 722 WPCM450_PINCFG(88, rmii2, MFSEL1, 14, none, NONE, 0), 723 WPCM450_PINCFG(89, rmii2, MFSEL1, 14, none, NONE, 0), 724 WPCM450_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0), 725 WPCM450_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0), 726 WPCM450_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0), 727 WPCM450_PINCFG(93, kbcc, MFSEL1, 17 | INV, none, NONE, 0), 728 WPCM450_PINCFG(94, kbcc, MFSEL1, 17 | INV, none, NONE, 0), 729 WPCM450_PINCFG(95, none, NONE, 0, none, NONE, 0), 730 731 WPCM450_PINCFG(96, none, NONE, 0, none, NONE, 0), 732 WPCM450_PINCFG(97, none, NONE, 0, none, NONE, 0), 733 WPCM450_PINCFG(98, none, NONE, 0, none, NONE, 0), 734 WPCM450_PINCFG(99, none, NONE, 0, none, NONE, 0), 735 WPCM450_PINCFG(100, none, NONE, 0, none, NONE, 0), 736 WPCM450_PINCFG(101, none, NONE, 0, none, NONE, 0), 737 WPCM450_PINCFG(102, none, NONE, 0, none, NONE, 0), 738 WPCM450_PINCFG(103, none, NONE, 0, none, NONE, 0), 739 WPCM450_PINCFG(104, none, NONE, 0, none, NONE, 0), 740 WPCM450_PINCFG(105, none, NONE, 0, none, NONE, 0), 741 WPCM450_PINCFG(106, none, NONE, 0, none, NONE, 0), 742 WPCM450_PINCFG(107, none, NONE, 0, none, NONE, 0), 743 WPCM450_PINCFG(108, none, NONE, 0, none, NONE, 0), /* DVO */ 744 WPCM450_PINCFG(109, none, NONE, 0, none, NONE, 0), /* DVO */ 745 WPCM450_PINCFG(110, none, NONE, 0, none, NONE, 0), /* DVO */ 746 WPCM450_PINCFG(111, none, NONE, 0, none, NONE, 0), /* DVO */ 747 WPCM450_PINCFG(112, none, NONE, 0, none, NONE, 0), /* DVO */ 748 WPCM450_PINCFG(113, none, NONE, 0, none, NONE, 0), /* DVO */ 749 WPCM450_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0), 750 WPCM450_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0), 751 WPCM450_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0), 752 WPCM450_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0), 753 WPCM450_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0), 754 WPCM450_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0), 755 WPCM450_PINCFG(120, none, NONE, 0, none, NONE, 0), /* DVO */ 756 WPCM450_PINCFG(121, none, NONE, 0, none, NONE, 0), /* DVO */ 757 WPCM450_PINCFG(122, none, NONE, 0, none, NONE, 0), /* DVO */ 758 WPCM450_PINCFG(123, none, NONE, 0, none, NONE, 0), /* DVO */ 759 WPCM450_PINCFG(124, none, NONE, 0, none, NONE, 0), /* DVO */ 760 WPCM450_PINCFG(125, none, NONE, 0, none, NONE, 0), /* DVO */ 761 WPCM450_PINCFG(126, none, NONE, 0, none, NONE, 0), /* DVO */ 762 WPCM450_PINCFG(127, none, NONE, 0, none, NONE, 0), /* DVO */ 763 }; 764 765 #define WPCM450_PIN(n) PINCTRL_PIN(n, "gpio" #n) 766 767 static const struct pinctrl_pin_desc wpcm450_pins[] = { 768 WPCM450_PIN(0), WPCM450_PIN(1), WPCM450_PIN(2), WPCM450_PIN(3), 769 WPCM450_PIN(4), WPCM450_PIN(5), WPCM450_PIN(6), WPCM450_PIN(7), 770 WPCM450_PIN(8), WPCM450_PIN(9), WPCM450_PIN(10), WPCM450_PIN(11), 771 WPCM450_PIN(12), WPCM450_PIN(13), WPCM450_PIN(14), WPCM450_PIN(15), 772 WPCM450_PIN(16), WPCM450_PIN(17), WPCM450_PIN(18), WPCM450_PIN(19), 773 WPCM450_PIN(20), WPCM450_PIN(21), WPCM450_PIN(22), WPCM450_PIN(23), 774 WPCM450_PIN(24), WPCM450_PIN(25), WPCM450_PIN(26), WPCM450_PIN(27), 775 WPCM450_PIN(28), WPCM450_PIN(29), WPCM450_PIN(30), WPCM450_PIN(31), 776 WPCM450_PIN(32), WPCM450_PIN(33), WPCM450_PIN(34), WPCM450_PIN(35), 777 WPCM450_PIN(36), WPCM450_PIN(37), WPCM450_PIN(38), WPCM450_PIN(39), 778 WPCM450_PIN(40), WPCM450_PIN(41), WPCM450_PIN(42), WPCM450_PIN(43), 779 WPCM450_PIN(44), WPCM450_PIN(45), WPCM450_PIN(46), WPCM450_PIN(47), 780 WPCM450_PIN(48), WPCM450_PIN(49), WPCM450_PIN(50), WPCM450_PIN(51), 781 WPCM450_PIN(52), WPCM450_PIN(53), WPCM450_PIN(54), WPCM450_PIN(55), 782 WPCM450_PIN(56), WPCM450_PIN(57), WPCM450_PIN(58), WPCM450_PIN(59), 783 WPCM450_PIN(60), WPCM450_PIN(61), WPCM450_PIN(62), WPCM450_PIN(63), 784 WPCM450_PIN(64), WPCM450_PIN(65), WPCM450_PIN(66), WPCM450_PIN(67), 785 WPCM450_PIN(68), WPCM450_PIN(69), WPCM450_PIN(70), WPCM450_PIN(71), 786 WPCM450_PIN(72), WPCM450_PIN(73), WPCM450_PIN(74), WPCM450_PIN(75), 787 WPCM450_PIN(76), WPCM450_PIN(77), WPCM450_PIN(78), WPCM450_PIN(79), 788 WPCM450_PIN(80), WPCM450_PIN(81), WPCM450_PIN(82), WPCM450_PIN(83), 789 WPCM450_PIN(84), WPCM450_PIN(85), WPCM450_PIN(86), WPCM450_PIN(87), 790 WPCM450_PIN(88), WPCM450_PIN(89), WPCM450_PIN(90), WPCM450_PIN(91), 791 WPCM450_PIN(92), WPCM450_PIN(93), WPCM450_PIN(94), WPCM450_PIN(95), 792 WPCM450_PIN(96), WPCM450_PIN(97), WPCM450_PIN(98), WPCM450_PIN(99), 793 WPCM450_PIN(100), WPCM450_PIN(101), WPCM450_PIN(102), WPCM450_PIN(103), 794 WPCM450_PIN(104), WPCM450_PIN(105), WPCM450_PIN(106), WPCM450_PIN(107), 795 WPCM450_PIN(108), WPCM450_PIN(109), WPCM450_PIN(110), WPCM450_PIN(111), 796 WPCM450_PIN(112), WPCM450_PIN(113), WPCM450_PIN(114), WPCM450_PIN(115), 797 WPCM450_PIN(116), WPCM450_PIN(117), WPCM450_PIN(118), WPCM450_PIN(119), 798 WPCM450_PIN(120), WPCM450_PIN(121), WPCM450_PIN(122), WPCM450_PIN(123), 799 WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127), 800 }; 801 802 /* Helper function to update MFSEL field according to the selected function */ 803 static void wpcm450_update_mfsel(struct regmap *gcr_regmap, int reg, int bit, int fn, int fn_selected) 804 { 805 bool value = (fn == fn_selected); 806 807 if (bit & INV) { 808 value = !value; 809 bit &= ~INV; 810 } 811 812 regmap_update_bits(gcr_regmap, reg, BIT(bit), value ? BIT(bit) : 0); 813 } 814 815 /* Enable mode in pin group */ 816 static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, 817 int npins, int func) 818 { 819 const struct wpcm450_pincfg *cfg; 820 int i; 821 822 for (i = 0; i < npins; i++) { 823 cfg = &pincfg[pin[i]]; 824 if (func == fn_gpio || cfg->fn0 == func || cfg->fn1 == func) { 825 if (cfg->reg0) 826 wpcm450_update_mfsel(gcr_regmap, cfg->reg0, 827 cfg->bit0, cfg->fn0, func); 828 if (cfg->reg1) 829 wpcm450_update_mfsel(gcr_regmap, cfg->reg1, 830 cfg->bit1, cfg->fn1, func); 831 } 832 } 833 } 834 835 static int wpcm450_get_groups_count(struct pinctrl_dev *pctldev) 836 { 837 return ARRAY_SIZE(wpcm450_groups); 838 } 839 840 static const char *wpcm450_get_group_name(struct pinctrl_dev *pctldev, 841 unsigned int selector) 842 { 843 return wpcm450_groups[selector].name; 844 } 845 846 static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev, 847 unsigned int selector, 848 const unsigned int **pins, 849 unsigned int *npins) 850 { 851 *npins = wpcm450_groups[selector].npins; 852 *pins = wpcm450_groups[selector].pins; 853 854 return 0; 855 } 856 857 static void wpcm450_dt_free_map(struct pinctrl_dev *pctldev, 858 struct pinctrl_map *map, u32 num_maps) 859 { 860 kfree(map); 861 } 862 863 static const struct pinctrl_ops wpcm450_pinctrl_ops = { 864 .get_groups_count = wpcm450_get_groups_count, 865 .get_group_name = wpcm450_get_group_name, 866 .get_group_pins = wpcm450_get_group_pins, 867 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 868 .dt_free_map = wpcm450_dt_free_map, 869 }; 870 871 static int wpcm450_get_functions_count(struct pinctrl_dev *pctldev) 872 { 873 return ARRAY_SIZE(wpcm450_funcs); 874 } 875 876 static const char *wpcm450_get_function_name(struct pinctrl_dev *pctldev, 877 unsigned int function) 878 { 879 return wpcm450_funcs[function].name; 880 } 881 882 static int wpcm450_get_function_groups(struct pinctrl_dev *pctldev, 883 unsigned int function, 884 const char * const **groups, 885 unsigned int * const ngroups) 886 { 887 *ngroups = wpcm450_funcs[function].ngroups; 888 *groups = wpcm450_funcs[function].groups; 889 890 return 0; 891 } 892 893 static int wpcm450_pinmux_set_mux(struct pinctrl_dev *pctldev, 894 unsigned int function, 895 unsigned int group) 896 { 897 struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 898 899 wpcm450_setfunc(pctrl->gcr_regmap, wpcm450_groups[group].pins, 900 wpcm450_groups[group].npins, function); 901 902 return 0; 903 } 904 905 static const struct pinmux_ops wpcm450_pinmux_ops = { 906 .get_functions_count = wpcm450_get_functions_count, 907 .get_function_name = wpcm450_get_function_name, 908 .get_function_groups = wpcm450_get_function_groups, 909 .set_mux = wpcm450_pinmux_set_mux, 910 }; 911 912 static int debounce_bitnum(int gpio) 913 { 914 if (gpio >= 0 && gpio < 16) 915 return gpio; 916 return -EINVAL; 917 } 918 919 static int wpcm450_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 920 unsigned long *config) 921 { 922 struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 923 enum pin_config_param param = pinconf_to_config_param(*config); 924 unsigned long flags; 925 int bit; 926 u32 reg; 927 928 switch (param) { 929 case PIN_CONFIG_INPUT_DEBOUNCE: 930 bit = debounce_bitnum(pin); 931 if (bit < 0) 932 return bit; 933 934 raw_spin_lock_irqsave(&pctrl->lock, flags); 935 reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC); 936 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 937 938 *config = pinconf_to_config_packed(param, !!(reg & BIT(bit))); 939 return 0; 940 default: 941 return -ENOTSUPP; 942 } 943 } 944 945 static int wpcm450_config_set_one(struct wpcm450_pinctrl *pctrl, 946 unsigned int pin, unsigned long config) 947 { 948 enum pin_config_param param = pinconf_to_config_param(config); 949 unsigned long flags; 950 unsigned long reg; 951 int bit; 952 int arg; 953 954 switch (param) { 955 case PIN_CONFIG_INPUT_DEBOUNCE: 956 bit = debounce_bitnum(pin); 957 if (bit < 0) 958 return bit; 959 960 arg = pinconf_to_config_argument(config); 961 962 raw_spin_lock_irqsave(&pctrl->lock, flags); 963 reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC); 964 __assign_bit(bit, ®, arg); 965 iowrite32(reg, pctrl->gpio_base + WPCM450_GPEVDBNC); 966 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 967 return 0; 968 default: 969 return -ENOTSUPP; 970 } 971 } 972 973 static int wpcm450_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 974 unsigned long *configs, unsigned int num_configs) 975 { 976 struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 977 int ret; 978 979 while (num_configs--) { 980 ret = wpcm450_config_set_one(pctrl, pin, *configs++); 981 if (ret) 982 return ret; 983 } 984 985 return 0; 986 } 987 988 static const struct pinconf_ops wpcm450_pinconf_ops = { 989 .is_generic = true, 990 .pin_config_get = wpcm450_config_get, 991 .pin_config_set = wpcm450_config_set, 992 }; 993 994 static const struct pinctrl_desc wpcm450_pinctrl_desc = { 995 .name = "wpcm450-pinctrl", 996 .pins = wpcm450_pins, 997 .npins = ARRAY_SIZE(wpcm450_pins), 998 .pctlops = &wpcm450_pinctrl_ops, 999 .pmxops = &wpcm450_pinmux_ops, 1000 .confops = &wpcm450_pinconf_ops, 1001 .owner = THIS_MODULE, 1002 }; 1003 1004 static int wpcm450_gpio_set_config(struct gpio_chip *chip, 1005 unsigned int offset, unsigned long config) 1006 { 1007 struct wpcm450_gpio *gpio = gpiochip_get_data(chip); 1008 1009 return wpcm450_config_set_one(gpio->pctrl, offset, config); 1010 } 1011 1012 static int wpcm450_gpio_add_pin_ranges(struct gpio_chip *chip) 1013 { 1014 struct wpcm450_gpio *gpio = gpiochip_get_data(chip); 1015 const struct wpcm450_bank *bank = gpio->bank; 1016 1017 return gpiochip_add_pin_range(&gpio->chip.gc, dev_name(gpio->pctrl->dev), 1018 0, bank->base, bank->length); 1019 } 1020 1021 static int wpcm450_gpio_register(struct platform_device *pdev, 1022 struct wpcm450_pinctrl *pctrl) 1023 { 1024 struct device *dev = &pdev->dev; 1025 struct fwnode_handle *child; 1026 int ret; 1027 1028 pctrl->gpio_base = devm_platform_ioremap_resource(pdev, 0); 1029 if (IS_ERR(pctrl->gpio_base)) 1030 return dev_err_probe(dev, PTR_ERR(pctrl->gpio_base), 1031 "Resource fail for GPIO controller\n"); 1032 1033 for_each_gpiochip_node(dev, child) { 1034 struct gpio_generic_chip_config config; 1035 void __iomem *dat = NULL; 1036 void __iomem *set = NULL; 1037 void __iomem *dirout = NULL; 1038 unsigned long flags = 0; 1039 const struct wpcm450_bank *bank; 1040 struct wpcm450_gpio *gpio; 1041 struct gpio_irq_chip *girq; 1042 u32 reg; 1043 int i; 1044 1045 ret = fwnode_property_read_u32(child, "reg", ®); 1046 if (ret < 0) 1047 return ret; 1048 1049 if (reg >= WPCM450_NUM_BANKS) 1050 return dev_err_probe(dev, -EINVAL, 1051 "GPIO index %d out of range!\n", reg); 1052 1053 gpio = &pctrl->gpio_bank[reg]; 1054 gpio->pctrl = pctrl; 1055 1056 bank = &wpcm450_banks[reg]; 1057 gpio->bank = bank; 1058 1059 dat = pctrl->gpio_base + bank->datain; 1060 if (bank->dataout) { 1061 set = pctrl->gpio_base + bank->dataout; 1062 dirout = pctrl->gpio_base + bank->cfg0; 1063 } else { 1064 flags = GPIO_GENERIC_NO_OUTPUT; 1065 } 1066 1067 config = (struct gpio_generic_chip_config) { 1068 .dev = dev, 1069 .sz = 4, 1070 .dat = dat, 1071 .set = set, 1072 .dirout = dirout, 1073 .flags = flags, 1074 }; 1075 1076 ret = gpio_generic_chip_init(&gpio->chip, &config); 1077 if (ret < 0) 1078 return dev_err_probe(dev, ret, "GPIO initialization failed\n"); 1079 1080 gpio->chip.gc.ngpio = bank->length; 1081 gpio->chip.gc.set_config = wpcm450_gpio_set_config; 1082 gpio->chip.gc.fwnode = child; 1083 gpio->chip.gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges; 1084 1085 girq = &gpio->chip.gc.irq; 1086 gpio_irq_chip_set_chip(girq, &wpcm450_gpio_irqchip); 1087 girq->parent_handler = wpcm450_gpio_irqhandler; 1088 girq->parents = devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS, 1089 sizeof(*girq->parents), GFP_KERNEL); 1090 if (!girq->parents) 1091 return -ENOMEM; 1092 girq->default_type = IRQ_TYPE_NONE; 1093 girq->handler = handle_bad_irq; 1094 1095 girq->num_parents = 0; 1096 for (i = 0; i < WPCM450_NUM_GPIO_IRQS; i++) { 1097 int irq; 1098 1099 irq = fwnode_irq_get(child, i); 1100 if (irq < 0) 1101 break; 1102 if (!irq) 1103 continue; 1104 1105 girq->parents[i] = irq; 1106 girq->num_parents++; 1107 } 1108 1109 ret = devm_gpiochip_add_data(dev, &gpio->chip.gc, gpio); 1110 if (ret) 1111 return dev_err_probe(dev, ret, "Failed to add GPIO chip\n"); 1112 } 1113 1114 return 0; 1115 } 1116 1117 static int wpcm450_pinctrl_probe(struct platform_device *pdev) 1118 { 1119 struct device *dev = &pdev->dev; 1120 struct wpcm450_pinctrl *pctrl; 1121 int ret; 1122 1123 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 1124 if (!pctrl) 1125 return -ENOMEM; 1126 1127 pctrl->dev = &pdev->dev; 1128 raw_spin_lock_init(&pctrl->lock); 1129 dev_set_drvdata(dev, pctrl); 1130 1131 pctrl->gcr_regmap = 1132 syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr"); 1133 if (IS_ERR(pctrl->gcr_regmap)) 1134 return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap), 1135 "Failed to find nuvoton,wpcm450-gcr\n"); 1136 1137 pctrl->pctldev = devm_pinctrl_register(dev, 1138 &wpcm450_pinctrl_desc, pctrl); 1139 if (IS_ERR(pctrl->pctldev)) 1140 return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), 1141 "Failed to register pinctrl device\n"); 1142 1143 ret = wpcm450_gpio_register(pdev, pctrl); 1144 if (ret < 0) 1145 return ret; 1146 1147 return 0; 1148 } 1149 1150 static const struct of_device_id wpcm450_pinctrl_match[] = { 1151 { .compatible = "nuvoton,wpcm450-pinctrl" }, 1152 { } 1153 }; 1154 MODULE_DEVICE_TABLE(of, wpcm450_pinctrl_match); 1155 1156 static struct platform_driver wpcm450_pinctrl_driver = { 1157 .probe = wpcm450_pinctrl_probe, 1158 .driver = { 1159 .name = "wpcm450-pinctrl", 1160 .of_match_table = wpcm450_pinctrl_match, 1161 }, 1162 }; 1163 module_platform_driver(wpcm450_pinctrl_driver); 1164 1165 MODULE_LICENSE("GPL v2"); 1166 MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>"); 1167 MODULE_DESCRIPTION("Nuvoton WPCM450 Pinctrl and GPIO driver"); 1168