1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2024 Nuvoton Technology Corp. 4 * 5 * Author: Shan-Chun Hung <schung@nuvoton.com> 6 * * Jacky Huang <ychuang3@nuvoton.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/bitops.h> 11 #include <linux/cleanup.h> 12 #include <linux/clk.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/regmap.h> 19 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include "../core.h" 23 #include "../pinconf.h" 24 #include "pinctrl-ma35.h" 25 26 #define MA35_MFP_REG_BASE 0x80 27 #define MA35_MFP_REG_SZ_PER_BANK 8 28 #define MA35_MFP_BITS_PER_PORT 4 29 30 #define MA35_GPIO_BANK_MAX 14 31 #define MA35_GPIO_PORT_MAX 16 32 33 /* GPIO control registers */ 34 #define MA35_GP_REG_MODE 0x00 35 #define MA35_GP_REG_DINOFF 0x04 36 #define MA35_GP_REG_DOUT 0x08 37 #define MA35_GP_REG_DATMSK 0x0c 38 #define MA35_GP_REG_PIN 0x10 39 #define MA35_GP_REG_DBEN 0x14 40 #define MA35_GP_REG_INTTYPE 0x18 41 #define MA35_GP_REG_INTEN 0x1c 42 #define MA35_GP_REG_INTSRC 0x20 43 #define MA35_GP_REG_SMTEN 0x24 44 #define MA35_GP_REG_SLEWCTL 0x28 45 #define MA35_GP_REG_SPW 0x2c 46 #define MA35_GP_REG_PUSEL 0x30 47 #define MA35_GP_REG_DSL 0x38 48 #define MA35_GP_REG_DSH 0x3c 49 50 /* GPIO mode control */ 51 #define MA35_GP_MODE_INPUT 0x0 52 #define MA35_GP_MODE_OUTPUT 0x1 53 #define MA35_GP_MODE_OPEN_DRAIN 0x2 54 #define MA35_GP_MODE_QUASI 0x3 55 #define MA35_GP_MODE_MASK(n) GENMASK(n * 2 + 1, n * 2) 56 57 #define MA35_GP_SLEWCTL_MASK(n) GENMASK(n * 2 + 1, n * 2) 58 59 /* GPIO pull-up and pull-down selection control */ 60 #define MA35_GP_PUSEL_DISABLE 0x0 61 #define MA35_GP_PUSEL_PULL_UP 0x1 62 #define MA35_GP_PUSEL_PULL_DOWN 0x2 63 #define MA35_GP_PUSEL_MASK(n) GENMASK(n * 2 + 1, n * 2) 64 65 /* 66 * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger, 67 * while bits 16 ~ 31 control high-level or rising edge trigger. 68 */ 69 #define MA35_GP_INTEN_L(n) BIT(n) 70 #define MA35_GP_INTEN_H(n) BIT(n + 16) 71 #define MA35_GP_INTEN_BOTH(n) (MA35_GP_INTEN_H(n) | MA35_GP_INTEN_L(n)) 72 73 /* 74 * The MA35_GP_REG_DSL register controls ports 0 to 7, while the MA35_GP_REG_DSH 75 * register controls ports 8 to 15. Each port occupies a width of 4 bits, with 3 76 * bits being effective. 77 */ 78 #define MA35_GP_DS_REG(n) (n < 8 ? MA35_GP_REG_DSL : MA35_GP_REG_DSH) 79 #define MA35_GP_DS_MASK(n) GENMASK((n % 8) * 4 + 3, (n % 8) * 4) 80 81 #define MVOLT_1800 0 82 #define MVOLT_3300 1 83 84 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ 85 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 86 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) 87 88 static const char * const gpio_group_name[] = { 89 "gpioa", "gpiob", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", 90 "gpioh", "gpioi", "gpioj", "gpiok", "gpiol", "gpiom", "gpion", 91 }; 92 93 static const u32 ds_1800mv_tbl[] = { 94 2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000, 95 }; 96 97 static const u32 ds_3300mv_tbl[] = { 98 17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000, 99 }; 100 101 struct ma35_pin_func { 102 const char *name; 103 const char **groups; 104 u32 ngroups; 105 }; 106 107 struct ma35_pin_setting { 108 u32 offset; 109 u32 shift; 110 u32 muxval; 111 unsigned long *configs; 112 unsigned int nconfigs; 113 }; 114 115 struct ma35_pin_group { 116 const char *name; 117 unsigned int npins; 118 unsigned int *pins; 119 struct ma35_pin_setting *settings; 120 }; 121 122 struct ma35_pin_bank { 123 void __iomem *reg_base; 124 struct clk *clk; 125 int irq; 126 u8 bank_num; 127 u8 nr_pins; 128 bool valid; 129 const char *name; 130 struct fwnode_handle *fwnode; 131 struct gpio_chip chip; 132 u32 irqtype; 133 u32 irqinten; 134 struct regmap *regmap; 135 struct device *dev; 136 }; 137 138 struct ma35_pin_ctrl { 139 struct ma35_pin_bank *pin_banks; 140 u32 nr_banks; 141 u32 nr_pins; 142 }; 143 144 struct ma35_pinctrl { 145 struct device *dev; 146 struct ma35_pin_ctrl *ctrl; 147 struct pinctrl_dev *pctl; 148 const struct ma35_pinctrl_soc_info *info; 149 struct regmap *regmap; 150 struct ma35_pin_group *groups; 151 unsigned int ngroups; 152 struct ma35_pin_func *functions; 153 unsigned int nfunctions; 154 }; 155 156 static DEFINE_RAW_SPINLOCK(ma35_lock); 157 158 static int ma35_get_groups_count(struct pinctrl_dev *pctldev) 159 { 160 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev); 161 162 return npctl->ngroups; 163 } 164 165 static const char *ma35_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector) 166 { 167 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev); 168 169 return npctl->groups[selector].name; 170 } 171 172 static int ma35_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, 173 const unsigned int **pins, unsigned int *npins) 174 { 175 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev); 176 177 if (selector >= npctl->ngroups) 178 return -EINVAL; 179 180 *pins = npctl->groups[selector].pins; 181 *npins = npctl->groups[selector].npins; 182 183 return 0; 184 } 185 186 static struct ma35_pin_group *ma35_pinctrl_find_group_by_name( 187 const struct ma35_pinctrl *npctl, const char *name) 188 { 189 int i; 190 191 for (i = 0; i < npctl->ngroups; i++) { 192 if (!strcmp(npctl->groups[i].name, name)) 193 return &npctl->groups[i]; 194 } 195 return NULL; 196 } 197 198 static int ma35_pinctrl_dt_node_to_map_func(struct pinctrl_dev *pctldev, 199 struct device_node *np, 200 struct pinctrl_map **map, 201 unsigned int *num_maps) 202 { 203 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev); 204 struct ma35_pin_group *grp; 205 struct pinctrl_map *new_map; 206 struct device_node *parent; 207 int map_num = 1; 208 int i; 209 210 /* 211 * first find the group of this node and check if we need create 212 * config maps for pins 213 */ 214 grp = ma35_pinctrl_find_group_by_name(npctl, np->name); 215 if (!grp) { 216 dev_err(npctl->dev, "unable to find group for node %s\n", np->name); 217 return -EINVAL; 218 } 219 220 map_num += grp->npins; 221 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); 222 if (!new_map) 223 return -ENOMEM; 224 225 *map = new_map; 226 *num_maps = map_num; 227 /* create mux map */ 228 parent = of_get_parent(np); 229 if (!parent) 230 return -EINVAL; 231 232 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 233 new_map[0].data.mux.function = parent->name; 234 new_map[0].data.mux.group = np->name; 235 of_node_put(parent); 236 237 new_map++; 238 for (i = 0; i < grp->npins; i++) { 239 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 240 new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->pins[i]); 241 new_map[i].data.configs.configs = grp->settings[i].configs; 242 new_map[i].data.configs.num_configs = grp->settings[i].nconfigs; 243 } 244 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 245 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 246 247 return 0; 248 } 249 250 static const struct pinctrl_ops ma35_pctrl_ops = { 251 .get_groups_count = ma35_get_groups_count, 252 .get_group_name = ma35_get_group_name, 253 .get_group_pins = ma35_get_group_pins, 254 .dt_node_to_map = ma35_pinctrl_dt_node_to_map_func, 255 .dt_free_map = pinconf_generic_dt_free_map, 256 }; 257 258 static int ma35_pinmux_get_func_count(struct pinctrl_dev *pctldev) 259 { 260 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev); 261 262 return npctl->nfunctions; 263 } 264 265 static const char *ma35_pinmux_get_func_name(struct pinctrl_dev *pctldev, 266 unsigned int selector) 267 { 268 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev); 269 270 return npctl->functions[selector].name; 271 } 272 273 static int ma35_pinmux_get_func_groups(struct pinctrl_dev *pctldev, 274 unsigned int function, 275 const char *const **groups, 276 unsigned int *const num_groups) 277 { 278 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev); 279 280 *groups = npctl->functions[function].groups; 281 *num_groups = npctl->functions[function].ngroups; 282 283 return 0; 284 } 285 286 static int ma35_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, 287 unsigned int group) 288 { 289 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev); 290 struct ma35_pin_group *grp = &npctl->groups[group]; 291 struct ma35_pin_setting *setting = grp->settings; 292 u32 i, regval; 293 294 dev_dbg(npctl->dev, "enable function %s group %s\n", 295 npctl->functions[selector].name, npctl->groups[group].name); 296 297 for (i = 0; i < grp->npins; i++) { 298 regmap_read(npctl->regmap, setting->offset, ®val); 299 regval &= ~GENMASK(setting->shift + MA35_MFP_BITS_PER_PORT - 1, 300 setting->shift); 301 regval |= setting->muxval << setting->shift; 302 regmap_write(npctl->regmap, setting->offset, regval); 303 setting++; 304 } 305 return 0; 306 } 307 308 static const struct pinmux_ops ma35_pmx_ops = { 309 .get_functions_count = ma35_pinmux_get_func_count, 310 .get_function_name = ma35_pinmux_get_func_name, 311 .get_function_groups = ma35_pinmux_get_func_groups, 312 .set_mux = ma35_pinmux_set_mux, 313 .strict = true, 314 }; 315 316 static void ma35_gpio_set_mode(void __iomem *reg_mode, unsigned int gpio, u32 mode) 317 { 318 u32 regval = readl(reg_mode); 319 320 regval &= ~MA35_GP_MODE_MASK(gpio); 321 regval |= field_prep(MA35_GP_MODE_MASK(gpio), mode); 322 323 writel(regval, reg_mode); 324 } 325 326 static u32 ma35_gpio_get_mode(void __iomem *reg_mode, unsigned int gpio) 327 { 328 u32 regval = readl(reg_mode); 329 330 return field_get(MA35_GP_MODE_MASK(gpio), regval); 331 } 332 333 static int ma35_gpio_core_direction_in(struct gpio_chip *gc, unsigned int gpio) 334 { 335 struct ma35_pin_bank *bank = gpiochip_get_data(gc); 336 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE; 337 338 guard(raw_spinlock_irqsave)(&ma35_lock); 339 340 ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_INPUT); 341 342 return 0; 343 } 344 345 static int ma35_gpio_core_direction_out(struct gpio_chip *gc, unsigned int gpio, int val) 346 { 347 struct ma35_pin_bank *bank = gpiochip_get_data(gc); 348 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT; 349 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE; 350 unsigned int regval; 351 352 guard(raw_spinlock_irqsave)(&ma35_lock); 353 354 regval = readl(reg_dout); 355 if (val) 356 regval |= BIT(gpio); 357 else 358 regval &= ~BIT(gpio); 359 writel(regval, reg_dout); 360 361 ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_OUTPUT); 362 363 return 0; 364 } 365 366 static int ma35_gpio_core_get(struct gpio_chip *gc, unsigned int gpio) 367 { 368 struct ma35_pin_bank *bank = gpiochip_get_data(gc); 369 void __iomem *reg_pin = bank->reg_base + MA35_GP_REG_PIN; 370 371 return !!(readl(reg_pin) & BIT(gpio)); 372 } 373 374 static void ma35_gpio_core_set(struct gpio_chip *gc, unsigned int gpio, int val) 375 { 376 struct ma35_pin_bank *bank = gpiochip_get_data(gc); 377 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT; 378 u32 regval; 379 380 if (val) 381 regval = readl(reg_dout) | BIT(gpio); 382 else 383 regval = readl(reg_dout) & ~BIT(gpio); 384 385 writel(regval, reg_dout); 386 } 387 388 static int ma35_gpio_core_to_request(struct gpio_chip *gc, unsigned int gpio) 389 { 390 struct ma35_pin_bank *bank = gpiochip_get_data(gc); 391 u32 reg_offs, bit_offs, regval; 392 393 if (gpio < 8) { 394 /* The MFP low register controls port 0 ~ 7 */ 395 reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK; 396 bit_offs = gpio * MA35_MFP_BITS_PER_PORT; 397 } else { 398 /* The MFP high register controls port 8 ~ 15 */ 399 reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK + 4; 400 bit_offs = (gpio - 8) * MA35_MFP_BITS_PER_PORT; 401 } 402 403 regmap_read(bank->regmap, MA35_MFP_REG_BASE + reg_offs, ®val); 404 regval &= ~GENMASK(bit_offs + MA35_MFP_BITS_PER_PORT - 1, bit_offs); 405 regmap_write(bank->regmap, MA35_MFP_REG_BASE + reg_offs, regval); 406 407 return 0; 408 } 409 410 static void ma35_irq_gpio_ack(struct irq_data *d) 411 { 412 struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 413 void __iomem *reg_intsrc = bank->reg_base + MA35_GP_REG_INTSRC; 414 irq_hw_number_t hwirq = irqd_to_hwirq(d); 415 416 writel(BIT(hwirq), reg_intsrc); 417 } 418 419 static void ma35_irq_gpio_mask(struct irq_data *d) 420 { 421 struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 422 void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN; 423 irq_hw_number_t hwirq = irqd_to_hwirq(d); 424 u32 regval; 425 426 regval = readl(reg_ien); 427 428 regval &= ~MA35_GP_INTEN_BOTH(hwirq); 429 430 writel(regval, reg_ien); 431 } 432 433 static void ma35_irq_gpio_unmask(struct irq_data *d) 434 { 435 struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 436 void __iomem *reg_itype = bank->reg_base + MA35_GP_REG_INTTYPE; 437 void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN; 438 irq_hw_number_t hwirq = irqd_to_hwirq(d); 439 u32 bval, regval; 440 441 bval = bank->irqtype & BIT(hwirq); 442 regval = readl(reg_itype); 443 regval &= ~BIT(hwirq); 444 writel(regval | bval, reg_itype); 445 446 bval = bank->irqinten & MA35_GP_INTEN_BOTH(hwirq); 447 regval = readl(reg_ien); 448 regval &= ~MA35_GP_INTEN_BOTH(hwirq); 449 writel(regval | bval, reg_ien); 450 } 451 452 static int ma35_irq_irqtype(struct irq_data *d, unsigned int type) 453 { 454 struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 455 irq_hw_number_t hwirq = irqd_to_hwirq(d); 456 457 switch (type) { 458 case IRQ_TYPE_EDGE_BOTH: 459 irq_set_handler_locked(d, handle_edge_irq); 460 bank->irqtype &= ~BIT(hwirq); 461 bank->irqinten |= MA35_GP_INTEN_BOTH(hwirq); 462 break; 463 case IRQ_TYPE_EDGE_RISING: 464 case IRQ_TYPE_LEVEL_HIGH: 465 irq_set_handler_locked(d, handle_edge_irq); 466 bank->irqtype &= ~BIT(hwirq); 467 bank->irqinten |= MA35_GP_INTEN_H(hwirq); 468 bank->irqinten &= ~MA35_GP_INTEN_L(hwirq); 469 break; 470 case IRQ_TYPE_EDGE_FALLING: 471 case IRQ_TYPE_LEVEL_LOW: 472 irq_set_handler_locked(d, handle_edge_irq); 473 bank->irqtype &= ~BIT(hwirq); 474 bank->irqinten |= MA35_GP_INTEN_L(hwirq); 475 bank->irqinten &= ~MA35_GP_INTEN_H(hwirq); 476 break; 477 default: 478 return -EINVAL; 479 } 480 481 writel(bank->irqtype, bank->reg_base + MA35_GP_REG_INTTYPE); 482 writel(bank->irqinten, bank->reg_base + MA35_GP_REG_INTEN); 483 484 return 0; 485 } 486 487 static struct irq_chip ma35_gpio_irqchip = { 488 .name = "MA35-GPIO-IRQ", 489 .irq_disable = ma35_irq_gpio_mask, 490 .irq_enable = ma35_irq_gpio_unmask, 491 .irq_ack = ma35_irq_gpio_ack, 492 .irq_mask = ma35_irq_gpio_mask, 493 .irq_unmask = ma35_irq_gpio_unmask, 494 .irq_set_type = ma35_irq_irqtype, 495 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 496 GPIOCHIP_IRQ_RESOURCE_HELPERS, 497 }; 498 499 static void ma35_irq_demux_intgroup(struct irq_desc *desc) 500 { 501 struct ma35_pin_bank *bank = gpiochip_get_data(irq_desc_get_handler_data(desc)); 502 struct irq_domain *irqdomain = bank->chip.irq.domain; 503 struct irq_chip *irqchip = irq_desc_get_chip(desc); 504 unsigned long isr; 505 int offset; 506 507 chained_irq_enter(irqchip, desc); 508 509 isr = readl(bank->reg_base + MA35_GP_REG_INTSRC); 510 511 for_each_set_bit(offset, &isr, bank->nr_pins) 512 generic_handle_irq(irq_find_mapping(irqdomain, offset)); 513 514 chained_irq_exit(irqchip, desc); 515 } 516 517 static int ma35_gpiolib_register(struct platform_device *pdev, struct ma35_pinctrl *npctl) 518 { 519 struct ma35_pin_ctrl *ctrl = npctl->ctrl; 520 struct ma35_pin_bank *bank = ctrl->pin_banks; 521 int ret; 522 int i; 523 524 for (i = 0; i < ctrl->nr_banks; i++, bank++) { 525 if (!bank->valid) { 526 dev_warn(&pdev->dev, "%pfw: bank is not valid\n", bank->fwnode); 527 continue; 528 } 529 bank->irqtype = 0; 530 bank->irqinten = 0; 531 bank->chip.label = bank->name; 532 bank->chip.of_gpio_n_cells = 2; 533 bank->chip.parent = &pdev->dev; 534 bank->chip.request = ma35_gpio_core_to_request; 535 bank->chip.direction_input = ma35_gpio_core_direction_in; 536 bank->chip.direction_output = ma35_gpio_core_direction_out; 537 bank->chip.get = ma35_gpio_core_get; 538 bank->chip.set = ma35_gpio_core_set; 539 bank->chip.base = -1; 540 bank->chip.ngpio = bank->nr_pins; 541 bank->chip.can_sleep = false; 542 543 if (bank->irq > 0) { 544 struct gpio_irq_chip *girq; 545 546 girq = &bank->chip.irq; 547 gpio_irq_chip_set_chip(girq, &ma35_gpio_irqchip); 548 girq->parent_handler = ma35_irq_demux_intgroup; 549 girq->num_parents = 1; 550 551 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents, 552 sizeof(*girq->parents), GFP_KERNEL); 553 if (!girq->parents) 554 return -ENOMEM; 555 556 girq->parents[0] = bank->irq; 557 girq->default_type = IRQ_TYPE_NONE; 558 girq->handler = handle_bad_irq; 559 } 560 561 ret = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank); 562 if (ret) { 563 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 564 bank->chip.label, ret); 565 return ret; 566 } 567 } 568 return 0; 569 } 570 571 static int ma35_get_bank_data(struct ma35_pin_bank *bank) 572 { 573 bank->reg_base = fwnode_iomap(bank->fwnode, 0); 574 if (!bank->reg_base) 575 return -ENOMEM; 576 577 bank->irq = fwnode_irq_get(bank->fwnode, 0); 578 579 bank->nr_pins = MA35_GPIO_PORT_MAX; 580 581 bank->clk = of_clk_get(to_of_node(bank->fwnode), 0); 582 if (IS_ERR(bank->clk)) 583 return PTR_ERR(bank->clk); 584 585 return clk_prepare_enable(bank->clk); 586 } 587 588 static int ma35_pinctrl_get_soc_data(struct ma35_pinctrl *pctl, struct platform_device *pdev) 589 { 590 struct fwnode_handle *child; 591 struct ma35_pin_ctrl *ctrl; 592 struct ma35_pin_bank *bank; 593 int i, id = 0; 594 595 ctrl = pctl->ctrl; 596 ctrl->nr_banks = MA35_GPIO_BANK_MAX; 597 598 ctrl->pin_banks = devm_kcalloc(&pdev->dev, ctrl->nr_banks, 599 sizeof(*ctrl->pin_banks), GFP_KERNEL); 600 if (!ctrl->pin_banks) 601 return -ENOMEM; 602 603 for (i = 0; i < ctrl->nr_banks; i++) { 604 ctrl->pin_banks[i].bank_num = i; 605 ctrl->pin_banks[i].name = gpio_group_name[i]; 606 } 607 608 for_each_gpiochip_node(&pdev->dev, child) { 609 bank = &ctrl->pin_banks[id]; 610 bank->fwnode = child; 611 bank->regmap = pctl->regmap; 612 bank->dev = &pdev->dev; 613 if (!ma35_get_bank_data(bank)) 614 bank->valid = true; 615 id++; 616 } 617 return 0; 618 } 619 620 static void ma35_gpio_cla_port(unsigned int gpio_num, unsigned int *group, 621 unsigned int *num) 622 { 623 *group = gpio_num / MA35_GPIO_PORT_MAX; 624 *num = gpio_num % MA35_GPIO_PORT_MAX; 625 } 626 627 static int ma35_pinconf_set_pull(struct ma35_pinctrl *npctl, unsigned int pin, 628 int pull_up) 629 { 630 unsigned int port, group_num; 631 void __iomem *base; 632 u32 regval, pull_sel = MA35_GP_PUSEL_DISABLE; 633 634 ma35_gpio_cla_port(pin, &group_num, &port); 635 base = npctl->ctrl->pin_banks[group_num].reg_base; 636 637 regval = readl(base + MA35_GP_REG_PUSEL); 638 regval &= ~MA35_GP_PUSEL_MASK(port); 639 640 switch (pull_up) { 641 case PIN_CONFIG_BIAS_PULL_UP: 642 pull_sel = MA35_GP_PUSEL_PULL_UP; 643 break; 644 645 case PIN_CONFIG_BIAS_PULL_DOWN: 646 pull_sel = MA35_GP_PUSEL_PULL_DOWN; 647 break; 648 649 case PIN_CONFIG_BIAS_DISABLE: 650 pull_sel = MA35_GP_PUSEL_DISABLE; 651 break; 652 } 653 654 regval |= field_prep(MA35_GP_PUSEL_MASK(port), pull_sel); 655 writel(regval, base + MA35_GP_REG_PUSEL); 656 657 return 0; 658 } 659 660 static int ma35_pinconf_get_output(struct ma35_pinctrl *npctl, unsigned int pin) 661 { 662 unsigned int port, group_num; 663 void __iomem *base; 664 u32 mode; 665 666 ma35_gpio_cla_port(pin, &group_num, &port); 667 base = npctl->ctrl->pin_banks[group_num].reg_base; 668 669 mode = ma35_gpio_get_mode(base + MA35_GP_REG_MODE, port); 670 if (mode == MA35_GP_MODE_OUTPUT) 671 return 1; 672 673 return 0; 674 } 675 676 static int ma35_pinconf_get_pull(struct ma35_pinctrl *npctl, unsigned int pin) 677 { 678 unsigned int port, group_num; 679 void __iomem *base; 680 u32 regval, pull_sel; 681 682 ma35_gpio_cla_port(pin, &group_num, &port); 683 base = npctl->ctrl->pin_banks[group_num].reg_base; 684 685 regval = readl(base + MA35_GP_REG_PUSEL); 686 687 pull_sel = field_get(MA35_GP_PUSEL_MASK(port), regval); 688 689 switch (pull_sel) { 690 case MA35_GP_PUSEL_PULL_UP: 691 return PIN_CONFIG_BIAS_PULL_UP; 692 693 case MA35_GP_PUSEL_PULL_DOWN: 694 return PIN_CONFIG_BIAS_PULL_DOWN; 695 696 case MA35_GP_PUSEL_DISABLE: 697 return PIN_CONFIG_BIAS_DISABLE; 698 } 699 700 return PIN_CONFIG_BIAS_DISABLE; 701 } 702 703 static int ma35_pinconf_set_output(struct ma35_pinctrl *npctl, unsigned int pin, bool out) 704 { 705 unsigned int port, group_num; 706 void __iomem *base; 707 708 ma35_gpio_cla_port(pin, &group_num, &port); 709 base = npctl->ctrl->pin_banks[group_num].reg_base; 710 711 ma35_gpio_set_mode(base + MA35_GP_REG_MODE, port, MA35_GP_MODE_OUTPUT); 712 713 return 0; 714 } 715 716 static int ma35_pinconf_get_power_source(struct ma35_pinctrl *npctl, unsigned int pin) 717 { 718 unsigned int port, group_num; 719 void __iomem *base; 720 u32 regval; 721 722 ma35_gpio_cla_port(pin, &group_num, &port); 723 base = npctl->ctrl->pin_banks[group_num].reg_base; 724 725 regval = readl(base + MA35_GP_REG_SPW); 726 727 if (regval & BIT(port)) 728 return MVOLT_3300; 729 else 730 return MVOLT_1800; 731 } 732 733 static int ma35_pinconf_set_power_source(struct ma35_pinctrl *npctl, 734 unsigned int pin, int arg) 735 { 736 unsigned int port, group_num; 737 void __iomem *base; 738 u32 regval; 739 740 if ((arg != MVOLT_1800) && (arg != MVOLT_3300)) 741 return -EINVAL; 742 743 ma35_gpio_cla_port(pin, &group_num, &port); 744 base = npctl->ctrl->pin_banks[group_num].reg_base; 745 746 regval = readl(base + MA35_GP_REG_SPW); 747 748 if (arg == MVOLT_1800) 749 regval &= ~BIT(port); 750 else 751 regval |= BIT(port); 752 753 writel(regval, base + MA35_GP_REG_SPW); 754 755 return 0; 756 } 757 758 static int ma35_pinconf_get_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin, 759 u32 *strength) 760 { 761 unsigned int port, group_num; 762 void __iomem *base; 763 u32 regval, ds_val; 764 765 ma35_gpio_cla_port(pin, &group_num, &port); 766 base = npctl->ctrl->pin_banks[group_num].reg_base; 767 768 regval = readl(base + MA35_GP_DS_REG(port)); 769 ds_val = field_get(MA35_GP_DS_MASK(port), regval); 770 771 if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800) 772 *strength = ds_1800mv_tbl[ds_val]; 773 else 774 *strength = ds_3300mv_tbl[ds_val]; 775 776 return 0; 777 } 778 779 static int ma35_pinconf_set_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin, 780 int strength) 781 { 782 unsigned int port, group_num; 783 void __iomem *base; 784 int i, ds_val = -1; 785 u32 regval; 786 787 if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800) { 788 for (i = 0; i < ARRAY_SIZE(ds_1800mv_tbl); i++) { 789 if (ds_1800mv_tbl[i] == strength) { 790 ds_val = i; 791 break; 792 } 793 } 794 } else { 795 for (i = 0; i < ARRAY_SIZE(ds_3300mv_tbl); i++) { 796 if (ds_3300mv_tbl[i] == strength) { 797 ds_val = i; 798 break; 799 } 800 } 801 } 802 if (ds_val == -1) 803 return -EINVAL; 804 805 ma35_gpio_cla_port(pin, &group_num, &port); 806 base = npctl->ctrl->pin_banks[group_num].reg_base; 807 808 regval = readl(base + MA35_GP_DS_REG(port)); 809 regval &= ~MA35_GP_DS_MASK(port); 810 regval |= field_prep(MA35_GP_DS_MASK(port), ds_val); 811 812 writel(regval, base + MA35_GP_DS_REG(port)); 813 814 return 0; 815 } 816 817 static int ma35_pinconf_get_schmitt_enable(struct ma35_pinctrl *npctl, unsigned int pin) 818 { 819 unsigned int port, group_num; 820 void __iomem *base; 821 u32 regval; 822 823 ma35_gpio_cla_port(pin, &group_num, &port); 824 base = npctl->ctrl->pin_banks[group_num].reg_base; 825 826 regval = readl(base + MA35_GP_REG_SMTEN); 827 828 return !!(regval & BIT(port)); 829 } 830 831 static int ma35_pinconf_set_schmitt(struct ma35_pinctrl *npctl, unsigned int pin, int enable) 832 { 833 unsigned int port, group_num; 834 void __iomem *base; 835 u32 regval; 836 837 ma35_gpio_cla_port(pin, &group_num, &port); 838 base = npctl->ctrl->pin_banks[group_num].reg_base; 839 840 regval = readl(base + MA35_GP_REG_SMTEN); 841 842 if (enable) 843 regval |= BIT(port); 844 else 845 regval &= ~BIT(port); 846 847 writel(regval, base + MA35_GP_REG_SMTEN); 848 849 return 0; 850 } 851 852 static int ma35_pinconf_get_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin) 853 { 854 unsigned int port, group_num; 855 void __iomem *base; 856 u32 regval; 857 858 ma35_gpio_cla_port(pin, &group_num, &port); 859 base = npctl->ctrl->pin_banks[group_num].reg_base; 860 861 regval = readl(base + MA35_GP_REG_SLEWCTL); 862 863 return field_get(MA35_GP_SLEWCTL_MASK(port), regval); 864 } 865 866 static int ma35_pinconf_set_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin, int rate) 867 { 868 unsigned int port, group_num; 869 void __iomem *base; 870 u32 regval; 871 872 ma35_gpio_cla_port(pin, &group_num, &port); 873 base = npctl->ctrl->pin_banks[group_num].reg_base; 874 875 regval = readl(base + MA35_GP_REG_SLEWCTL); 876 regval &= ~MA35_GP_SLEWCTL_MASK(port); 877 regval |= field_prep(MA35_GP_SLEWCTL_MASK(port), rate); 878 879 writel(regval, base + MA35_GP_REG_SLEWCTL); 880 881 return 0; 882 } 883 884 static int ma35_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) 885 { 886 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev); 887 enum pin_config_param param = pinconf_to_config_param(*config); 888 u32 arg; 889 int ret; 890 891 switch (param) { 892 case PIN_CONFIG_BIAS_DISABLE: 893 case PIN_CONFIG_BIAS_PULL_DOWN: 894 case PIN_CONFIG_BIAS_PULL_UP: 895 if (ma35_pinconf_get_pull(npctl, pin) != param) 896 return -EINVAL; 897 arg = 1; 898 break; 899 900 case PIN_CONFIG_DRIVE_STRENGTH: 901 ret = ma35_pinconf_get_drive_strength(npctl, pin, &arg); 902 if (ret) 903 return ret; 904 break; 905 906 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 907 arg = ma35_pinconf_get_schmitt_enable(npctl, pin); 908 break; 909 910 case PIN_CONFIG_SLEW_RATE: 911 arg = ma35_pinconf_get_slew_rate(npctl, pin); 912 break; 913 914 case PIN_CONFIG_OUTPUT_ENABLE: 915 arg = ma35_pinconf_get_output(npctl, pin); 916 break; 917 918 case PIN_CONFIG_POWER_SOURCE: 919 arg = ma35_pinconf_get_power_source(npctl, pin); 920 break; 921 922 default: 923 return -EINVAL; 924 } 925 *config = pinconf_to_config_packed(param, arg); 926 927 return 0; 928 } 929 930 static int ma35_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 931 unsigned long *configs, unsigned int num_configs) 932 { 933 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev); 934 enum pin_config_param param; 935 unsigned int arg = 0; 936 int i, ret = 0; 937 938 for (i = 0; i < num_configs; i++) { 939 param = pinconf_to_config_param(configs[i]); 940 arg = pinconf_to_config_argument(configs[i]); 941 942 switch (param) { 943 case PIN_CONFIG_BIAS_DISABLE: 944 case PIN_CONFIG_BIAS_PULL_UP: 945 case PIN_CONFIG_BIAS_PULL_DOWN: 946 ret = ma35_pinconf_set_pull(npctl, pin, param); 947 break; 948 949 case PIN_CONFIG_DRIVE_STRENGTH: 950 ret = ma35_pinconf_set_drive_strength(npctl, pin, arg); 951 break; 952 953 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 954 ret = ma35_pinconf_set_schmitt(npctl, pin, 1); 955 break; 956 957 case PIN_CONFIG_INPUT_SCHMITT: 958 ret = ma35_pinconf_set_schmitt(npctl, pin, arg); 959 break; 960 961 case PIN_CONFIG_SLEW_RATE: 962 ret = ma35_pinconf_set_slew_rate(npctl, pin, arg); 963 break; 964 965 case PIN_CONFIG_OUTPUT_ENABLE: 966 ret = ma35_pinconf_set_output(npctl, pin, arg); 967 break; 968 969 case PIN_CONFIG_POWER_SOURCE: 970 ret = ma35_pinconf_set_power_source(npctl, pin, arg); 971 break; 972 973 default: 974 return -EINVAL; 975 } 976 977 if (ret) 978 break; 979 } 980 return ret; 981 } 982 983 static const struct pinconf_ops ma35_pinconf_ops = { 984 .pin_config_get = ma35_pinconf_get, 985 .pin_config_set = ma35_pinconf_set, 986 .is_generic = true, 987 }; 988 989 static int ma35_pinctrl_parse_groups(struct device_node *np, struct ma35_pin_group *grp, 990 struct ma35_pinctrl *npctl, u32 index) 991 { 992 struct ma35_pin_setting *pin; 993 unsigned long *configs; 994 unsigned int nconfigs; 995 int i, j, count, ret; 996 u32 *elems; 997 998 grp->name = np->name; 999 1000 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &nconfigs); 1001 if (ret) 1002 return ret; 1003 1004 count = of_property_count_elems_of_size(np, "nuvoton,pins", sizeof(u32)); 1005 if (!count || count % 3) 1006 return -EINVAL; 1007 1008 elems = devm_kmalloc_array(npctl->dev, count, sizeof(u32), GFP_KERNEL); 1009 if (!elems) 1010 return -ENOMEM; 1011 1012 ret = of_property_read_u32_array(np, "nuvoton,pins", elems, count); 1013 if (ret) 1014 return -EINVAL; 1015 1016 grp->npins = count / 3; 1017 1018 grp->pins = devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); 1019 if (!grp->pins) 1020 return -ENOMEM; 1021 1022 grp->settings = devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->settings), GFP_KERNEL); 1023 if (!grp->settings) 1024 return -ENOMEM; 1025 1026 pin = grp->settings; 1027 1028 for (i = 0, j = 0; i < count; i += 3, j++) { 1029 pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE; 1030 pin->shift = (elems[i + 1] * MA35_MFP_BITS_PER_PORT) % 32; 1031 pin->muxval = elems[i + 2]; 1032 pin->configs = configs; 1033 pin->nconfigs = nconfigs; 1034 grp->pins[j] = npctl->info->get_pin_num(pin->offset, pin->shift); 1035 pin++; 1036 } 1037 return 0; 1038 } 1039 1040 static int ma35_pinctrl_parse_functions(struct device_node *np, struct ma35_pinctrl *npctl, 1041 u32 index) 1042 { 1043 struct device_node *child; 1044 struct ma35_pin_func *func; 1045 struct ma35_pin_group *grp; 1046 static u32 grp_index; 1047 u32 ret, i = 0; 1048 1049 dev_dbg(npctl->dev, "parse function(%d): %s\n", index, np->name); 1050 1051 func = &npctl->functions[index]; 1052 func->name = np->name; 1053 func->ngroups = of_get_child_count(np); 1054 1055 if (func->ngroups <= 0) 1056 return 0; 1057 1058 func->groups = devm_kcalloc(npctl->dev, func->ngroups, sizeof(char *), GFP_KERNEL); 1059 if (!func->groups) 1060 return -ENOMEM; 1061 1062 for_each_child_of_node(np, child) { 1063 func->groups[i] = child->name; 1064 grp = &npctl->groups[grp_index++]; 1065 ret = ma35_pinctrl_parse_groups(child, grp, npctl, i++); 1066 if (ret) { 1067 of_node_put(child); 1068 return ret; 1069 } 1070 } 1071 return 0; 1072 } 1073 1074 static int ma35_pinctrl_probe_dt(struct platform_device *pdev, struct ma35_pinctrl *npctl) 1075 { 1076 struct fwnode_handle *child; 1077 u32 idx = 0; 1078 int ret; 1079 1080 device_for_each_child_node(&pdev->dev, child) { 1081 if (fwnode_property_present(child, "gpio-controller")) 1082 continue; 1083 npctl->nfunctions++; 1084 npctl->ngroups += of_get_child_count(to_of_node(child)); 1085 } 1086 1087 if (!npctl->nfunctions) 1088 return -EINVAL; 1089 1090 npctl->functions = devm_kcalloc(&pdev->dev, npctl->nfunctions, 1091 sizeof(*npctl->functions), GFP_KERNEL); 1092 if (!npctl->functions) 1093 return -ENOMEM; 1094 1095 npctl->groups = devm_kcalloc(&pdev->dev, npctl->ngroups, 1096 sizeof(*npctl->groups), GFP_KERNEL); 1097 if (!npctl->groups) 1098 return -ENOMEM; 1099 1100 device_for_each_child_node(&pdev->dev, child) { 1101 if (fwnode_property_present(child, "gpio-controller")) 1102 continue; 1103 1104 ret = ma35_pinctrl_parse_functions(to_of_node(child), npctl, idx++); 1105 if (ret) { 1106 fwnode_handle_put(child); 1107 dev_err(&pdev->dev, "failed to parse function\n"); 1108 return ret; 1109 } 1110 } 1111 return 0; 1112 } 1113 1114 int ma35_pinctrl_probe(struct platform_device *pdev, const struct ma35_pinctrl_soc_info *info) 1115 { 1116 struct pinctrl_desc *ma35_pinctrl_desc; 1117 struct device *dev = &pdev->dev; 1118 struct ma35_pinctrl *npctl; 1119 int ret; 1120 1121 if (!info || !info->pins || !info->npins) { 1122 dev_err(&pdev->dev, "wrong pinctrl info\n"); 1123 return -EINVAL; 1124 } 1125 1126 npctl = devm_kzalloc(&pdev->dev, sizeof(*npctl), GFP_KERNEL); 1127 if (!npctl) 1128 return -ENOMEM; 1129 1130 ma35_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ma35_pinctrl_desc), GFP_KERNEL); 1131 if (!ma35_pinctrl_desc) 1132 return -ENOMEM; 1133 1134 npctl->ctrl = devm_kzalloc(&pdev->dev, sizeof(*npctl->ctrl), GFP_KERNEL); 1135 if (!npctl->ctrl) 1136 return -ENOMEM; 1137 1138 ma35_pinctrl_desc->name = dev_name(&pdev->dev); 1139 ma35_pinctrl_desc->pins = info->pins; 1140 ma35_pinctrl_desc->npins = info->npins; 1141 ma35_pinctrl_desc->pctlops = &ma35_pctrl_ops; 1142 ma35_pinctrl_desc->pmxops = &ma35_pmx_ops; 1143 ma35_pinctrl_desc->confops = &ma35_pinconf_ops; 1144 ma35_pinctrl_desc->owner = THIS_MODULE; 1145 1146 npctl->info = info; 1147 npctl->dev = &pdev->dev; 1148 1149 npctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "nuvoton,sys"); 1150 if (IS_ERR(npctl->regmap)) 1151 return dev_err_probe(&pdev->dev, PTR_ERR(npctl->regmap), 1152 "No syscfg phandle specified\n"); 1153 1154 ret = ma35_pinctrl_get_soc_data(npctl, pdev); 1155 if (ret) 1156 return dev_err_probe(&pdev->dev, ret, "fail to get soc data\n"); 1157 1158 platform_set_drvdata(pdev, npctl); 1159 1160 ret = ma35_pinctrl_probe_dt(pdev, npctl); 1161 if (ret) 1162 return dev_err_probe(&pdev->dev, ret, "fail to probe MA35 pinctrl dt\n"); 1163 1164 ret = devm_pinctrl_register_and_init(dev, ma35_pinctrl_desc, npctl, &npctl->pctl); 1165 if (ret) 1166 return dev_err_probe(&pdev->dev, ret, "fail to register MA35 pinctrl\n"); 1167 1168 ret = pinctrl_enable(npctl->pctl); 1169 if (ret) 1170 return dev_err_probe(&pdev->dev, ret, "fail to enable MA35 pinctrl\n"); 1171 1172 return ma35_gpiolib_register(pdev, npctl); 1173 } 1174 1175 int ma35_pinctrl_suspend(struct device *dev) 1176 { 1177 struct ma35_pinctrl *npctl = dev_get_drvdata(dev); 1178 1179 return pinctrl_force_sleep(npctl->pctl); 1180 } 1181 1182 int ma35_pinctrl_resume(struct device *dev) 1183 { 1184 struct ma35_pinctrl *npctl = dev_get_drvdata(dev); 1185 1186 return pinctrl_force_default(npctl->pctl); 1187 } 1188