1 /* 2 * Generic GPIO driver for logic cells found in the Nomadik SoC 3 * 4 * Copyright (C) 2008,2009 STMicroelectronics 5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/init.h> 16 #include <linux/device.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/clk.h> 20 #include <linux/err.h> 21 #include <linux/gpio.h> 22 #include <linux/spinlock.h> 23 #include <linux/interrupt.h> 24 #include <linux/slab.h> 25 #include <linux/of_device.h> 26 #include <linux/of_address.h> 27 #include <linux/pinctrl/machine.h> 28 #include <linux/pinctrl/pinctrl.h> 29 #include <linux/pinctrl/pinmux.h> 30 #include <linux/pinctrl/pinconf.h> 31 /* Since we request GPIOs from ourself */ 32 #include <linux/pinctrl/consumer.h> 33 #include "pinctrl-nomadik.h" 34 #include "../core.h" 35 #include "../pinctrl-utils.h" 36 37 /* 38 * The GPIO module in the Nomadik family of Systems-on-Chip is an 39 * AMBA device, managing 32 pins and alternate functions. The logic block 40 * is currently used in the Nomadik and ux500. 41 * 42 * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 43 */ 44 45 /* 46 * pin configurations are represented by 32-bit integers: 47 * 48 * bit 0.. 8 - Pin Number (512 Pins Maximum) 49 * bit 9..10 - Alternate Function Selection 50 * bit 11..12 - Pull up/down state 51 * bit 13 - Sleep mode behaviour 52 * bit 14 - Direction 53 * bit 15 - Value (if output) 54 * bit 16..18 - SLPM pull up/down state 55 * bit 19..20 - SLPM direction 56 * bit 21..22 - SLPM Value (if output) 57 * bit 23..25 - PDIS value (if input) 58 * bit 26 - Gpio mode 59 * bit 27 - Sleep mode 60 * 61 * to facilitate the definition, the following macros are provided 62 * 63 * PIN_CFG_DEFAULT - default config (0): 64 * pull up/down = disabled 65 * sleep mode = input/wakeup 66 * direction = input 67 * value = low 68 * SLPM direction = same as normal 69 * SLPM pull = same as normal 70 * SLPM value = same as normal 71 * 72 * PIN_CFG - default config with alternate function 73 */ 74 75 typedef unsigned long pin_cfg_t; 76 77 #define PIN_NUM_MASK 0x1ff 78 #define PIN_NUM(x) ((x) & PIN_NUM_MASK) 79 80 #define PIN_ALT_SHIFT 9 81 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) 82 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) 83 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) 84 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) 85 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) 86 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) 87 88 #define PIN_PULL_SHIFT 11 89 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) 90 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) 91 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) 92 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) 93 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) 94 95 #define PIN_SLPM_SHIFT 13 96 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) 97 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) 98 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) 99 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) 100 /* These two replace the above in DB8500v2+ */ 101 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) 102 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) 103 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE 104 105 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ 106 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ 107 108 #define PIN_DIR_SHIFT 14 109 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) 110 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) 111 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) 112 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) 113 114 #define PIN_VAL_SHIFT 15 115 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) 116 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) 117 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) 118 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) 119 120 #define PIN_SLPM_PULL_SHIFT 16 121 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) 122 #define PIN_SLPM_PULL(x) \ 123 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) 124 #define PIN_SLPM_PULL_NONE \ 125 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) 126 #define PIN_SLPM_PULL_UP \ 127 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) 128 #define PIN_SLPM_PULL_DOWN \ 129 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) 130 131 #define PIN_SLPM_DIR_SHIFT 19 132 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) 133 #define PIN_SLPM_DIR(x) \ 134 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) 135 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) 136 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) 137 138 #define PIN_SLPM_VAL_SHIFT 21 139 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) 140 #define PIN_SLPM_VAL(x) \ 141 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) 142 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) 143 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) 144 145 #define PIN_SLPM_PDIS_SHIFT 23 146 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) 147 #define PIN_SLPM_PDIS(x) \ 148 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) 149 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) 150 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) 151 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) 152 153 #define PIN_LOWEMI_SHIFT 25 154 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) 155 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) 156 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) 157 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) 158 159 #define PIN_GPIOMODE_SHIFT 26 160 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) 161 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) 162 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) 163 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) 164 165 #define PIN_SLEEPMODE_SHIFT 27 166 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) 167 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) 168 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) 169 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) 170 171 172 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ 173 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) 174 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) 175 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) 176 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) 177 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) 178 179 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) 180 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) 181 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) 182 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) 183 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) 184 185 #define PIN_CFG_DEFAULT (0) 186 187 #define PIN_CFG(num, alt) \ 188 (PIN_CFG_DEFAULT |\ 189 (PIN_NUM(num) | PIN_##alt)) 190 191 #define PIN_CFG_INPUT(num, alt, pull) \ 192 (PIN_CFG_DEFAULT |\ 193 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) 194 195 #define PIN_CFG_OUTPUT(num, alt, val) \ 196 (PIN_CFG_DEFAULT |\ 197 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) 198 199 /* 200 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving 201 * the "gpio" namespace for generic and cross-machine functions 202 */ 203 204 #define GPIO_BLOCK_SHIFT 5 205 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) 206 207 /* Register in the logic block */ 208 #define NMK_GPIO_DAT 0x00 209 #define NMK_GPIO_DATS 0x04 210 #define NMK_GPIO_DATC 0x08 211 #define NMK_GPIO_PDIS 0x0c 212 #define NMK_GPIO_DIR 0x10 213 #define NMK_GPIO_DIRS 0x14 214 #define NMK_GPIO_DIRC 0x18 215 #define NMK_GPIO_SLPC 0x1c 216 #define NMK_GPIO_AFSLA 0x20 217 #define NMK_GPIO_AFSLB 0x24 218 #define NMK_GPIO_LOWEMI 0x28 219 220 #define NMK_GPIO_RIMSC 0x40 221 #define NMK_GPIO_FIMSC 0x44 222 #define NMK_GPIO_IS 0x48 223 #define NMK_GPIO_IC 0x4c 224 #define NMK_GPIO_RWIMSC 0x50 225 #define NMK_GPIO_FWIMSC 0x54 226 #define NMK_GPIO_WKS 0x58 227 /* These appear in DB8540 and later ASICs */ 228 #define NMK_GPIO_EDGELEVEL 0x5C 229 #define NMK_GPIO_LEVEL 0x60 230 231 232 /* Pull up/down values */ 233 enum nmk_gpio_pull { 234 NMK_GPIO_PULL_NONE, 235 NMK_GPIO_PULL_UP, 236 NMK_GPIO_PULL_DOWN, 237 }; 238 239 /* Sleep mode */ 240 enum nmk_gpio_slpm { 241 NMK_GPIO_SLPM_INPUT, 242 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, 243 NMK_GPIO_SLPM_NOCHANGE, 244 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, 245 }; 246 247 struct nmk_gpio_chip { 248 struct gpio_chip chip; 249 void __iomem *addr; 250 struct clk *clk; 251 unsigned int bank; 252 unsigned int parent_irq; 253 int latent_parent_irq; 254 u32 (*get_latent_status)(unsigned int bank); 255 void (*set_ioforce)(bool enable); 256 spinlock_t lock; 257 bool sleepmode; 258 /* Keep track of configured edges */ 259 u32 edge_rising; 260 u32 edge_falling; 261 u32 real_wake; 262 u32 rwimsc; 263 u32 fwimsc; 264 u32 rimsc; 265 u32 fimsc; 266 u32 pull_up; 267 u32 lowemi; 268 }; 269 270 /** 271 * struct nmk_pinctrl - state container for the Nomadik pin controller 272 * @dev: containing device pointer 273 * @pctl: corresponding pin controller device 274 * @soc: SoC data for this specific chip 275 * @prcm_base: PRCM register range virtual base 276 */ 277 struct nmk_pinctrl { 278 struct device *dev; 279 struct pinctrl_dev *pctl; 280 const struct nmk_pinctrl_soc_data *soc; 281 void __iomem *prcm_base; 282 }; 283 284 static struct nmk_gpio_chip * 285 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; 286 287 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); 288 289 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) 290 291 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, 292 unsigned offset, int gpio_mode) 293 { 294 u32 bit = 1 << offset; 295 u32 afunc, bfunc; 296 297 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; 298 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; 299 if (gpio_mode & NMK_GPIO_ALT_A) 300 afunc |= bit; 301 if (gpio_mode & NMK_GPIO_ALT_B) 302 bfunc |= bit; 303 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); 304 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); 305 } 306 307 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, 308 unsigned offset, enum nmk_gpio_slpm mode) 309 { 310 u32 bit = 1 << offset; 311 u32 slpm; 312 313 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); 314 if (mode == NMK_GPIO_SLPM_NOCHANGE) 315 slpm |= bit; 316 else 317 slpm &= ~bit; 318 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); 319 } 320 321 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, 322 unsigned offset, enum nmk_gpio_pull pull) 323 { 324 u32 bit = 1 << offset; 325 u32 pdis; 326 327 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); 328 if (pull == NMK_GPIO_PULL_NONE) { 329 pdis |= bit; 330 nmk_chip->pull_up &= ~bit; 331 } else { 332 pdis &= ~bit; 333 } 334 335 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); 336 337 if (pull == NMK_GPIO_PULL_UP) { 338 nmk_chip->pull_up |= bit; 339 writel(bit, nmk_chip->addr + NMK_GPIO_DATS); 340 } else if (pull == NMK_GPIO_PULL_DOWN) { 341 nmk_chip->pull_up &= ~bit; 342 writel(bit, nmk_chip->addr + NMK_GPIO_DATC); 343 } 344 } 345 346 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, 347 unsigned offset, bool lowemi) 348 { 349 u32 bit = BIT(offset); 350 bool enabled = nmk_chip->lowemi & bit; 351 352 if (lowemi == enabled) 353 return; 354 355 if (lowemi) 356 nmk_chip->lowemi |= bit; 357 else 358 nmk_chip->lowemi &= ~bit; 359 360 writel_relaxed(nmk_chip->lowemi, 361 nmk_chip->addr + NMK_GPIO_LOWEMI); 362 } 363 364 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, 365 unsigned offset) 366 { 367 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); 368 } 369 370 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, 371 unsigned offset, int val) 372 { 373 if (val) 374 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); 375 else 376 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); 377 } 378 379 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, 380 unsigned offset, int val) 381 { 382 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); 383 __nmk_gpio_set_output(nmk_chip, offset, val); 384 } 385 386 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, 387 unsigned offset, int gpio_mode, 388 bool glitch) 389 { 390 u32 rwimsc = nmk_chip->rwimsc; 391 u32 fwimsc = nmk_chip->fwimsc; 392 393 if (glitch && nmk_chip->set_ioforce) { 394 u32 bit = BIT(offset); 395 396 /* Prevent spurious wakeups */ 397 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); 398 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); 399 400 nmk_chip->set_ioforce(true); 401 } 402 403 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); 404 405 if (glitch && nmk_chip->set_ioforce) { 406 nmk_chip->set_ioforce(false); 407 408 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); 409 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); 410 } 411 } 412 413 static void 414 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) 415 { 416 u32 falling = nmk_chip->fimsc & BIT(offset); 417 u32 rising = nmk_chip->rimsc & BIT(offset); 418 int gpio = nmk_chip->chip.base + offset; 419 int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); 420 struct irq_data *d = irq_get_irq_data(irq); 421 422 if (!rising && !falling) 423 return; 424 425 if (!d || !irqd_irq_disabled(d)) 426 return; 427 428 if (rising) { 429 nmk_chip->rimsc &= ~BIT(offset); 430 writel_relaxed(nmk_chip->rimsc, 431 nmk_chip->addr + NMK_GPIO_RIMSC); 432 } 433 434 if (falling) { 435 nmk_chip->fimsc &= ~BIT(offset); 436 writel_relaxed(nmk_chip->fimsc, 437 nmk_chip->addr + NMK_GPIO_FIMSC); 438 } 439 440 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); 441 } 442 443 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) 444 { 445 u32 val; 446 447 val = readl(reg); 448 val = ((val & ~mask) | (value & mask)); 449 writel(val, reg); 450 } 451 452 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, 453 unsigned offset, unsigned alt_num) 454 { 455 int i; 456 u16 reg; 457 u8 bit; 458 u8 alt_index; 459 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 460 const u16 *gpiocr_regs; 461 462 if (!npct->prcm_base) 463 return; 464 465 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { 466 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", 467 alt_num); 468 return; 469 } 470 471 for (i = 0 ; i < npct->soc->npins_altcx ; i++) { 472 if (npct->soc->altcx_pins[i].pin == offset) 473 break; 474 } 475 if (i == npct->soc->npins_altcx) { 476 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", 477 offset); 478 return; 479 } 480 481 pin_desc = npct->soc->altcx_pins + i; 482 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 483 484 /* 485 * If alt_num is NULL, just clear current ALTCx selection 486 * to make sure we come back to a pure ALTC selection 487 */ 488 if (!alt_num) { 489 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 490 if (pin_desc->altcx[i].used == true) { 491 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 492 bit = pin_desc->altcx[i].control_bit; 493 if (readl(npct->prcm_base + reg) & BIT(bit)) { 494 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 495 dev_dbg(npct->dev, 496 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 497 offset, i+1); 498 } 499 } 500 } 501 return; 502 } 503 504 alt_index = alt_num - 1; 505 if (pin_desc->altcx[alt_index].used == false) { 506 dev_warn(npct->dev, 507 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", 508 offset, alt_num); 509 return; 510 } 511 512 /* 513 * Check if any other ALTCx functions are activated on this pin 514 * and disable it first. 515 */ 516 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 517 if (i == alt_index) 518 continue; 519 if (pin_desc->altcx[i].used == true) { 520 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 521 bit = pin_desc->altcx[i].control_bit; 522 if (readl(npct->prcm_base + reg) & BIT(bit)) { 523 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 524 dev_dbg(npct->dev, 525 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 526 offset, i+1); 527 } 528 } 529 } 530 531 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; 532 bit = pin_desc->altcx[alt_index].control_bit; 533 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", 534 offset, alt_index+1); 535 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); 536 } 537 538 /* 539 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 540 * - Save SLPM registers 541 * - Set SLPM=0 for the IOs you want to switch and others to 1 542 * - Configure the GPIO registers for the IOs that are being switched 543 * - Set IOFORCE=1 544 * - Modify the AFLSA/B registers for the IOs that are being switched 545 * - Set IOFORCE=0 546 * - Restore SLPM registers 547 * - Any spurious wake up event during switch sequence to be ignored and 548 * cleared 549 */ 550 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) 551 { 552 int i; 553 554 for (i = 0; i < NUM_BANKS; i++) { 555 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 556 unsigned int temp = slpm[i]; 557 558 if (!chip) 559 break; 560 561 clk_enable(chip->clk); 562 563 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); 564 writel(temp, chip->addr + NMK_GPIO_SLPC); 565 } 566 } 567 568 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) 569 { 570 int i; 571 572 for (i = 0; i < NUM_BANKS; i++) { 573 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 574 575 if (!chip) 576 break; 577 578 writel(slpm[i], chip->addr + NMK_GPIO_SLPC); 579 580 clk_disable(chip->clk); 581 } 582 } 583 584 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) 585 { 586 int i; 587 u16 reg; 588 u8 bit; 589 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 590 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 591 const u16 *gpiocr_regs; 592 593 if (!npct->prcm_base) 594 return NMK_GPIO_ALT_C; 595 596 for (i = 0; i < npct->soc->npins_altcx; i++) { 597 if (npct->soc->altcx_pins[i].pin == gpio) 598 break; 599 } 600 if (i == npct->soc->npins_altcx) 601 return NMK_GPIO_ALT_C; 602 603 pin_desc = npct->soc->altcx_pins + i; 604 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 605 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { 606 if (pin_desc->altcx[i].used == true) { 607 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 608 bit = pin_desc->altcx[i].control_bit; 609 if (readl(npct->prcm_base + reg) & BIT(bit)) 610 return NMK_GPIO_ALT_C+i+1; 611 } 612 } 613 return NMK_GPIO_ALT_C; 614 } 615 616 int nmk_gpio_get_mode(int gpio) 617 { 618 struct nmk_gpio_chip *nmk_chip; 619 u32 afunc, bfunc, bit; 620 621 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; 622 if (!nmk_chip) 623 return -EINVAL; 624 625 bit = 1 << (gpio % NMK_GPIO_PER_CHIP); 626 627 clk_enable(nmk_chip->clk); 628 629 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; 630 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; 631 632 clk_disable(nmk_chip->clk); 633 634 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); 635 } 636 EXPORT_SYMBOL(nmk_gpio_get_mode); 637 638 639 /* IRQ functions */ 640 static inline int nmk_gpio_get_bitmask(int gpio) 641 { 642 return 1 << (gpio % NMK_GPIO_PER_CHIP); 643 } 644 645 static void nmk_gpio_irq_ack(struct irq_data *d) 646 { 647 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 648 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 649 650 clk_enable(nmk_chip->clk); 651 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); 652 clk_disable(nmk_chip->clk); 653 } 654 655 enum nmk_gpio_irq_type { 656 NORMAL, 657 WAKE, 658 }; 659 660 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, 661 int gpio, enum nmk_gpio_irq_type which, 662 bool enable) 663 { 664 u32 bitmask = nmk_gpio_get_bitmask(gpio); 665 u32 *rimscval; 666 u32 *fimscval; 667 u32 rimscreg; 668 u32 fimscreg; 669 670 if (which == NORMAL) { 671 rimscreg = NMK_GPIO_RIMSC; 672 fimscreg = NMK_GPIO_FIMSC; 673 rimscval = &nmk_chip->rimsc; 674 fimscval = &nmk_chip->fimsc; 675 } else { 676 rimscreg = NMK_GPIO_RWIMSC; 677 fimscreg = NMK_GPIO_FWIMSC; 678 rimscval = &nmk_chip->rwimsc; 679 fimscval = &nmk_chip->fwimsc; 680 } 681 682 /* we must individually set/clear the two edges */ 683 if (nmk_chip->edge_rising & bitmask) { 684 if (enable) 685 *rimscval |= bitmask; 686 else 687 *rimscval &= ~bitmask; 688 writel(*rimscval, nmk_chip->addr + rimscreg); 689 } 690 if (nmk_chip->edge_falling & bitmask) { 691 if (enable) 692 *fimscval |= bitmask; 693 else 694 *fimscval &= ~bitmask; 695 writel(*fimscval, nmk_chip->addr + fimscreg); 696 } 697 } 698 699 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 700 int gpio, bool on) 701 { 702 /* 703 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is 704 * disabled, since setting SLPM to 1 increases power consumption, and 705 * wakeup is anyhow controlled by the RIMSC and FIMSC registers. 706 */ 707 if (nmk_chip->sleepmode && on) { 708 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, 709 NMK_GPIO_SLPM_WAKEUP_ENABLE); 710 } 711 712 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); 713 } 714 715 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) 716 { 717 struct nmk_gpio_chip *nmk_chip; 718 unsigned long flags; 719 u32 bitmask; 720 721 nmk_chip = irq_data_get_irq_chip_data(d); 722 bitmask = nmk_gpio_get_bitmask(d->hwirq); 723 if (!nmk_chip) 724 return -EINVAL; 725 726 clk_enable(nmk_chip->clk); 727 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 728 spin_lock(&nmk_chip->lock); 729 730 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); 731 732 if (!(nmk_chip->real_wake & bitmask)) 733 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); 734 735 spin_unlock(&nmk_chip->lock); 736 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 737 clk_disable(nmk_chip->clk); 738 739 return 0; 740 } 741 742 static void nmk_gpio_irq_mask(struct irq_data *d) 743 { 744 nmk_gpio_irq_maskunmask(d, false); 745 } 746 747 static void nmk_gpio_irq_unmask(struct irq_data *d) 748 { 749 nmk_gpio_irq_maskunmask(d, true); 750 } 751 752 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 753 { 754 struct nmk_gpio_chip *nmk_chip; 755 unsigned long flags; 756 u32 bitmask; 757 758 nmk_chip = irq_data_get_irq_chip_data(d); 759 if (!nmk_chip) 760 return -EINVAL; 761 bitmask = nmk_gpio_get_bitmask(d->hwirq); 762 763 clk_enable(nmk_chip->clk); 764 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 765 spin_lock(&nmk_chip->lock); 766 767 if (irqd_irq_disabled(d)) 768 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); 769 770 if (on) 771 nmk_chip->real_wake |= bitmask; 772 else 773 nmk_chip->real_wake &= ~bitmask; 774 775 spin_unlock(&nmk_chip->lock); 776 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 777 clk_disable(nmk_chip->clk); 778 779 return 0; 780 } 781 782 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) 783 { 784 bool enabled = !irqd_irq_disabled(d); 785 bool wake = irqd_is_wakeup_set(d); 786 struct nmk_gpio_chip *nmk_chip; 787 unsigned long flags; 788 u32 bitmask; 789 790 nmk_chip = irq_data_get_irq_chip_data(d); 791 bitmask = nmk_gpio_get_bitmask(d->hwirq); 792 if (!nmk_chip) 793 return -EINVAL; 794 if (type & IRQ_TYPE_LEVEL_HIGH) 795 return -EINVAL; 796 if (type & IRQ_TYPE_LEVEL_LOW) 797 return -EINVAL; 798 799 clk_enable(nmk_chip->clk); 800 spin_lock_irqsave(&nmk_chip->lock, flags); 801 802 if (enabled) 803 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); 804 805 if (enabled || wake) 806 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); 807 808 nmk_chip->edge_rising &= ~bitmask; 809 if (type & IRQ_TYPE_EDGE_RISING) 810 nmk_chip->edge_rising |= bitmask; 811 812 nmk_chip->edge_falling &= ~bitmask; 813 if (type & IRQ_TYPE_EDGE_FALLING) 814 nmk_chip->edge_falling |= bitmask; 815 816 if (enabled) 817 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); 818 819 if (enabled || wake) 820 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); 821 822 spin_unlock_irqrestore(&nmk_chip->lock, flags); 823 clk_disable(nmk_chip->clk); 824 825 return 0; 826 } 827 828 static unsigned int nmk_gpio_irq_startup(struct irq_data *d) 829 { 830 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 831 832 clk_enable(nmk_chip->clk); 833 nmk_gpio_irq_unmask(d); 834 return 0; 835 } 836 837 static void nmk_gpio_irq_shutdown(struct irq_data *d) 838 { 839 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 840 841 nmk_gpio_irq_mask(d); 842 clk_disable(nmk_chip->clk); 843 } 844 845 static struct irq_chip nmk_gpio_irq_chip = { 846 .name = "Nomadik-GPIO", 847 .irq_ack = nmk_gpio_irq_ack, 848 .irq_mask = nmk_gpio_irq_mask, 849 .irq_unmask = nmk_gpio_irq_unmask, 850 .irq_set_type = nmk_gpio_irq_set_type, 851 .irq_set_wake = nmk_gpio_irq_set_wake, 852 .irq_startup = nmk_gpio_irq_startup, 853 .irq_shutdown = nmk_gpio_irq_shutdown, 854 .flags = IRQCHIP_MASK_ON_SUSPEND, 855 }; 856 857 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, 858 u32 status) 859 { 860 struct irq_chip *host_chip = irq_get_chip(irq); 861 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 862 863 chained_irq_enter(host_chip, desc); 864 865 while (status) { 866 int bit = __ffs(status); 867 868 generic_handle_irq(irq_find_mapping(chip->irqdomain, bit)); 869 status &= ~BIT(bit); 870 } 871 872 chained_irq_exit(host_chip, desc); 873 } 874 875 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 876 { 877 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 878 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 879 u32 status; 880 881 clk_enable(nmk_chip->clk); 882 status = readl(nmk_chip->addr + NMK_GPIO_IS); 883 clk_disable(nmk_chip->clk); 884 885 __nmk_gpio_irq_handler(irq, desc, status); 886 } 887 888 static void nmk_gpio_latent_irq_handler(unsigned int irq, 889 struct irq_desc *desc) 890 { 891 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 892 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 893 u32 status = nmk_chip->get_latent_status(nmk_chip->bank); 894 895 __nmk_gpio_irq_handler(irq, desc, status); 896 } 897 898 /* I/O Functions */ 899 900 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) 901 { 902 /* 903 * Map back to global GPIO space and request muxing, the direction 904 * parameter does not matter for this controller. 905 */ 906 int gpio = chip->base + offset; 907 908 return pinctrl_request_gpio(gpio); 909 } 910 911 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) 912 { 913 int gpio = chip->base + offset; 914 915 pinctrl_free_gpio(gpio); 916 } 917 918 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) 919 { 920 struct nmk_gpio_chip *nmk_chip = 921 container_of(chip, struct nmk_gpio_chip, chip); 922 923 clk_enable(nmk_chip->clk); 924 925 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); 926 927 clk_disable(nmk_chip->clk); 928 929 return 0; 930 } 931 932 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) 933 { 934 struct nmk_gpio_chip *nmk_chip = 935 container_of(chip, struct nmk_gpio_chip, chip); 936 u32 bit = 1 << offset; 937 int value; 938 939 clk_enable(nmk_chip->clk); 940 941 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; 942 943 clk_disable(nmk_chip->clk); 944 945 return value; 946 } 947 948 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, 949 int val) 950 { 951 struct nmk_gpio_chip *nmk_chip = 952 container_of(chip, struct nmk_gpio_chip, chip); 953 954 clk_enable(nmk_chip->clk); 955 956 __nmk_gpio_set_output(nmk_chip, offset, val); 957 958 clk_disable(nmk_chip->clk); 959 } 960 961 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, 962 int val) 963 { 964 struct nmk_gpio_chip *nmk_chip = 965 container_of(chip, struct nmk_gpio_chip, chip); 966 967 clk_enable(nmk_chip->clk); 968 969 __nmk_gpio_make_output(nmk_chip, offset, val); 970 971 clk_disable(nmk_chip->clk); 972 973 return 0; 974 } 975 976 #ifdef CONFIG_DEBUG_FS 977 978 #include <linux/seq_file.h> 979 980 static void nmk_gpio_dbg_show_one(struct seq_file *s, 981 struct pinctrl_dev *pctldev, struct gpio_chip *chip, 982 unsigned offset, unsigned gpio) 983 { 984 const char *label = gpiochip_is_requested(chip, offset); 985 struct nmk_gpio_chip *nmk_chip = 986 container_of(chip, struct nmk_gpio_chip, chip); 987 int mode; 988 bool is_out; 989 bool data_out; 990 bool pull; 991 u32 bit = 1 << offset; 992 const char *modes[] = { 993 [NMK_GPIO_ALT_GPIO] = "gpio", 994 [NMK_GPIO_ALT_A] = "altA", 995 [NMK_GPIO_ALT_B] = "altB", 996 [NMK_GPIO_ALT_C] = "altC", 997 [NMK_GPIO_ALT_C+1] = "altC1", 998 [NMK_GPIO_ALT_C+2] = "altC2", 999 [NMK_GPIO_ALT_C+3] = "altC3", 1000 [NMK_GPIO_ALT_C+4] = "altC4", 1001 }; 1002 const char *pulls[] = { 1003 "none ", 1004 "pull down", 1005 "pull up ", 1006 }; 1007 1008 clk_enable(nmk_chip->clk); 1009 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); 1010 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); 1011 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & bit); 1012 mode = nmk_gpio_get_mode(gpio); 1013 if ((mode == NMK_GPIO_ALT_C) && pctldev) 1014 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); 1015 1016 if (is_out) { 1017 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", 1018 gpio, 1019 label ?: "(none)", 1020 data_out ? "hi" : "lo", 1021 (mode < 0) ? "unknown" : modes[mode]); 1022 } else { 1023 int irq = gpio_to_irq(gpio); 1024 struct irq_desc *desc = irq_to_desc(irq); 1025 int pullidx = 0; 1026 1027 if (pull) 1028 pullidx = data_out ? 1 : 2; 1029 1030 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", 1031 gpio, 1032 label ?: "(none)", 1033 pulls[pullidx], 1034 (mode < 0) ? "unknown" : modes[mode]); 1035 /* 1036 * This races with request_irq(), set_irq_type(), 1037 * and set_irq_wake() ... but those are "rare". 1038 */ 1039 if (irq > 0 && desc && desc->action) { 1040 char *trigger; 1041 u32 bitmask = nmk_gpio_get_bitmask(gpio); 1042 1043 if (nmk_chip->edge_rising & bitmask) 1044 trigger = "edge-rising"; 1045 else if (nmk_chip->edge_falling & bitmask) 1046 trigger = "edge-falling"; 1047 else 1048 trigger = "edge-undefined"; 1049 1050 seq_printf(s, " irq-%d %s%s", 1051 irq, trigger, 1052 irqd_is_wakeup_set(&desc->irq_data) 1053 ? " wakeup" : ""); 1054 } 1055 } 1056 clk_disable(nmk_chip->clk); 1057 } 1058 1059 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1060 { 1061 unsigned i; 1062 unsigned gpio = chip->base; 1063 1064 for (i = 0; i < chip->ngpio; i++, gpio++) { 1065 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); 1066 seq_printf(s, "\n"); 1067 } 1068 } 1069 1070 #else 1071 static inline void nmk_gpio_dbg_show_one(struct seq_file *s, 1072 struct pinctrl_dev *pctldev, 1073 struct gpio_chip *chip, 1074 unsigned offset, unsigned gpio) 1075 { 1076 } 1077 #define nmk_gpio_dbg_show NULL 1078 #endif 1079 1080 /* This structure is replicated for each GPIO block allocated at probe time */ 1081 static struct gpio_chip nmk_gpio_template = { 1082 .request = nmk_gpio_request, 1083 .free = nmk_gpio_free, 1084 .direction_input = nmk_gpio_make_input, 1085 .get = nmk_gpio_get_input, 1086 .direction_output = nmk_gpio_make_output, 1087 .set = nmk_gpio_set_output, 1088 .dbg_show = nmk_gpio_dbg_show, 1089 .can_sleep = false, 1090 }; 1091 1092 void nmk_gpio_clocks_enable(void) 1093 { 1094 int i; 1095 1096 for (i = 0; i < NUM_BANKS; i++) { 1097 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 1098 1099 if (!chip) 1100 continue; 1101 1102 clk_enable(chip->clk); 1103 } 1104 } 1105 1106 void nmk_gpio_clocks_disable(void) 1107 { 1108 int i; 1109 1110 for (i = 0; i < NUM_BANKS; i++) { 1111 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 1112 1113 if (!chip) 1114 continue; 1115 1116 clk_disable(chip->clk); 1117 } 1118 } 1119 1120 /* 1121 * Called from the suspend/resume path to only keep the real wakeup interrupts 1122 * (those that have had set_irq_wake() called on them) as wakeup interrupts, 1123 * and not the rest of the interrupts which we needed to have as wakeups for 1124 * cpuidle. 1125 * 1126 * PM ops are not used since this needs to be done at the end, after all the 1127 * other drivers are done with their suspend callbacks. 1128 */ 1129 void nmk_gpio_wakeups_suspend(void) 1130 { 1131 int i; 1132 1133 for (i = 0; i < NUM_BANKS; i++) { 1134 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 1135 1136 if (!chip) 1137 break; 1138 1139 clk_enable(chip->clk); 1140 1141 writel(chip->rwimsc & chip->real_wake, 1142 chip->addr + NMK_GPIO_RWIMSC); 1143 writel(chip->fwimsc & chip->real_wake, 1144 chip->addr + NMK_GPIO_FWIMSC); 1145 1146 clk_disable(chip->clk); 1147 } 1148 } 1149 1150 void nmk_gpio_wakeups_resume(void) 1151 { 1152 int i; 1153 1154 for (i = 0; i < NUM_BANKS; i++) { 1155 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 1156 1157 if (!chip) 1158 break; 1159 1160 clk_enable(chip->clk); 1161 1162 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); 1163 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); 1164 1165 clk_disable(chip->clk); 1166 } 1167 } 1168 1169 /* 1170 * Read the pull up/pull down status. 1171 * A bit set in 'pull_up' means that pull up 1172 * is selected if pull is enabled in PDIS register. 1173 * Note: only pull up/down set via this driver can 1174 * be detected due to HW limitations. 1175 */ 1176 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) 1177 { 1178 if (gpio_bank < NUM_BANKS) { 1179 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; 1180 1181 if (!chip) 1182 return; 1183 1184 *pull_up = chip->pull_up; 1185 } 1186 } 1187 1188 static int nmk_gpio_probe(struct platform_device *dev) 1189 { 1190 struct device_node *np = dev->dev.of_node; 1191 struct nmk_gpio_chip *nmk_chip; 1192 struct gpio_chip *chip; 1193 struct resource *res; 1194 struct clk *clk; 1195 int latent_irq; 1196 bool supports_sleepmode; 1197 void __iomem *base; 1198 int irq; 1199 int ret; 1200 1201 if (of_get_property(np, "st,supports-sleepmode", NULL)) 1202 supports_sleepmode = true; 1203 else 1204 supports_sleepmode = false; 1205 1206 if (of_property_read_u32(np, "gpio-bank", &dev->id)) { 1207 dev_err(&dev->dev, "gpio-bank property not found\n"); 1208 return -EINVAL; 1209 } 1210 1211 irq = platform_get_irq(dev, 0); 1212 if (irq < 0) 1213 return irq; 1214 1215 /* It's OK for this IRQ not to be present */ 1216 latent_irq = platform_get_irq(dev, 1); 1217 1218 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1219 base = devm_ioremap_resource(&dev->dev, res); 1220 if (IS_ERR(base)) 1221 return PTR_ERR(base); 1222 1223 clk = devm_clk_get(&dev->dev, NULL); 1224 if (IS_ERR(clk)) 1225 return PTR_ERR(clk); 1226 clk_prepare(clk); 1227 1228 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL); 1229 if (!nmk_chip) 1230 return -ENOMEM; 1231 1232 /* 1233 * The virt address in nmk_chip->addr is in the nomadik register space, 1234 * so we can simply convert the resource address, without remapping 1235 */ 1236 nmk_chip->bank = dev->id; 1237 nmk_chip->clk = clk; 1238 nmk_chip->addr = base; 1239 nmk_chip->chip = nmk_gpio_template; 1240 nmk_chip->parent_irq = irq; 1241 nmk_chip->latent_parent_irq = latent_irq; 1242 nmk_chip->sleepmode = supports_sleepmode; 1243 spin_lock_init(&nmk_chip->lock); 1244 1245 chip = &nmk_chip->chip; 1246 chip->base = dev->id * NMK_GPIO_PER_CHIP; 1247 chip->ngpio = NMK_GPIO_PER_CHIP; 1248 chip->label = dev_name(&dev->dev); 1249 chip->dev = &dev->dev; 1250 chip->owner = THIS_MODULE; 1251 1252 clk_enable(nmk_chip->clk); 1253 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 1254 clk_disable(nmk_chip->clk); 1255 chip->of_node = np; 1256 1257 ret = gpiochip_add(&nmk_chip->chip); 1258 if (ret) 1259 return ret; 1260 1261 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 1262 1263 nmk_gpio_chips[nmk_chip->bank] = nmk_chip; 1264 1265 platform_set_drvdata(dev, nmk_chip); 1266 1267 /* 1268 * Let the generic code handle this edge IRQ, the the chained 1269 * handler will perform the actual work of handling the parent 1270 * interrupt. 1271 */ 1272 ret = gpiochip_irqchip_add(&nmk_chip->chip, 1273 &nmk_gpio_irq_chip, 1274 0, 1275 handle_edge_irq, 1276 IRQ_TYPE_EDGE_FALLING); 1277 if (ret) { 1278 dev_err(&dev->dev, "could not add irqchip\n"); 1279 gpiochip_remove(&nmk_chip->chip); 1280 return -ENODEV; 1281 } 1282 /* Then register the chain on the parent IRQ */ 1283 gpiochip_set_chained_irqchip(&nmk_chip->chip, 1284 &nmk_gpio_irq_chip, 1285 nmk_chip->parent_irq, 1286 nmk_gpio_irq_handler); 1287 if (nmk_chip->latent_parent_irq > 0) 1288 gpiochip_set_chained_irqchip(&nmk_chip->chip, 1289 &nmk_gpio_irq_chip, 1290 nmk_chip->latent_parent_irq, 1291 nmk_gpio_latent_irq_handler); 1292 1293 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); 1294 1295 return 0; 1296 } 1297 1298 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) 1299 { 1300 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1301 1302 return npct->soc->ngroups; 1303 } 1304 1305 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, 1306 unsigned selector) 1307 { 1308 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1309 1310 return npct->soc->groups[selector].name; 1311 } 1312 1313 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 1314 const unsigned **pins, 1315 unsigned *num_pins) 1316 { 1317 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1318 1319 *pins = npct->soc->groups[selector].pins; 1320 *num_pins = npct->soc->groups[selector].npins; 1321 return 0; 1322 } 1323 1324 static struct pinctrl_gpio_range * 1325 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) 1326 { 1327 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1328 int i; 1329 1330 for (i = 0; i < npct->soc->gpio_num_ranges; i++) { 1331 struct pinctrl_gpio_range *range; 1332 1333 range = &npct->soc->gpio_ranges[i]; 1334 if (offset >= range->pin_base && 1335 offset <= (range->pin_base + range->npins - 1)) 1336 return range; 1337 } 1338 return NULL; 1339 } 1340 1341 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1342 unsigned offset) 1343 { 1344 struct pinctrl_gpio_range *range; 1345 struct gpio_chip *chip; 1346 1347 range = nmk_match_gpio_range(pctldev, offset); 1348 if (!range || !range->gc) { 1349 seq_printf(s, "invalid pin offset"); 1350 return; 1351 } 1352 chip = range->gc; 1353 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 1354 } 1355 1356 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, 1357 unsigned *num_maps, const char *group, 1358 const char *function) 1359 { 1360 if (*num_maps == *reserved_maps) 1361 return -ENOSPC; 1362 1363 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 1364 (*map)[*num_maps].data.mux.group = group; 1365 (*map)[*num_maps].data.mux.function = function; 1366 (*num_maps)++; 1367 1368 return 0; 1369 } 1370 1371 static int nmk_dt_add_map_configs(struct pinctrl_map **map, 1372 unsigned *reserved_maps, 1373 unsigned *num_maps, const char *group, 1374 unsigned long *configs, unsigned num_configs) 1375 { 1376 unsigned long *dup_configs; 1377 1378 if (*num_maps == *reserved_maps) 1379 return -ENOSPC; 1380 1381 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 1382 GFP_KERNEL); 1383 if (!dup_configs) 1384 return -ENOMEM; 1385 1386 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; 1387 1388 (*map)[*num_maps].data.configs.group_or_pin = group; 1389 (*map)[*num_maps].data.configs.configs = dup_configs; 1390 (*map)[*num_maps].data.configs.num_configs = num_configs; 1391 (*num_maps)++; 1392 1393 return 0; 1394 } 1395 1396 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } 1397 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ 1398 .size = ARRAY_SIZE(y), } 1399 1400 static const unsigned long nmk_pin_input_modes[] = { 1401 PIN_INPUT_NOPULL, 1402 PIN_INPUT_PULLUP, 1403 PIN_INPUT_PULLDOWN, 1404 }; 1405 1406 static const unsigned long nmk_pin_output_modes[] = { 1407 PIN_OUTPUT_LOW, 1408 PIN_OUTPUT_HIGH, 1409 PIN_DIR_OUTPUT, 1410 }; 1411 1412 static const unsigned long nmk_pin_sleep_modes[] = { 1413 PIN_SLEEPMODE_DISABLED, 1414 PIN_SLEEPMODE_ENABLED, 1415 }; 1416 1417 static const unsigned long nmk_pin_sleep_input_modes[] = { 1418 PIN_SLPM_INPUT_NOPULL, 1419 PIN_SLPM_INPUT_PULLUP, 1420 PIN_SLPM_INPUT_PULLDOWN, 1421 PIN_SLPM_DIR_INPUT, 1422 }; 1423 1424 static const unsigned long nmk_pin_sleep_output_modes[] = { 1425 PIN_SLPM_OUTPUT_LOW, 1426 PIN_SLPM_OUTPUT_HIGH, 1427 PIN_SLPM_DIR_OUTPUT, 1428 }; 1429 1430 static const unsigned long nmk_pin_sleep_wakeup_modes[] = { 1431 PIN_SLPM_WAKEUP_DISABLE, 1432 PIN_SLPM_WAKEUP_ENABLE, 1433 }; 1434 1435 static const unsigned long nmk_pin_gpio_modes[] = { 1436 PIN_GPIOMODE_DISABLED, 1437 PIN_GPIOMODE_ENABLED, 1438 }; 1439 1440 static const unsigned long nmk_pin_sleep_pdis_modes[] = { 1441 PIN_SLPM_PDIS_DISABLED, 1442 PIN_SLPM_PDIS_ENABLED, 1443 }; 1444 1445 struct nmk_cfg_param { 1446 const char *property; 1447 unsigned long config; 1448 const unsigned long *choice; 1449 int size; 1450 }; 1451 1452 static const struct nmk_cfg_param nmk_cfg_params[] = { 1453 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), 1454 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), 1455 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), 1456 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), 1457 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), 1458 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), 1459 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), 1460 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), 1461 }; 1462 1463 static int nmk_dt_pin_config(int index, int val, unsigned long *config) 1464 { 1465 int ret = 0; 1466 1467 if (nmk_cfg_params[index].choice == NULL) 1468 *config = nmk_cfg_params[index].config; 1469 else { 1470 /* test if out of range */ 1471 if (val < nmk_cfg_params[index].size) { 1472 *config = nmk_cfg_params[index].config | 1473 nmk_cfg_params[index].choice[val]; 1474 } 1475 } 1476 return ret; 1477 } 1478 1479 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) 1480 { 1481 int i, pin_number; 1482 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1483 1484 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) 1485 for (i = 0; i < npct->soc->npins; i++) 1486 if (npct->soc->pins[i].number == pin_number) 1487 return npct->soc->pins[i].name; 1488 return NULL; 1489 } 1490 1491 static bool nmk_pinctrl_dt_get_config(struct device_node *np, 1492 unsigned long *configs) 1493 { 1494 bool has_config = 0; 1495 unsigned long cfg = 0; 1496 int i, val, ret; 1497 1498 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { 1499 ret = of_property_read_u32(np, 1500 nmk_cfg_params[i].property, &val); 1501 if (ret != -EINVAL) { 1502 if (nmk_dt_pin_config(i, val, &cfg) == 0) { 1503 *configs |= cfg; 1504 has_config = 1; 1505 } 1506 } 1507 } 1508 1509 return has_config; 1510 } 1511 1512 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 1513 struct device_node *np, 1514 struct pinctrl_map **map, 1515 unsigned *reserved_maps, 1516 unsigned *num_maps) 1517 { 1518 int ret; 1519 const char *function = NULL; 1520 unsigned long configs = 0; 1521 bool has_config = 0; 1522 struct property *prop; 1523 const char *group, *gpio_name; 1524 struct device_node *np_config; 1525 1526 ret = of_property_read_string(np, "ste,function", &function); 1527 if (ret >= 0) { 1528 ret = of_property_count_strings(np, "ste,pins"); 1529 if (ret < 0) 1530 goto exit; 1531 1532 ret = pinctrl_utils_reserve_map(pctldev, map, 1533 reserved_maps, 1534 num_maps, ret); 1535 if (ret < 0) 1536 goto exit; 1537 1538 of_property_for_each_string(np, "ste,pins", prop, group) { 1539 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, 1540 group, function); 1541 if (ret < 0) 1542 goto exit; 1543 } 1544 } 1545 1546 has_config = nmk_pinctrl_dt_get_config(np, &configs); 1547 np_config = of_parse_phandle(np, "ste,config", 0); 1548 if (np_config) 1549 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); 1550 if (has_config) { 1551 ret = of_property_count_strings(np, "ste,pins"); 1552 if (ret < 0) 1553 goto exit; 1554 ret = pinctrl_utils_reserve_map(pctldev, map, 1555 reserved_maps, 1556 num_maps, ret); 1557 if (ret < 0) 1558 goto exit; 1559 1560 of_property_for_each_string(np, "ste,pins", prop, group) { 1561 gpio_name = nmk_find_pin_name(pctldev, group); 1562 1563 ret = nmk_dt_add_map_configs(map, reserved_maps, 1564 num_maps, 1565 gpio_name, &configs, 1); 1566 if (ret < 0) 1567 goto exit; 1568 } 1569 } 1570 1571 exit: 1572 return ret; 1573 } 1574 1575 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 1576 struct device_node *np_config, 1577 struct pinctrl_map **map, unsigned *num_maps) 1578 { 1579 unsigned reserved_maps; 1580 struct device_node *np; 1581 int ret; 1582 1583 reserved_maps = 0; 1584 *map = NULL; 1585 *num_maps = 0; 1586 1587 for_each_child_of_node(np_config, np) { 1588 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, 1589 &reserved_maps, num_maps); 1590 if (ret < 0) { 1591 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); 1592 return ret; 1593 } 1594 } 1595 1596 return 0; 1597 } 1598 1599 static const struct pinctrl_ops nmk_pinctrl_ops = { 1600 .get_groups_count = nmk_get_groups_cnt, 1601 .get_group_name = nmk_get_group_name, 1602 .get_group_pins = nmk_get_group_pins, 1603 .pin_dbg_show = nmk_pin_dbg_show, 1604 .dt_node_to_map = nmk_pinctrl_dt_node_to_map, 1605 .dt_free_map = pinctrl_utils_dt_free_map, 1606 }; 1607 1608 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 1609 { 1610 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1611 1612 return npct->soc->nfunctions; 1613 } 1614 1615 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, 1616 unsigned function) 1617 { 1618 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1619 1620 return npct->soc->functions[function].name; 1621 } 1622 1623 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 1624 unsigned function, 1625 const char * const **groups, 1626 unsigned * const num_groups) 1627 { 1628 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1629 1630 *groups = npct->soc->functions[function].groups; 1631 *num_groups = npct->soc->functions[function].ngroups; 1632 1633 return 0; 1634 } 1635 1636 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function, 1637 unsigned group) 1638 { 1639 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1640 const struct nmk_pingroup *g; 1641 static unsigned int slpm[NUM_BANKS]; 1642 unsigned long flags = 0; 1643 bool glitch; 1644 int ret = -EINVAL; 1645 int i; 1646 1647 g = &npct->soc->groups[group]; 1648 1649 if (g->altsetting < 0) 1650 return -EINVAL; 1651 1652 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); 1653 1654 /* 1655 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, 1656 * we may pass through an undesired state. In this case we take 1657 * some extra care. 1658 * 1659 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 1660 * - Save SLPM registers (since we have a shadow register in the 1661 * nmk_chip we're using that as backup) 1662 * - Set SLPM=0 for the IOs you want to switch and others to 1 1663 * - Configure the GPIO registers for the IOs that are being switched 1664 * - Set IOFORCE=1 1665 * - Modify the AFLSA/B registers for the IOs that are being switched 1666 * - Set IOFORCE=0 1667 * - Restore SLPM registers 1668 * - Any spurious wake up event during switch sequence to be ignored 1669 * and cleared 1670 * 1671 * We REALLY need to save ALL slpm registers, because the external 1672 * IOFORCE will switch *all* ports to their sleepmode setting to as 1673 * to avoid glitches. (Not just one port!) 1674 */ 1675 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); 1676 1677 if (glitch) { 1678 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 1679 1680 /* Initially don't put any pins to sleep when switching */ 1681 memset(slpm, 0xff, sizeof(slpm)); 1682 1683 /* 1684 * Then mask the pins that need to be sleeping now when we're 1685 * switching to the ALT C function. 1686 */ 1687 for (i = 0; i < g->npins; i++) 1688 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); 1689 nmk_gpio_glitch_slpm_init(slpm); 1690 } 1691 1692 for (i = 0; i < g->npins; i++) { 1693 struct pinctrl_gpio_range *range; 1694 struct nmk_gpio_chip *nmk_chip; 1695 struct gpio_chip *chip; 1696 unsigned bit; 1697 1698 range = nmk_match_gpio_range(pctldev, g->pins[i]); 1699 if (!range) { 1700 dev_err(npct->dev, 1701 "invalid pin offset %d in group %s at index %d\n", 1702 g->pins[i], g->name, i); 1703 goto out_glitch; 1704 } 1705 if (!range->gc) { 1706 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", 1707 g->pins[i], g->name, i); 1708 goto out_glitch; 1709 } 1710 chip = range->gc; 1711 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 1712 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); 1713 1714 clk_enable(nmk_chip->clk); 1715 bit = g->pins[i] % NMK_GPIO_PER_CHIP; 1716 /* 1717 * If the pin is switching to altfunc, and there was an 1718 * interrupt installed on it which has been lazy disabled, 1719 * actually mask the interrupt to prevent spurious interrupts 1720 * that would occur while the pin is under control of the 1721 * peripheral. Only SKE does this. 1722 */ 1723 nmk_gpio_disable_lazy_irq(nmk_chip, bit); 1724 1725 __nmk_gpio_set_mode_safe(nmk_chip, bit, 1726 (g->altsetting & NMK_GPIO_ALT_C), glitch); 1727 clk_disable(nmk_chip->clk); 1728 1729 /* 1730 * Call PRCM GPIOCR config function in case ALTC 1731 * has been selected: 1732 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers 1733 * must be set. 1734 * - If selection is pure ALTC and previous selection was ALTCx, 1735 * then some bits in PRCM GPIOCR registers must be cleared. 1736 */ 1737 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) 1738 nmk_prcm_altcx_set_mode(npct, g->pins[i], 1739 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); 1740 } 1741 1742 /* When all pins are successfully reconfigured we get here */ 1743 ret = 0; 1744 1745 out_glitch: 1746 if (glitch) { 1747 nmk_gpio_glitch_slpm_restore(slpm); 1748 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 1749 } 1750 1751 return ret; 1752 } 1753 1754 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, 1755 struct pinctrl_gpio_range *range, 1756 unsigned offset) 1757 { 1758 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1759 struct nmk_gpio_chip *nmk_chip; 1760 struct gpio_chip *chip; 1761 unsigned bit; 1762 1763 if (!range) { 1764 dev_err(npct->dev, "invalid range\n"); 1765 return -EINVAL; 1766 } 1767 if (!range->gc) { 1768 dev_err(npct->dev, "missing GPIO chip in range\n"); 1769 return -EINVAL; 1770 } 1771 chip = range->gc; 1772 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 1773 1774 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 1775 1776 clk_enable(nmk_chip->clk); 1777 bit = offset % NMK_GPIO_PER_CHIP; 1778 /* There is no glitch when converting any pin to GPIO */ 1779 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1780 clk_disable(nmk_chip->clk); 1781 1782 return 0; 1783 } 1784 1785 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, 1786 struct pinctrl_gpio_range *range, 1787 unsigned offset) 1788 { 1789 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1790 1791 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 1792 /* Set the pin to some default state, GPIO is usually default */ 1793 } 1794 1795 static const struct pinmux_ops nmk_pinmux_ops = { 1796 .get_functions_count = nmk_pmx_get_funcs_cnt, 1797 .get_function_name = nmk_pmx_get_func_name, 1798 .get_function_groups = nmk_pmx_get_func_groups, 1799 .set_mux = nmk_pmx_set, 1800 .gpio_request_enable = nmk_gpio_request_enable, 1801 .gpio_disable_free = nmk_gpio_disable_free, 1802 }; 1803 1804 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 1805 unsigned long *config) 1806 { 1807 /* Not implemented */ 1808 return -EINVAL; 1809 } 1810 1811 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 1812 unsigned long *configs, unsigned num_configs) 1813 { 1814 static const char *pullnames[] = { 1815 [NMK_GPIO_PULL_NONE] = "none", 1816 [NMK_GPIO_PULL_UP] = "up", 1817 [NMK_GPIO_PULL_DOWN] = "down", 1818 [3] /* illegal */ = "??" 1819 }; 1820 static const char *slpmnames[] = { 1821 [NMK_GPIO_SLPM_INPUT] = "input/wakeup", 1822 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", 1823 }; 1824 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1825 struct nmk_gpio_chip *nmk_chip; 1826 struct pinctrl_gpio_range *range; 1827 struct gpio_chip *chip; 1828 unsigned bit; 1829 pin_cfg_t cfg; 1830 int pull, slpm, output, val, i; 1831 bool lowemi, gpiomode, sleep; 1832 1833 range = nmk_match_gpio_range(pctldev, pin); 1834 if (!range) { 1835 dev_err(npct->dev, "invalid pin offset %d\n", pin); 1836 return -EINVAL; 1837 } 1838 if (!range->gc) { 1839 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", 1840 pin); 1841 return -EINVAL; 1842 } 1843 chip = range->gc; 1844 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 1845 1846 for (i = 0; i < num_configs; i++) { 1847 /* 1848 * The pin config contains pin number and altfunction fields, 1849 * here we just ignore that part. It's being handled by the 1850 * framework and pinmux callback respectively. 1851 */ 1852 cfg = (pin_cfg_t) configs[i]; 1853 pull = PIN_PULL(cfg); 1854 slpm = PIN_SLPM(cfg); 1855 output = PIN_DIR(cfg); 1856 val = PIN_VAL(cfg); 1857 lowemi = PIN_LOWEMI(cfg); 1858 gpiomode = PIN_GPIOMODE(cfg); 1859 sleep = PIN_SLEEPMODE(cfg); 1860 1861 if (sleep) { 1862 int slpm_pull = PIN_SLPM_PULL(cfg); 1863 int slpm_output = PIN_SLPM_DIR(cfg); 1864 int slpm_val = PIN_SLPM_VAL(cfg); 1865 1866 /* All pins go into GPIO mode at sleep */ 1867 gpiomode = true; 1868 1869 /* 1870 * The SLPM_* values are normal values + 1 to allow zero 1871 * to mean "same as normal". 1872 */ 1873 if (slpm_pull) 1874 pull = slpm_pull - 1; 1875 if (slpm_output) 1876 output = slpm_output - 1; 1877 if (slpm_val) 1878 val = slpm_val - 1; 1879 1880 dev_dbg(nmk_chip->chip.dev, 1881 "pin %d: sleep pull %s, dir %s, val %s\n", 1882 pin, 1883 slpm_pull ? pullnames[pull] : "same", 1884 slpm_output ? (output ? "output" : "input") 1885 : "same", 1886 slpm_val ? (val ? "high" : "low") : "same"); 1887 } 1888 1889 dev_dbg(nmk_chip->chip.dev, 1890 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", 1891 pin, cfg, pullnames[pull], slpmnames[slpm], 1892 output ? "output " : "input", 1893 output ? (val ? "high" : "low") : "", 1894 lowemi ? "on" : "off"); 1895 1896 clk_enable(nmk_chip->clk); 1897 bit = pin % NMK_GPIO_PER_CHIP; 1898 if (gpiomode) 1899 /* No glitch when going to GPIO mode */ 1900 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1901 if (output) 1902 __nmk_gpio_make_output(nmk_chip, bit, val); 1903 else { 1904 __nmk_gpio_make_input(nmk_chip, bit); 1905 __nmk_gpio_set_pull(nmk_chip, bit, pull); 1906 } 1907 /* TODO: isn't this only applicable on output pins? */ 1908 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); 1909 1910 __nmk_gpio_set_slpm(nmk_chip, bit, slpm); 1911 clk_disable(nmk_chip->clk); 1912 } /* for each config */ 1913 1914 return 0; 1915 } 1916 1917 static const struct pinconf_ops nmk_pinconf_ops = { 1918 .pin_config_get = nmk_pin_config_get, 1919 .pin_config_set = nmk_pin_config_set, 1920 }; 1921 1922 static struct pinctrl_desc nmk_pinctrl_desc = { 1923 .name = "pinctrl-nomadik", 1924 .pctlops = &nmk_pinctrl_ops, 1925 .pmxops = &nmk_pinmux_ops, 1926 .confops = &nmk_pinconf_ops, 1927 .owner = THIS_MODULE, 1928 }; 1929 1930 static const struct of_device_id nmk_pinctrl_match[] = { 1931 { 1932 .compatible = "stericsson,stn8815-pinctrl", 1933 .data = (void *)PINCTRL_NMK_STN8815, 1934 }, 1935 { 1936 .compatible = "stericsson,db8500-pinctrl", 1937 .data = (void *)PINCTRL_NMK_DB8500, 1938 }, 1939 { 1940 .compatible = "stericsson,db8540-pinctrl", 1941 .data = (void *)PINCTRL_NMK_DB8540, 1942 }, 1943 {}, 1944 }; 1945 1946 #ifdef CONFIG_PM_SLEEP 1947 static int nmk_pinctrl_suspend(struct device *dev) 1948 { 1949 struct nmk_pinctrl *npct; 1950 1951 npct = dev_get_drvdata(dev); 1952 if (!npct) 1953 return -EINVAL; 1954 1955 return pinctrl_force_sleep(npct->pctl); 1956 } 1957 1958 static int nmk_pinctrl_resume(struct device *dev) 1959 { 1960 struct nmk_pinctrl *npct; 1961 1962 npct = dev_get_drvdata(dev); 1963 if (!npct) 1964 return -EINVAL; 1965 1966 return pinctrl_force_default(npct->pctl); 1967 } 1968 #endif 1969 1970 static int nmk_pinctrl_probe(struct platform_device *pdev) 1971 { 1972 const struct of_device_id *match; 1973 struct device_node *np = pdev->dev.of_node; 1974 struct device_node *prcm_np; 1975 struct nmk_pinctrl *npct; 1976 unsigned int version = 0; 1977 int i; 1978 1979 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); 1980 if (!npct) 1981 return -ENOMEM; 1982 1983 match = of_match_device(nmk_pinctrl_match, &pdev->dev); 1984 if (!match) 1985 return -ENODEV; 1986 version = (unsigned int) match->data; 1987 1988 /* Poke in other ASIC variants here */ 1989 if (version == PINCTRL_NMK_STN8815) 1990 nmk_pinctrl_stn8815_init(&npct->soc); 1991 if (version == PINCTRL_NMK_DB8500) 1992 nmk_pinctrl_db8500_init(&npct->soc); 1993 if (version == PINCTRL_NMK_DB8540) 1994 nmk_pinctrl_db8540_init(&npct->soc); 1995 1996 prcm_np = of_parse_phandle(np, "prcm", 0); 1997 if (prcm_np) 1998 npct->prcm_base = of_iomap(prcm_np, 0); 1999 if (!npct->prcm_base) { 2000 if (version == PINCTRL_NMK_STN8815) { 2001 dev_info(&pdev->dev, 2002 "No PRCM base, " 2003 "assuming no ALT-Cx control is available\n"); 2004 } else { 2005 dev_err(&pdev->dev, "missing PRCM base address\n"); 2006 return -EINVAL; 2007 } 2008 } 2009 2010 /* 2011 * We need all the GPIO drivers to probe FIRST, or we will not be able 2012 * to obtain references to the struct gpio_chip * for them, and we 2013 * need this to proceed. 2014 */ 2015 for (i = 0; i < npct->soc->gpio_num_ranges; i++) { 2016 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) { 2017 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); 2018 return -EPROBE_DEFER; 2019 } 2020 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip; 2021 } 2022 2023 nmk_pinctrl_desc.pins = npct->soc->pins; 2024 nmk_pinctrl_desc.npins = npct->soc->npins; 2025 npct->dev = &pdev->dev; 2026 2027 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); 2028 if (!npct->pctl) { 2029 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); 2030 return -EINVAL; 2031 } 2032 2033 /* We will handle a range of GPIO pins */ 2034 for (i = 0; i < npct->soc->gpio_num_ranges; i++) 2035 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); 2036 2037 platform_set_drvdata(pdev, npct); 2038 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); 2039 2040 return 0; 2041 } 2042 2043 static const struct of_device_id nmk_gpio_match[] = { 2044 { .compatible = "st,nomadik-gpio", }, 2045 {} 2046 }; 2047 2048 static struct platform_driver nmk_gpio_driver = { 2049 .driver = { 2050 .owner = THIS_MODULE, 2051 .name = "gpio", 2052 .of_match_table = nmk_gpio_match, 2053 }, 2054 .probe = nmk_gpio_probe, 2055 }; 2056 2057 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, 2058 nmk_pinctrl_suspend, 2059 nmk_pinctrl_resume); 2060 2061 static struct platform_driver nmk_pinctrl_driver = { 2062 .driver = { 2063 .owner = THIS_MODULE, 2064 .name = "pinctrl-nomadik", 2065 .of_match_table = nmk_pinctrl_match, 2066 .pm = &nmk_pinctrl_pm_ops, 2067 }, 2068 .probe = nmk_pinctrl_probe, 2069 }; 2070 2071 static int __init nmk_gpio_init(void) 2072 { 2073 int ret; 2074 2075 ret = platform_driver_register(&nmk_gpio_driver); 2076 if (ret) 2077 return ret; 2078 return platform_driver_register(&nmk_pinctrl_driver); 2079 } 2080 2081 core_initcall(nmk_gpio_init); 2082 2083 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); 2084 MODULE_DESCRIPTION("Nomadik GPIO Driver"); 2085 MODULE_LICENSE("GPL"); 2086