1 /* 2 * Marvell Armada XP pinctrl driver based on mvebu pinctrl core 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This file supports the three variants of Armada XP SoCs that are 14 * available: mv78230, mv78260 and mv78460. From a pin muxing 15 * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460 16 * both have 67 MPP pins (more GPIOs and address lines for the memory 17 * bus mainly). The only difference between the mv78260 and the 18 * mv78460 in terms of pin muxing is the addition of two functions on 19 * pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two 20 * cores, mv78460 has four cores). 21 */ 22 23 #include <linux/err.h> 24 #include <linux/init.h> 25 #include <linux/io.h> 26 #include <linux/module.h> 27 #include <linux/platform_device.h> 28 #include <linux/clk.h> 29 #include <linux/of.h> 30 #include <linux/of_device.h> 31 #include <linux/pinctrl/pinctrl.h> 32 #include <linux/bitops.h> 33 34 #include "pinctrl-mvebu.h" 35 36 static void __iomem *mpp_base; 37 38 static int armada_xp_mpp_ctrl_get(unsigned pid, unsigned long *config) 39 { 40 return default_mpp_ctrl_get(mpp_base, pid, config); 41 } 42 43 static int armada_xp_mpp_ctrl_set(unsigned pid, unsigned long config) 44 { 45 return default_mpp_ctrl_set(mpp_base, pid, config); 46 } 47 48 enum armada_xp_variant { 49 V_MV78230 = BIT(0), 50 V_MV78260 = BIT(1), 51 V_MV78460 = BIT(2), 52 V_MV78230_PLUS = (V_MV78230 | V_MV78260 | V_MV78460), 53 V_MV78260_PLUS = (V_MV78260 | V_MV78460), 54 }; 55 56 static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { 57 MPP_MODE(0, 58 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 59 MPP_VAR_FUNCTION(0x1, "ge0", "txclko", V_MV78230_PLUS), 60 MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)), 61 MPP_MODE(1, 62 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 63 MPP_VAR_FUNCTION(0x1, "ge0", "txd0", V_MV78230_PLUS), 64 MPP_VAR_FUNCTION(0x4, "lcd", "d1", V_MV78230_PLUS)), 65 MPP_MODE(2, 66 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 67 MPP_VAR_FUNCTION(0x1, "ge0", "txd1", V_MV78230_PLUS), 68 MPP_VAR_FUNCTION(0x4, "lcd", "d2", V_MV78230_PLUS)), 69 MPP_MODE(3, 70 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 71 MPP_VAR_FUNCTION(0x1, "ge0", "txd2", V_MV78230_PLUS), 72 MPP_VAR_FUNCTION(0x4, "lcd", "d3", V_MV78230_PLUS)), 73 MPP_MODE(4, 74 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 75 MPP_VAR_FUNCTION(0x1, "ge0", "txd3", V_MV78230_PLUS), 76 MPP_VAR_FUNCTION(0x4, "lcd", "d4", V_MV78230_PLUS)), 77 MPP_MODE(5, 78 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 79 MPP_VAR_FUNCTION(0x1, "ge0", "txctl", V_MV78230_PLUS), 80 MPP_VAR_FUNCTION(0x4, "lcd", "d5", V_MV78230_PLUS)), 81 MPP_MODE(6, 82 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 83 MPP_VAR_FUNCTION(0x1, "ge0", "rxd0", V_MV78230_PLUS), 84 MPP_VAR_FUNCTION(0x4, "lcd", "d6", V_MV78230_PLUS)), 85 MPP_MODE(7, 86 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 87 MPP_VAR_FUNCTION(0x1, "ge0", "rxd1", V_MV78230_PLUS), 88 MPP_VAR_FUNCTION(0x4, "lcd", "d7", V_MV78230_PLUS)), 89 MPP_MODE(8, 90 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 91 MPP_VAR_FUNCTION(0x1, "ge0", "rxd2", V_MV78230_PLUS), 92 MPP_VAR_FUNCTION(0x4, "lcd", "d8", V_MV78230_PLUS)), 93 MPP_MODE(9, 94 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 95 MPP_VAR_FUNCTION(0x1, "ge0", "rxd3", V_MV78230_PLUS), 96 MPP_VAR_FUNCTION(0x4, "lcd", "d9", V_MV78230_PLUS)), 97 MPP_MODE(10, 98 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 99 MPP_VAR_FUNCTION(0x1, "ge0", "rxctl", V_MV78230_PLUS), 100 MPP_VAR_FUNCTION(0x4, "lcd", "d10", V_MV78230_PLUS)), 101 MPP_MODE(11, 102 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 103 MPP_VAR_FUNCTION(0x1, "ge0", "rxclk", V_MV78230_PLUS), 104 MPP_VAR_FUNCTION(0x4, "lcd", "d11", V_MV78230_PLUS)), 105 MPP_MODE(12, 106 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 107 MPP_VAR_FUNCTION(0x1, "ge0", "txd4", V_MV78230_PLUS), 108 MPP_VAR_FUNCTION(0x2, "ge1", "clkout", V_MV78230_PLUS), 109 MPP_VAR_FUNCTION(0x4, "lcd", "d12", V_MV78230_PLUS)), 110 MPP_MODE(13, 111 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 112 MPP_VAR_FUNCTION(0x1, "ge0", "txd5", V_MV78230_PLUS), 113 MPP_VAR_FUNCTION(0x2, "ge1", "txd0", V_MV78230_PLUS), 114 MPP_VAR_FUNCTION(0x4, "lcd", "d13", V_MV78230_PLUS)), 115 MPP_MODE(14, 116 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 117 MPP_VAR_FUNCTION(0x1, "ge0", "txd6", V_MV78230_PLUS), 118 MPP_VAR_FUNCTION(0x2, "ge1", "txd1", V_MV78230_PLUS), 119 MPP_VAR_FUNCTION(0x4, "lcd", "d14", V_MV78230_PLUS)), 120 MPP_MODE(15, 121 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 122 MPP_VAR_FUNCTION(0x1, "ge0", "txd7", V_MV78230_PLUS), 123 MPP_VAR_FUNCTION(0x2, "ge1", "txd2", V_MV78230_PLUS), 124 MPP_VAR_FUNCTION(0x4, "lcd", "d15", V_MV78230_PLUS)), 125 MPP_MODE(16, 126 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 127 MPP_VAR_FUNCTION(0x1, "ge0", "txclk", V_MV78230_PLUS), 128 MPP_VAR_FUNCTION(0x2, "ge1", "txd3", V_MV78230_PLUS), 129 MPP_VAR_FUNCTION(0x4, "lcd", "d16", V_MV78230_PLUS)), 130 MPP_MODE(17, 131 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 132 MPP_VAR_FUNCTION(0x1, "ge0", "col", V_MV78230_PLUS), 133 MPP_VAR_FUNCTION(0x2, "ge1", "txctl", V_MV78230_PLUS), 134 MPP_VAR_FUNCTION(0x4, "lcd", "d17", V_MV78230_PLUS)), 135 MPP_MODE(18, 136 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 137 MPP_VAR_FUNCTION(0x1, "ge0", "rxerr", V_MV78230_PLUS), 138 MPP_VAR_FUNCTION(0x2, "ge1", "rxd0", V_MV78230_PLUS), 139 MPP_VAR_FUNCTION(0x3, "ptp", "trig", V_MV78230_PLUS), 140 MPP_VAR_FUNCTION(0x4, "lcd", "d18", V_MV78230_PLUS)), 141 MPP_MODE(19, 142 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 143 MPP_VAR_FUNCTION(0x1, "ge0", "crs", V_MV78230_PLUS), 144 MPP_VAR_FUNCTION(0x2, "ge1", "rxd1", V_MV78230_PLUS), 145 MPP_VAR_FUNCTION(0x3, "ptp", "evreq", V_MV78230_PLUS), 146 MPP_VAR_FUNCTION(0x4, "lcd", "d19", V_MV78230_PLUS)), 147 MPP_MODE(20, 148 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 149 MPP_VAR_FUNCTION(0x1, "ge0", "rxd4", V_MV78230_PLUS), 150 MPP_VAR_FUNCTION(0x2, "ge1", "rxd2", V_MV78230_PLUS), 151 MPP_VAR_FUNCTION(0x3, "ptp", "clk", V_MV78230_PLUS), 152 MPP_VAR_FUNCTION(0x4, "lcd", "d20", V_MV78230_PLUS)), 153 MPP_MODE(21, 154 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 155 MPP_VAR_FUNCTION(0x1, "ge0", "rxd5", V_MV78230_PLUS), 156 MPP_VAR_FUNCTION(0x2, "ge1", "rxd3", V_MV78230_PLUS), 157 MPP_VAR_FUNCTION(0x3, "mem", "bat", V_MV78230_PLUS), 158 MPP_VAR_FUNCTION(0x4, "lcd", "d21", V_MV78230_PLUS)), 159 MPP_MODE(22, 160 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 161 MPP_VAR_FUNCTION(0x1, "ge0", "rxd6", V_MV78230_PLUS), 162 MPP_VAR_FUNCTION(0x2, "ge1", "rxctl", V_MV78230_PLUS), 163 MPP_VAR_FUNCTION(0x3, "sata0", "prsnt", V_MV78230_PLUS), 164 MPP_VAR_FUNCTION(0x4, "lcd", "d22", V_MV78230_PLUS)), 165 MPP_MODE(23, 166 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 167 MPP_VAR_FUNCTION(0x1, "ge0", "rxd7", V_MV78230_PLUS), 168 MPP_VAR_FUNCTION(0x2, "ge1", "rxclk", V_MV78230_PLUS), 169 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS), 170 MPP_VAR_FUNCTION(0x4, "lcd", "d23", V_MV78230_PLUS)), 171 MPP_MODE(24, 172 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 173 MPP_VAR_FUNCTION(0x1, "sata1", "prsnt", V_MV78230_PLUS), 174 MPP_VAR_FUNCTION(0x2, "nf", "bootcs-re", V_MV78230_PLUS), 175 MPP_VAR_FUNCTION(0x3, "tdm", "rst", V_MV78230_PLUS), 176 MPP_VAR_FUNCTION(0x4, "lcd", "hsync", V_MV78230_PLUS)), 177 MPP_MODE(25, 178 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 179 MPP_VAR_FUNCTION(0x1, "sata0", "prsnt", V_MV78230_PLUS), 180 MPP_VAR_FUNCTION(0x2, "nf", "bootcs-we", V_MV78230_PLUS), 181 MPP_VAR_FUNCTION(0x3, "tdm", "pclk", V_MV78230_PLUS), 182 MPP_VAR_FUNCTION(0x4, "lcd", "vsync", V_MV78230_PLUS)), 183 MPP_MODE(26, 184 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 185 MPP_VAR_FUNCTION(0x3, "tdm", "fsync", V_MV78230_PLUS), 186 MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS), 187 MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)), 188 MPP_MODE(27, 189 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 190 MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS), 191 MPP_VAR_FUNCTION(0x3, "tdm", "dtx", V_MV78230_PLUS), 192 MPP_VAR_FUNCTION(0x4, "lcd", "e", V_MV78230_PLUS)), 193 MPP_MODE(28, 194 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 195 MPP_VAR_FUNCTION(0x1, "ptp", "evreq", V_MV78230_PLUS), 196 MPP_VAR_FUNCTION(0x3, "tdm", "drx", V_MV78230_PLUS), 197 MPP_VAR_FUNCTION(0x4, "lcd", "pwm", V_MV78230_PLUS)), 198 MPP_MODE(29, 199 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 200 MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS), 201 MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS), 202 MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS), 203 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), 204 MPP_MODE(30, 205 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 206 MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS), 207 MPP_VAR_FUNCTION(0x3, "tdm", "int1", V_MV78230_PLUS)), 208 MPP_MODE(31, 209 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 210 MPP_VAR_FUNCTION(0x1, "sd0", "cmd", V_MV78230_PLUS), 211 MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS), 212 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), 213 MPP_MODE(32, 214 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 215 MPP_VAR_FUNCTION(0x1, "sd0", "d0", V_MV78230_PLUS), 216 MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS), 217 MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)), 218 MPP_MODE(33, 219 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 220 MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS), 221 MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS), 222 MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS)), 223 MPP_MODE(34, 224 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 225 MPP_VAR_FUNCTION(0x1, "sd0", "d2", V_MV78230_PLUS), 226 MPP_VAR_FUNCTION(0x2, "sata0", "prsnt", V_MV78230_PLUS), 227 MPP_VAR_FUNCTION(0x3, "tdm", "int5", V_MV78230_PLUS)), 228 MPP_MODE(35, 229 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 230 MPP_VAR_FUNCTION(0x1, "sd0", "d3", V_MV78230_PLUS), 231 MPP_VAR_FUNCTION(0x2, "sata1", "prsnt", V_MV78230_PLUS), 232 MPP_VAR_FUNCTION(0x3, "tdm", "int6", V_MV78230_PLUS)), 233 MPP_MODE(36, 234 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 235 MPP_VAR_FUNCTION(0x1, "spi", "mosi", V_MV78230_PLUS)), 236 MPP_MODE(37, 237 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 238 MPP_VAR_FUNCTION(0x1, "spi", "miso", V_MV78230_PLUS)), 239 MPP_MODE(38, 240 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 241 MPP_VAR_FUNCTION(0x1, "spi", "sck", V_MV78230_PLUS)), 242 MPP_MODE(39, 243 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 244 MPP_VAR_FUNCTION(0x1, "spi", "cs0", V_MV78230_PLUS)), 245 MPP_MODE(40, 246 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 247 MPP_VAR_FUNCTION(0x1, "spi", "cs1", V_MV78230_PLUS), 248 MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS), 249 MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd", V_MV78230_PLUS), 250 MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS), 251 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)), 252 MPP_MODE(41, 253 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 254 MPP_VAR_FUNCTION(0x1, "spi", "cs2", V_MV78230_PLUS), 255 MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS), 256 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS), 257 MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS), 258 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS)), 259 MPP_MODE(42, 260 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 261 MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS), 262 MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS), 263 MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS), 264 MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS), 265 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), 266 MPP_MODE(43, 267 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 268 MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), 269 MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS), 270 MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS), 271 MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS), 272 MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd", V_MV78460)), 273 MPP_MODE(44, 274 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 275 MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), 276 MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS), 277 MPP_VAR_FUNCTION(0x3, "spi", "cs4", V_MV78230_PLUS), 278 MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS), 279 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)), 280 MPP_MODE(45, 281 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 282 MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS), 283 MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS), 284 MPP_VAR_FUNCTION(0x3, "spi", "cs5", V_MV78230_PLUS), 285 MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS)), 286 MPP_MODE(46, 287 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 288 MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS), 289 MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS), 290 MPP_VAR_FUNCTION(0x3, "spi", "cs6", V_MV78230_PLUS), 291 MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS)), 292 MPP_MODE(47, 293 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 294 MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS), 295 MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS), 296 MPP_VAR_FUNCTION(0x3, "spi", "cs7", V_MV78230_PLUS), 297 MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS), 298 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)), 299 MPP_MODE(48, 300 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), 301 MPP_VAR_FUNCTION(0x1, "tclk", NULL, V_MV78230_PLUS), 302 MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)), 303 MPP_MODE(49, 304 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 305 MPP_VAR_FUNCTION(0x1, "dev", "we3", V_MV78260_PLUS)), 306 MPP_MODE(50, 307 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 308 MPP_VAR_FUNCTION(0x1, "dev", "we2", V_MV78260_PLUS)), 309 MPP_MODE(51, 310 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 311 MPP_VAR_FUNCTION(0x1, "dev", "ad16", V_MV78260_PLUS)), 312 MPP_MODE(52, 313 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 314 MPP_VAR_FUNCTION(0x1, "dev", "ad17", V_MV78260_PLUS)), 315 MPP_MODE(53, 316 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 317 MPP_VAR_FUNCTION(0x1, "dev", "ad18", V_MV78260_PLUS)), 318 MPP_MODE(54, 319 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 320 MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)), 321 MPP_MODE(55, 322 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 323 MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS), 324 MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd", V_MV78260_PLUS)), 325 MPP_MODE(56, 326 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 327 MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS), 328 MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd", V_MV78260_PLUS)), 329 MPP_MODE(57, 330 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 331 MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS), 332 MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd", V_MV78460)), 333 MPP_MODE(58, 334 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 335 MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)), 336 MPP_MODE(59, 337 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 338 MPP_VAR_FUNCTION(0x1, "dev", "ad24", V_MV78260_PLUS)), 339 MPP_MODE(60, 340 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 341 MPP_VAR_FUNCTION(0x1, "dev", "ad25", V_MV78260_PLUS)), 342 MPP_MODE(61, 343 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 344 MPP_VAR_FUNCTION(0x1, "dev", "ad26", V_MV78260_PLUS)), 345 MPP_MODE(62, 346 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 347 MPP_VAR_FUNCTION(0x1, "dev", "ad27", V_MV78260_PLUS)), 348 MPP_MODE(63, 349 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 350 MPP_VAR_FUNCTION(0x1, "dev", "ad28", V_MV78260_PLUS)), 351 MPP_MODE(64, 352 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 353 MPP_VAR_FUNCTION(0x1, "dev", "ad29", V_MV78260_PLUS)), 354 MPP_MODE(65, 355 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 356 MPP_VAR_FUNCTION(0x1, "dev", "ad30", V_MV78260_PLUS)), 357 MPP_MODE(66, 358 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), 359 MPP_VAR_FUNCTION(0x1, "dev", "ad31", V_MV78260_PLUS)), 360 }; 361 362 static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info; 363 364 static struct of_device_id armada_xp_pinctrl_of_match[] = { 365 { 366 .compatible = "marvell,mv78230-pinctrl", 367 .data = (void *) V_MV78230, 368 }, 369 { 370 .compatible = "marvell,mv78260-pinctrl", 371 .data = (void *) V_MV78260, 372 }, 373 { 374 .compatible = "marvell,mv78460-pinctrl", 375 .data = (void *) V_MV78460, 376 }, 377 { }, 378 }; 379 380 static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = { 381 MPP_FUNC_CTRL(0, 48, NULL, armada_xp_mpp_ctrl), 382 }; 383 384 static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = { 385 MPP_GPIO_RANGE(0, 0, 0, 32), 386 MPP_GPIO_RANGE(1, 32, 32, 17), 387 }; 388 389 static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = { 390 MPP_FUNC_CTRL(0, 66, NULL, armada_xp_mpp_ctrl), 391 }; 392 393 static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = { 394 MPP_GPIO_RANGE(0, 0, 0, 32), 395 MPP_GPIO_RANGE(1, 32, 32, 32), 396 MPP_GPIO_RANGE(2, 64, 64, 3), 397 }; 398 399 static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = { 400 MPP_FUNC_CTRL(0, 66, NULL, armada_xp_mpp_ctrl), 401 }; 402 403 static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = { 404 MPP_GPIO_RANGE(0, 0, 0, 32), 405 MPP_GPIO_RANGE(1, 32, 32, 32), 406 MPP_GPIO_RANGE(2, 64, 64, 3), 407 }; 408 409 static int armada_xp_pinctrl_probe(struct platform_device *pdev) 410 { 411 struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info; 412 const struct of_device_id *match = 413 of_match_device(armada_xp_pinctrl_of_match, &pdev->dev); 414 struct resource *res; 415 416 if (!match) 417 return -ENODEV; 418 419 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 420 mpp_base = devm_ioremap_resource(&pdev->dev, res); 421 if (IS_ERR(mpp_base)) 422 return PTR_ERR(mpp_base); 423 424 soc->variant = (unsigned) match->data & 0xff; 425 426 switch (soc->variant) { 427 case V_MV78230: 428 soc->controls = mv78230_mpp_controls; 429 soc->ncontrols = ARRAY_SIZE(mv78230_mpp_controls); 430 soc->modes = armada_xp_mpp_modes; 431 /* We don't necessarily want the full list of the 432 * armada_xp_mpp_modes, but only the first 'n' ones 433 * that are available on this SoC */ 434 soc->nmodes = mv78230_mpp_controls[0].npins; 435 soc->gpioranges = mv78230_mpp_gpio_ranges; 436 soc->ngpioranges = ARRAY_SIZE(mv78230_mpp_gpio_ranges); 437 break; 438 case V_MV78260: 439 soc->controls = mv78260_mpp_controls; 440 soc->ncontrols = ARRAY_SIZE(mv78260_mpp_controls); 441 soc->modes = armada_xp_mpp_modes; 442 /* We don't necessarily want the full list of the 443 * armada_xp_mpp_modes, but only the first 'n' ones 444 * that are available on this SoC */ 445 soc->nmodes = mv78260_mpp_controls[0].npins; 446 soc->gpioranges = mv78260_mpp_gpio_ranges; 447 soc->ngpioranges = ARRAY_SIZE(mv78260_mpp_gpio_ranges); 448 break; 449 case V_MV78460: 450 soc->controls = mv78460_mpp_controls; 451 soc->ncontrols = ARRAY_SIZE(mv78460_mpp_controls); 452 soc->modes = armada_xp_mpp_modes; 453 /* We don't necessarily want the full list of the 454 * armada_xp_mpp_modes, but only the first 'n' ones 455 * that are available on this SoC */ 456 soc->nmodes = mv78460_mpp_controls[0].npins; 457 soc->gpioranges = mv78460_mpp_gpio_ranges; 458 soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges); 459 break; 460 } 461 462 pdev->dev.platform_data = soc; 463 464 return mvebu_pinctrl_probe(pdev); 465 } 466 467 static int armada_xp_pinctrl_remove(struct platform_device *pdev) 468 { 469 return mvebu_pinctrl_remove(pdev); 470 } 471 472 static struct platform_driver armada_xp_pinctrl_driver = { 473 .driver = { 474 .name = "armada-xp-pinctrl", 475 .of_match_table = armada_xp_pinctrl_of_match, 476 }, 477 .probe = armada_xp_pinctrl_probe, 478 .remove = armada_xp_pinctrl_remove, 479 }; 480 481 module_platform_driver(armada_xp_pinctrl_driver); 482 483 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 484 MODULE_DESCRIPTION("Marvell Armada XP pinctrl driver"); 485 MODULE_LICENSE("GPL v2"); 486