1 /* 2 * Marvell 37xx SoC pinctrl driver 3 * 4 * Copyright (C) 2017 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2 or later. This program is licensed "as is" 10 * without any warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/gpio/driver.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/platform_device.h> 24 #include <linux/property.h> 25 #include <linux/regmap.h> 26 #include <linux/slab.h> 27 #include <linux/string_helpers.h> 28 29 #include "../pinctrl-utils.h" 30 31 #define OUTPUT_EN 0x0 32 #define INPUT_VAL 0x10 33 #define OUTPUT_VAL 0x18 34 #define OUTPUT_CTL 0x20 35 #define SELECTION 0x30 36 37 #define IRQ_EN 0x0 38 #define IRQ_POL 0x08 39 #define IRQ_STATUS 0x10 40 #define IRQ_WKUP 0x18 41 42 #define NB_FUNCS 3 43 #define GPIO_PER_REG 32 44 45 /** 46 * struct armada_37xx_pin_group: represents group of pins of a pinmux function. 47 * The pins of a pinmux groups are composed of one or two groups of contiguous 48 * pins. 49 * @name: Name of the pin group, used to lookup the group. 50 * @start_pin: Index of the first pin of the main range of pins belonging to 51 * the group 52 * @npins: Number of pins included in the first range 53 * @reg_mask: Bit mask matching the group in the selection register 54 * @val: Value to write to the registers for a given function 55 * @extra_pin: Index of the first pin of the optional second range of pins 56 * belonging to the group 57 * @extra_npins:Number of pins included in the second optional range 58 * @funcs: A list of pinmux functions that can be selected for this group. 59 * @pins: List of the pins included in the group 60 */ 61 struct armada_37xx_pin_group { 62 const char *name; 63 unsigned int start_pin; 64 unsigned int npins; 65 u32 reg_mask; 66 u32 val[NB_FUNCS]; 67 unsigned int extra_pin; 68 unsigned int extra_npins; 69 const char *funcs[NB_FUNCS]; 70 unsigned int *pins; 71 }; 72 73 struct armada_37xx_pin_data { 74 u8 nr_pins; 75 char *name; 76 struct armada_37xx_pin_group *groups; 77 int ngroups; 78 }; 79 80 struct armada_37xx_pmx_func { 81 const char *name; 82 const char **groups; 83 unsigned int ngroups; 84 }; 85 86 struct armada_37xx_pm_state { 87 u32 out_en_l; 88 u32 out_en_h; 89 u32 out_val_l; 90 u32 out_val_h; 91 u32 irq_en_l; 92 u32 irq_en_h; 93 u32 irq_pol_l; 94 u32 irq_pol_h; 95 u32 selection; 96 }; 97 98 struct armada_37xx_pinctrl { 99 struct regmap *regmap; 100 void __iomem *base; 101 const struct armada_37xx_pin_data *data; 102 struct device *dev; 103 struct gpio_chip gpio_chip; 104 struct irq_chip irq_chip; 105 raw_spinlock_t irq_lock; 106 struct pinctrl_desc pctl; 107 struct pinctrl_dev *pctl_dev; 108 struct armada_37xx_pin_group *groups; 109 unsigned int ngroups; 110 struct armada_37xx_pmx_func *funcs; 111 unsigned int nfuncs; 112 struct armada_37xx_pm_state pm; 113 }; 114 115 #define PIN_GRP_GPIO_0(_name, _start, _nr) \ 116 { \ 117 .name = _name, \ 118 .start_pin = _start, \ 119 .npins = _nr, \ 120 .reg_mask = 0, \ 121 .val = {0}, \ 122 .funcs = {"gpio"} \ 123 } 124 125 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \ 126 { \ 127 .name = _name, \ 128 .start_pin = _start, \ 129 .npins = _nr, \ 130 .reg_mask = _mask, \ 131 .val = {0, _mask}, \ 132 .funcs = {_func1, "gpio"} \ 133 } 134 135 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \ 136 { \ 137 .name = _name, \ 138 .start_pin = _start, \ 139 .npins = _nr, \ 140 .reg_mask = _mask, \ 141 .val = {_val1, _val2}, \ 142 .funcs = {_func1, "gpio"} \ 143 } 144 145 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \ 146 { \ 147 .name = _name, \ 148 .start_pin = _start, \ 149 .npins = _nr, \ 150 .reg_mask = _mask, \ 151 .val = {_v1, _v2, _v3}, \ 152 .funcs = {_f1, _f2, "gpio"} \ 153 } 154 155 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \ 156 _f1, _f2) \ 157 { \ 158 .name = _name, \ 159 .start_pin = _start, \ 160 .npins = _nr, \ 161 .reg_mask = _mask, \ 162 .val = {_v1, _v2}, \ 163 .extra_pin = _start2, \ 164 .extra_npins = _nr2, \ 165 .funcs = {_f1, _f2} \ 166 } 167 168 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { 169 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"), 170 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"), 171 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"), 172 PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3), 173 "pwm", "led"), 174 PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4), 175 "pwm", "led"), 176 PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5), 177 "pwm", "led"), 178 PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6), 179 "pwm", "led"), 180 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"), 181 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"), 182 PIN_GRP_GPIO_0("gpio1_5", 5, 1), 183 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"), 184 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"), 185 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"), 186 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"), 187 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"), 188 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"), 189 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"), 190 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"), 191 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), 192 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), 193 18, 2, "gpio", "uart"), 194 }; 195 196 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { 197 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"), 198 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"), 199 PIN_GRP_GPIO_0("gpio2_2", 2, 1), 200 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), 201 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"), 202 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"), 203 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ 204 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), 205 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), 206 PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"), 207 PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12), 208 "ptp", "mii"), 209 PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13), 210 "ptp", "mii"), 211 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), 212 "mii", "mii_err"), 213 }; 214 215 static const struct armada_37xx_pin_data armada_37xx_pin_nb = { 216 .nr_pins = 36, 217 .name = "GPIO1", 218 .groups = armada_37xx_nb_groups, 219 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups), 220 }; 221 222 static const struct armada_37xx_pin_data armada_37xx_pin_sb = { 223 .nr_pins = 30, 224 .name = "GPIO2", 225 .groups = armada_37xx_sb_groups, 226 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups), 227 }; 228 229 static inline void armada_37xx_update_reg(unsigned int *reg, 230 unsigned int *offset) 231 { 232 /* We never have more than 2 registers */ 233 if (*offset >= GPIO_PER_REG) { 234 *offset -= GPIO_PER_REG; 235 *reg += sizeof(u32); 236 } 237 } 238 239 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin( 240 struct armada_37xx_pinctrl *info, int pin, int *grp) 241 { 242 while (*grp < info->ngroups) { 243 struct armada_37xx_pin_group *group = &info->groups[*grp]; 244 int j; 245 246 *grp = *grp + 1; 247 for (j = 0; j < (group->npins + group->extra_npins); j++) 248 if (group->pins[j] == pin) 249 return group; 250 } 251 return NULL; 252 } 253 254 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev, 255 unsigned int selector, unsigned long *config) 256 { 257 return -ENOTSUPP; 258 } 259 260 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev, 261 unsigned int selector, unsigned long *configs, 262 unsigned int num_configs) 263 { 264 return -ENOTSUPP; 265 } 266 267 static const struct pinconf_ops armada_37xx_pinconf_ops = { 268 .is_generic = true, 269 .pin_config_group_get = armada_37xx_pin_config_group_get, 270 .pin_config_group_set = armada_37xx_pin_config_group_set, 271 }; 272 273 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev) 274 { 275 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 276 277 return info->ngroups; 278 } 279 280 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev, 281 unsigned int group) 282 { 283 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 284 285 return info->groups[group].name; 286 } 287 288 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev, 289 unsigned int selector, 290 const unsigned int **pins, 291 unsigned int *npins) 292 { 293 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 294 295 if (selector >= info->ngroups) 296 return -EINVAL; 297 298 *pins = info->groups[selector].pins; 299 *npins = info->groups[selector].npins + 300 info->groups[selector].extra_npins; 301 302 return 0; 303 } 304 305 static const struct pinctrl_ops armada_37xx_pctrl_ops = { 306 .get_groups_count = armada_37xx_get_groups_count, 307 .get_group_name = armada_37xx_get_group_name, 308 .get_group_pins = armada_37xx_get_group_pins, 309 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 310 .dt_free_map = pinctrl_utils_free_map, 311 }; 312 313 /* 314 * Pinmux_ops handling 315 */ 316 317 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 318 { 319 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 320 321 return info->nfuncs; 322 } 323 324 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev, 325 unsigned int selector) 326 { 327 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 328 329 return info->funcs[selector].name; 330 } 331 332 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev, 333 unsigned int selector, 334 const char * const **groups, 335 unsigned int * const num_groups) 336 { 337 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 338 339 *groups = info->funcs[selector].groups; 340 *num_groups = info->funcs[selector].ngroups; 341 342 return 0; 343 } 344 345 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev, 346 const char *name, 347 struct armada_37xx_pin_group *grp) 348 { 349 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 350 struct device *dev = info->dev; 351 unsigned int reg = SELECTION; 352 unsigned int mask = grp->reg_mask; 353 int func, val; 354 355 dev_dbg(dev, "enable function %s group %s\n", name, grp->name); 356 357 func = match_string(grp->funcs, NB_FUNCS, name); 358 if (func < 0) 359 return -ENOTSUPP; 360 361 val = grp->val[func]; 362 363 regmap_update_bits(info->regmap, reg, mask, val); 364 365 return 0; 366 } 367 368 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev, 369 unsigned int selector, 370 unsigned int group) 371 { 372 373 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 374 struct armada_37xx_pin_group *grp = &info->groups[group]; 375 const char *name = info->funcs[selector].name; 376 377 return armada_37xx_pmx_set_by_name(pctldev, name, grp); 378 } 379 380 static inline void armada_37xx_irq_update_reg(unsigned int *reg, 381 struct irq_data *d) 382 { 383 int offset = irqd_to_hwirq(d); 384 385 armada_37xx_update_reg(reg, &offset); 386 } 387 388 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip, 389 unsigned int offset) 390 { 391 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 392 unsigned int reg = OUTPUT_EN; 393 unsigned int mask; 394 395 armada_37xx_update_reg(®, &offset); 396 mask = BIT(offset); 397 398 return regmap_update_bits(info->regmap, reg, mask, 0); 399 } 400 401 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip, 402 unsigned int offset) 403 { 404 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 405 unsigned int reg = OUTPUT_EN; 406 unsigned int val, mask; 407 408 armada_37xx_update_reg(®, &offset); 409 mask = BIT(offset); 410 regmap_read(info->regmap, reg, &val); 411 412 if (val & mask) 413 return GPIO_LINE_DIRECTION_OUT; 414 415 return GPIO_LINE_DIRECTION_IN; 416 } 417 418 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip, 419 unsigned int offset, int value) 420 { 421 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 422 unsigned int reg = OUTPUT_EN; 423 unsigned int mask, val, ret; 424 425 armada_37xx_update_reg(®, &offset); 426 mask = BIT(offset); 427 428 ret = regmap_update_bits(info->regmap, reg, mask, mask); 429 430 if (ret) 431 return ret; 432 433 reg = OUTPUT_VAL; 434 val = value ? mask : 0; 435 regmap_update_bits(info->regmap, reg, mask, val); 436 437 return 0; 438 } 439 440 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 441 { 442 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 443 unsigned int reg = INPUT_VAL; 444 unsigned int val, mask; 445 446 armada_37xx_update_reg(®, &offset); 447 mask = BIT(offset); 448 449 regmap_read(info->regmap, reg, &val); 450 451 return (val & mask) != 0; 452 } 453 454 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 455 int value) 456 { 457 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 458 unsigned int reg = OUTPUT_VAL; 459 unsigned int mask, val; 460 461 armada_37xx_update_reg(®, &offset); 462 mask = BIT(offset); 463 val = value ? mask : 0; 464 465 regmap_update_bits(info->regmap, reg, mask, val); 466 } 467 468 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 469 struct pinctrl_gpio_range *range, 470 unsigned int offset, bool input) 471 { 472 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 473 struct gpio_chip *chip = range->gc; 474 475 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 476 offset, range->name, offset, input ? "input" : "output"); 477 478 if (input) 479 armada_37xx_gpio_direction_input(chip, offset); 480 else 481 armada_37xx_gpio_direction_output(chip, offset, 0); 482 483 return 0; 484 } 485 486 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev, 487 struct pinctrl_gpio_range *range, 488 unsigned int offset) 489 { 490 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 491 struct armada_37xx_pin_group *group; 492 int grp = 0; 493 int ret; 494 495 dev_dbg(info->dev, "requesting gpio %d\n", offset); 496 497 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp))) { 498 ret = armada_37xx_pmx_set_by_name(pctldev, "gpio", group); 499 if (ret) 500 return ret; 501 } 502 503 return 0; 504 } 505 506 static const struct pinmux_ops armada_37xx_pmx_ops = { 507 .get_functions_count = armada_37xx_pmx_get_funcs_count, 508 .get_function_name = armada_37xx_pmx_get_func_name, 509 .get_function_groups = armada_37xx_pmx_get_groups, 510 .set_mux = armada_37xx_pmx_set, 511 .gpio_request_enable = armada_37xx_gpio_request_enable, 512 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction, 513 }; 514 515 static const struct gpio_chip armada_37xx_gpiolib_chip = { 516 .request = gpiochip_generic_request, 517 .free = gpiochip_generic_free, 518 .set = armada_37xx_gpio_set, 519 .get = armada_37xx_gpio_get, 520 .get_direction = armada_37xx_gpio_get_direction, 521 .direction_input = armada_37xx_gpio_direction_input, 522 .direction_output = armada_37xx_gpio_direction_output, 523 .owner = THIS_MODULE, 524 }; 525 526 static void armada_37xx_irq_ack(struct irq_data *d) 527 { 528 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 529 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 530 u32 reg = IRQ_STATUS; 531 unsigned long flags; 532 533 armada_37xx_irq_update_reg(®, d); 534 raw_spin_lock_irqsave(&info->irq_lock, flags); 535 writel(d->mask, info->base + reg); 536 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 537 } 538 539 static void armada_37xx_irq_mask(struct irq_data *d) 540 { 541 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 542 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 543 u32 val, reg = IRQ_EN; 544 unsigned long flags; 545 546 armada_37xx_irq_update_reg(®, d); 547 raw_spin_lock_irqsave(&info->irq_lock, flags); 548 val = readl(info->base + reg); 549 writel(val & ~d->mask, info->base + reg); 550 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 551 } 552 553 static void armada_37xx_irq_unmask(struct irq_data *d) 554 { 555 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 556 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 557 u32 val, reg = IRQ_EN; 558 unsigned long flags; 559 560 armada_37xx_irq_update_reg(®, d); 561 raw_spin_lock_irqsave(&info->irq_lock, flags); 562 val = readl(info->base + reg); 563 writel(val | d->mask, info->base + reg); 564 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 565 } 566 567 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on) 568 { 569 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 570 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 571 u32 val, reg = IRQ_WKUP; 572 unsigned long flags; 573 574 armada_37xx_irq_update_reg(®, d); 575 raw_spin_lock_irqsave(&info->irq_lock, flags); 576 val = readl(info->base + reg); 577 if (on) 578 val |= (BIT(d->hwirq % GPIO_PER_REG)); 579 else 580 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); 581 writel(val, info->base + reg); 582 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 583 584 return 0; 585 } 586 587 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type) 588 { 589 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 590 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 591 u32 val, reg = IRQ_POL; 592 unsigned long flags; 593 594 raw_spin_lock_irqsave(&info->irq_lock, flags); 595 armada_37xx_irq_update_reg(®, d); 596 val = readl(info->base + reg); 597 switch (type) { 598 case IRQ_TYPE_EDGE_RISING: 599 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); 600 break; 601 case IRQ_TYPE_EDGE_FALLING: 602 val |= (BIT(d->hwirq % GPIO_PER_REG)); 603 break; 604 case IRQ_TYPE_EDGE_BOTH: { 605 u32 in_val, in_reg = INPUT_VAL; 606 607 armada_37xx_irq_update_reg(&in_reg, d); 608 regmap_read(info->regmap, in_reg, &in_val); 609 610 /* Set initial polarity based on current input level. */ 611 if (in_val & BIT(d->hwirq % GPIO_PER_REG)) 612 val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */ 613 else 614 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */ 615 break; 616 } 617 default: 618 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 619 return -EINVAL; 620 } 621 writel(val, info->base + reg); 622 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 623 624 return 0; 625 } 626 627 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info, 628 u32 pin_idx) 629 { 630 u32 reg_idx = pin_idx / GPIO_PER_REG; 631 u32 bit_num = pin_idx % GPIO_PER_REG; 632 u32 p, l, ret; 633 unsigned long flags; 634 635 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l); 636 637 raw_spin_lock_irqsave(&info->irq_lock, flags); 638 p = readl(info->base + IRQ_POL + 4 * reg_idx); 639 if ((p ^ l) & (1 << bit_num)) { 640 /* 641 * For the gpios which are used for both-edge irqs, when their 642 * interrupts happen, their input levels are changed, 643 * yet their interrupt polarities are kept in old values, we 644 * should synchronize their interrupt polarities; for example, 645 * at first a gpio's input level is low and its interrupt 646 * polarity control is "Detect rising edge", then the gpio has 647 * a interrupt , its level turns to high, we should change its 648 * polarity control to "Detect falling edge" correspondingly. 649 */ 650 p ^= 1 << bit_num; 651 writel(p, info->base + IRQ_POL + 4 * reg_idx); 652 ret = 0; 653 } else { 654 /* Spurious irq */ 655 ret = -1; 656 } 657 658 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 659 return ret; 660 } 661 662 static void armada_37xx_irq_handler(struct irq_desc *desc) 663 { 664 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 665 struct irq_chip *chip = irq_desc_get_chip(desc); 666 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc); 667 struct irq_domain *d = gc->irq.domain; 668 int i; 669 670 chained_irq_enter(chip, desc); 671 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) { 672 u32 status; 673 unsigned long flags; 674 675 raw_spin_lock_irqsave(&info->irq_lock, flags); 676 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i); 677 /* Manage only the interrupt that was enabled */ 678 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 679 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 680 while (status) { 681 u32 hwirq = ffs(status) - 1; 682 u32 virq = irq_find_mapping(d, hwirq + 683 i * GPIO_PER_REG); 684 u32 t = irq_get_trigger_type(virq); 685 686 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 687 /* Swap polarity (race with GPIO line) */ 688 if (armada_37xx_edge_both_irq_swap_pol(info, 689 hwirq + i * GPIO_PER_REG)) { 690 /* 691 * For spurious irq, which gpio level 692 * is not as expected after incoming 693 * edge, just ack the gpio irq. 694 */ 695 writel(1 << hwirq, 696 info->base + 697 IRQ_STATUS + 4 * i); 698 goto update_status; 699 } 700 } 701 702 generic_handle_irq(virq); 703 704 update_status: 705 /* Update status in case a new IRQ appears */ 706 raw_spin_lock_irqsave(&info->irq_lock, flags); 707 status = readl_relaxed(info->base + 708 IRQ_STATUS + 4 * i); 709 /* Manage only the interrupt that was enabled */ 710 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 711 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 712 } 713 } 714 chained_irq_exit(chip, desc); 715 } 716 717 static unsigned int armada_37xx_irq_startup(struct irq_data *d) 718 { 719 /* 720 * The mask field is a "precomputed bitmask for accessing the 721 * chip registers" which was introduced for the generic 722 * irqchip framework. As we don't use this framework, we can 723 * reuse this field for our own usage. 724 */ 725 d->mask = BIT(d->hwirq % GPIO_PER_REG); 726 727 armada_37xx_irq_unmask(d); 728 729 return 0; 730 } 731 732 static int armada_37xx_irqchip_register(struct platform_device *pdev, 733 struct armada_37xx_pinctrl *info) 734 { 735 struct gpio_chip *gc = &info->gpio_chip; 736 struct irq_chip *irqchip = &info->irq_chip; 737 struct gpio_irq_chip *girq = &gc->irq; 738 struct device_node *np = to_of_node(gc->fwnode); 739 struct device *dev = &pdev->dev; 740 unsigned int i, nr_irq_parent; 741 742 raw_spin_lock_init(&info->irq_lock); 743 744 nr_irq_parent = of_irq_count(np); 745 if (!nr_irq_parent) { 746 dev_err(dev, "invalid or no IRQ\n"); 747 return 0; 748 } 749 750 info->base = devm_platform_ioremap_resource(pdev, 1); 751 if (IS_ERR(info->base)) 752 return PTR_ERR(info->base); 753 754 irqchip->irq_ack = armada_37xx_irq_ack; 755 irqchip->irq_mask = armada_37xx_irq_mask; 756 irqchip->irq_unmask = armada_37xx_irq_unmask; 757 irqchip->irq_set_wake = armada_37xx_irq_set_wake; 758 irqchip->irq_set_type = armada_37xx_irq_set_type; 759 irqchip->irq_startup = armada_37xx_irq_startup; 760 irqchip->name = info->data->name; 761 girq->chip = irqchip; 762 girq->parent_handler = armada_37xx_irq_handler; 763 /* 764 * Many interrupts are connected to the parent interrupt 765 * controller. But we do not take advantage of this and use 766 * the chained irq with all of them. 767 */ 768 girq->num_parents = nr_irq_parent; 769 girq->parents = devm_kcalloc(dev, nr_irq_parent, sizeof(*girq->parents), GFP_KERNEL); 770 if (!girq->parents) 771 return -ENOMEM; 772 for (i = 0; i < nr_irq_parent; i++) { 773 int irq = irq_of_parse_and_map(np, i); 774 775 if (!irq) 776 continue; 777 girq->parents[i] = irq; 778 } 779 girq->default_type = IRQ_TYPE_NONE; 780 girq->handler = handle_edge_irq; 781 782 return 0; 783 } 784 785 static int armada_37xx_gpiochip_register(struct platform_device *pdev, 786 struct armada_37xx_pinctrl *info) 787 { 788 struct device *dev = &pdev->dev; 789 struct fwnode_handle *fwnode; 790 struct gpio_chip *gc; 791 int ret; 792 793 fwnode = gpiochip_node_get_first(dev); 794 if (!fwnode) 795 return -ENODEV; 796 797 info->gpio_chip = armada_37xx_gpiolib_chip; 798 799 gc = &info->gpio_chip; 800 gc->ngpio = info->data->nr_pins; 801 gc->parent = dev; 802 gc->base = -1; 803 gc->fwnode = fwnode; 804 gc->label = info->data->name; 805 806 ret = armada_37xx_irqchip_register(pdev, info); 807 if (ret) 808 return ret; 809 810 return devm_gpiochip_add_data(dev, gc, info); 811 } 812 813 /** 814 * armada_37xx_add_function() - Add a new function to the list 815 * @funcs: array of function to add the new one 816 * @funcsize: size of the remaining space for the function 817 * @name: name of the function to add 818 * 819 * If it is a new function then create it by adding its name else 820 * increment the number of group associated to this function. 821 */ 822 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs, 823 int *funcsize, const char *name) 824 { 825 int i = 0; 826 827 if (*funcsize <= 0) 828 return -EOVERFLOW; 829 830 while (funcs->ngroups) { 831 /* function already there */ 832 if (strcmp(funcs->name, name) == 0) { 833 funcs->ngroups++; 834 835 return -EEXIST; 836 } 837 funcs++; 838 i++; 839 } 840 841 /* append new unique function */ 842 funcs->name = name; 843 funcs->ngroups = 1; 844 (*funcsize)--; 845 846 return 0; 847 } 848 849 /** 850 * armada_37xx_fill_group() - complete the group array 851 * @info: info driver instance 852 * 853 * Based on the data available from the armada_37xx_pin_group array 854 * completes the last member of the struct for each function: the list 855 * of the groups associated to this function. 856 * 857 */ 858 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) 859 { 860 int n, num = 0, funcsize = info->data->nr_pins; 861 struct device *dev = info->dev; 862 863 for (n = 0; n < info->ngroups; n++) { 864 struct armada_37xx_pin_group *grp = &info->groups[n]; 865 int i, j, f; 866 867 grp->pins = devm_kcalloc(dev, grp->npins + grp->extra_npins, 868 sizeof(*grp->pins), 869 GFP_KERNEL); 870 if (!grp->pins) 871 return -ENOMEM; 872 873 for (i = 0; i < grp->npins; i++) 874 grp->pins[i] = grp->start_pin + i; 875 876 for (j = 0; j < grp->extra_npins; j++) 877 grp->pins[i+j] = grp->extra_pin + j; 878 879 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) { 880 int ret; 881 /* check for unique functions and count groups */ 882 ret = armada_37xx_add_function(info->funcs, &funcsize, 883 grp->funcs[f]); 884 if (ret == -EOVERFLOW) 885 dev_err(dev, "More functions than pins(%d)\n", 886 info->data->nr_pins); 887 if (ret < 0) 888 continue; 889 num++; 890 } 891 } 892 893 info->nfuncs = num; 894 895 return 0; 896 } 897 898 /** 899 * armada_37xx_fill_func() - complete the funcs array 900 * @info: info driver instance 901 * 902 * Based on the data available from the armada_37xx_pin_group array 903 * completes the last two member of the struct for each group: 904 * - the list of the pins included in the group 905 * - the list of pinmux functions that can be selected for this group 906 * 907 */ 908 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info) 909 { 910 struct armada_37xx_pmx_func *funcs = info->funcs; 911 struct device *dev = info->dev; 912 int n; 913 914 for (n = 0; n < info->nfuncs; n++) { 915 const char *name = funcs[n].name; 916 const char **groups; 917 int g; 918 919 funcs[n].groups = devm_kcalloc(dev, funcs[n].ngroups, 920 sizeof(*(funcs[n].groups)), 921 GFP_KERNEL); 922 if (!funcs[n].groups) 923 return -ENOMEM; 924 925 groups = funcs[n].groups; 926 927 for (g = 0; g < info->ngroups; g++) { 928 struct armada_37xx_pin_group *gp = &info->groups[g]; 929 int f; 930 931 f = match_string(gp->funcs, NB_FUNCS, name); 932 if (f < 0) 933 continue; 934 935 *groups = gp->name; 936 groups++; 937 } 938 } 939 return 0; 940 } 941 942 static int armada_37xx_pinctrl_register(struct platform_device *pdev, 943 struct armada_37xx_pinctrl *info) 944 { 945 const struct armada_37xx_pin_data *pin_data = info->data; 946 struct pinctrl_desc *ctrldesc = &info->pctl; 947 struct pinctrl_pin_desc *pindesc, *pdesc; 948 struct device *dev = &pdev->dev; 949 char **pin_names; 950 int pin, ret; 951 952 info->groups = pin_data->groups; 953 info->ngroups = pin_data->ngroups; 954 955 ctrldesc->name = "armada_37xx-pinctrl"; 956 ctrldesc->owner = THIS_MODULE; 957 ctrldesc->pctlops = &armada_37xx_pctrl_ops; 958 ctrldesc->pmxops = &armada_37xx_pmx_ops; 959 ctrldesc->confops = &armada_37xx_pinconf_ops; 960 961 pindesc = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*pindesc), GFP_KERNEL); 962 if (!pindesc) 963 return -ENOMEM; 964 965 ctrldesc->pins = pindesc; 966 ctrldesc->npins = pin_data->nr_pins; 967 968 pin_names = devm_kasprintf_strarray(dev, pin_data->name, pin_data->nr_pins); 969 if (IS_ERR(pin_names)) 970 return PTR_ERR(pin_names); 971 972 pdesc = pindesc; 973 for (pin = 0; pin < pin_data->nr_pins; pin++) { 974 pdesc->number = pin; 975 pdesc->name = pin_names[pin]; 976 pdesc++; 977 } 978 979 /* 980 * we allocate functions for number of pins and hope there are 981 * fewer unique functions than pins available 982 */ 983 info->funcs = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*info->funcs), GFP_KERNEL); 984 if (!info->funcs) 985 return -ENOMEM; 986 987 ret = armada_37xx_fill_group(info); 988 if (ret) 989 return ret; 990 991 ret = armada_37xx_fill_func(info); 992 if (ret) 993 return ret; 994 995 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); 996 if (IS_ERR(info->pctl_dev)) 997 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); 998 999 return 0; 1000 } 1001 1002 #if defined(CONFIG_PM) 1003 static int armada_3700_pinctrl_suspend(struct device *dev) 1004 { 1005 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev); 1006 1007 /* Save GPIO state */ 1008 regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l); 1009 regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h); 1010 regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l); 1011 regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32), 1012 &info->pm.out_val_h); 1013 1014 info->pm.irq_en_l = readl(info->base + IRQ_EN); 1015 info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32)); 1016 info->pm.irq_pol_l = readl(info->base + IRQ_POL); 1017 info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32)); 1018 1019 /* Save pinctrl state */ 1020 regmap_read(info->regmap, SELECTION, &info->pm.selection); 1021 1022 return 0; 1023 } 1024 1025 static int armada_3700_pinctrl_resume(struct device *dev) 1026 { 1027 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev); 1028 struct gpio_chip *gc; 1029 struct irq_domain *d; 1030 int i; 1031 1032 /* Restore GPIO state */ 1033 regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l); 1034 regmap_write(info->regmap, OUTPUT_EN + sizeof(u32), 1035 info->pm.out_en_h); 1036 regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l); 1037 regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32), 1038 info->pm.out_val_h); 1039 1040 /* 1041 * Input levels may change during suspend, which is not monitored at 1042 * that time. GPIOs used for both-edge IRQs may not be synchronized 1043 * anymore with their polarities (rising/falling edge) and must be 1044 * re-configured manually. 1045 */ 1046 gc = &info->gpio_chip; 1047 d = gc->irq.domain; 1048 for (i = 0; i < gc->ngpio; i++) { 1049 u32 irq_bit = BIT(i % GPIO_PER_REG); 1050 u32 mask, *irq_pol, input_reg, virq, type, level; 1051 1052 if (i < GPIO_PER_REG) { 1053 mask = info->pm.irq_en_l; 1054 irq_pol = &info->pm.irq_pol_l; 1055 input_reg = INPUT_VAL; 1056 } else { 1057 mask = info->pm.irq_en_h; 1058 irq_pol = &info->pm.irq_pol_h; 1059 input_reg = INPUT_VAL + sizeof(u32); 1060 } 1061 1062 if (!(mask & irq_bit)) 1063 continue; 1064 1065 virq = irq_find_mapping(d, i); 1066 type = irq_get_trigger_type(virq); 1067 1068 /* 1069 * Synchronize level and polarity for both-edge irqs: 1070 * - a high input level expects a falling edge, 1071 * - a low input level exepects a rising edge. 1072 */ 1073 if ((type & IRQ_TYPE_SENSE_MASK) == 1074 IRQ_TYPE_EDGE_BOTH) { 1075 regmap_read(info->regmap, input_reg, &level); 1076 if ((*irq_pol ^ level) & irq_bit) 1077 *irq_pol ^= irq_bit; 1078 } 1079 } 1080 1081 writel(info->pm.irq_en_l, info->base + IRQ_EN); 1082 writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32)); 1083 writel(info->pm.irq_pol_l, info->base + IRQ_POL); 1084 writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32)); 1085 1086 /* Restore pinctrl state */ 1087 regmap_write(info->regmap, SELECTION, info->pm.selection); 1088 1089 return 0; 1090 } 1091 1092 /* 1093 * Since pinctrl is an infrastructure module, its resume should be issued prior 1094 * to other IO drivers. 1095 */ 1096 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = { 1097 .suspend_noirq = armada_3700_pinctrl_suspend, 1098 .resume_noirq = armada_3700_pinctrl_resume, 1099 }; 1100 1101 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops) 1102 #else 1103 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL 1104 #endif /* CONFIG_PM */ 1105 1106 static const struct of_device_id armada_37xx_pinctrl_of_match[] = { 1107 { 1108 .compatible = "marvell,armada3710-sb-pinctrl", 1109 .data = &armada_37xx_pin_sb, 1110 }, 1111 { 1112 .compatible = "marvell,armada3710-nb-pinctrl", 1113 .data = &armada_37xx_pin_nb, 1114 }, 1115 { }, 1116 }; 1117 1118 static const struct regmap_config armada_37xx_pinctrl_regmap_config = { 1119 .reg_bits = 32, 1120 .val_bits = 32, 1121 .reg_stride = 4, 1122 .use_raw_spinlock = true, 1123 }; 1124 1125 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev) 1126 { 1127 struct armada_37xx_pinctrl *info; 1128 struct device *dev = &pdev->dev; 1129 struct regmap *regmap; 1130 void __iomem *base; 1131 int ret; 1132 1133 base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 1134 if (IS_ERR(base)) { 1135 dev_err(dev, "failed to ioremap base address: %pe\n", base); 1136 return PTR_ERR(base); 1137 } 1138 1139 regmap = devm_regmap_init_mmio(dev, base, 1140 &armada_37xx_pinctrl_regmap_config); 1141 if (IS_ERR(regmap)) { 1142 dev_err(dev, "failed to create regmap: %pe\n", regmap); 1143 return PTR_ERR(regmap); 1144 } 1145 1146 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1147 if (!info) 1148 return -ENOMEM; 1149 1150 info->dev = dev; 1151 info->regmap = regmap; 1152 info->data = of_device_get_match_data(dev); 1153 1154 ret = armada_37xx_pinctrl_register(pdev, info); 1155 if (ret) 1156 return ret; 1157 1158 ret = armada_37xx_gpiochip_register(pdev, info); 1159 if (ret) 1160 return ret; 1161 1162 platform_set_drvdata(pdev, info); 1163 1164 return 0; 1165 } 1166 1167 static struct platform_driver armada_37xx_pinctrl_driver = { 1168 .driver = { 1169 .name = "armada-37xx-pinctrl", 1170 .of_match_table = armada_37xx_pinctrl_of_match, 1171 .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS, 1172 }, 1173 }; 1174 1175 builtin_platform_driver_probe(armada_37xx_pinctrl_driver, 1176 armada_37xx_pinctrl_probe); 1177