1 /* 2 * Marvell 37xx SoC pinctrl driver 3 * 4 * Copyright (C) 2017 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2 or later. This program is licensed "as is" 10 * without any warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/gpio/driver.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/of.h> 16 #include <linux/of_irq.h> 17 #include <linux/pinctrl/pinconf-generic.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/platform_device.h> 22 #include <linux/property.h> 23 #include <linux/regmap.h> 24 #include <linux/seq_file.h> 25 #include <linux/slab.h> 26 #include <linux/string_helpers.h> 27 28 #include "../pinctrl-utils.h" 29 30 #define OUTPUT_EN 0x0 31 #define INPUT_VAL 0x10 32 #define OUTPUT_VAL 0x18 33 #define OUTPUT_CTL 0x20 34 #define SELECTION 0x30 35 36 #define IRQ_EN 0x0 37 #define IRQ_POL 0x08 38 #define IRQ_STATUS 0x10 39 #define IRQ_WKUP 0x18 40 41 #define NB_FUNCS 3 42 #define GPIO_PER_REG 32 43 44 /** 45 * struct armada_37xx_pin_group: represents group of pins of a pinmux function. 46 * The pins of a pinmux groups are composed of one or two groups of contiguous 47 * pins. 48 * @name: Name of the pin group, used to lookup the group. 49 * @start_pin: Index of the first pin of the main range of pins belonging to 50 * the group 51 * @npins: Number of pins included in the first range 52 * @reg_mask: Bit mask matching the group in the selection register 53 * @val: Value to write to the registers for a given function 54 * @extra_pin: Index of the first pin of the optional second range of pins 55 * belonging to the group 56 * @extra_npins:Number of pins included in the second optional range 57 * @funcs: A list of pinmux functions that can be selected for this group. 58 * @pins: List of the pins included in the group 59 */ 60 struct armada_37xx_pin_group { 61 const char *name; 62 unsigned int start_pin; 63 unsigned int npins; 64 u32 reg_mask; 65 u32 val[NB_FUNCS]; 66 unsigned int extra_pin; 67 unsigned int extra_npins; 68 const char *funcs[NB_FUNCS]; 69 unsigned int *pins; 70 }; 71 72 struct armada_37xx_pin_data { 73 u8 nr_pins; 74 char *name; 75 struct armada_37xx_pin_group *groups; 76 int ngroups; 77 }; 78 79 struct armada_37xx_pmx_func { 80 const char *name; 81 const char **groups; 82 unsigned int ngroups; 83 }; 84 85 struct armada_37xx_pm_state { 86 u32 out_en_l; 87 u32 out_en_h; 88 u32 out_val_l; 89 u32 out_val_h; 90 u32 irq_en_l; 91 u32 irq_en_h; 92 u32 irq_pol_l; 93 u32 irq_pol_h; 94 u32 selection; 95 }; 96 97 struct armada_37xx_pinctrl { 98 struct regmap *regmap; 99 void __iomem *base; 100 const struct armada_37xx_pin_data *data; 101 struct device *dev; 102 struct gpio_chip gpio_chip; 103 raw_spinlock_t irq_lock; 104 struct pinctrl_desc pctl; 105 struct pinctrl_dev *pctl_dev; 106 struct armada_37xx_pin_group *groups; 107 unsigned int ngroups; 108 struct armada_37xx_pmx_func *funcs; 109 unsigned int nfuncs; 110 struct armada_37xx_pm_state pm; 111 }; 112 113 #define PIN_GRP_GPIO_0(_name, _start, _nr) \ 114 { \ 115 .name = _name, \ 116 .start_pin = _start, \ 117 .npins = _nr, \ 118 .reg_mask = 0, \ 119 .val = {0}, \ 120 .funcs = {"gpio"} \ 121 } 122 123 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \ 124 { \ 125 .name = _name, \ 126 .start_pin = _start, \ 127 .npins = _nr, \ 128 .reg_mask = _mask, \ 129 .val = {0, _mask}, \ 130 .funcs = {_func1, "gpio"} \ 131 } 132 133 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \ 134 { \ 135 .name = _name, \ 136 .start_pin = _start, \ 137 .npins = _nr, \ 138 .reg_mask = _mask, \ 139 .val = {_val1, _val2}, \ 140 .funcs = {_func1, "gpio"} \ 141 } 142 143 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \ 144 { \ 145 .name = _name, \ 146 .start_pin = _start, \ 147 .npins = _nr, \ 148 .reg_mask = _mask, \ 149 .val = {_v1, _v2, _v3}, \ 150 .funcs = {_f1, _f2, "gpio"} \ 151 } 152 153 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \ 154 _f1, _f2) \ 155 { \ 156 .name = _name, \ 157 .start_pin = _start, \ 158 .npins = _nr, \ 159 .reg_mask = _mask, \ 160 .val = {_v1, _v2}, \ 161 .extra_pin = _start2, \ 162 .extra_npins = _nr2, \ 163 .funcs = {_f1, _f2} \ 164 } 165 166 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { 167 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"), 168 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"), 169 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"), 170 PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3), 171 "pwm", "led"), 172 PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4), 173 "pwm", "led"), 174 PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5), 175 "pwm", "led"), 176 PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6), 177 "pwm", "led"), 178 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"), 179 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"), 180 PIN_GRP_GPIO_0("gpio1_5", 5, 1), 181 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"), 182 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"), 183 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"), 184 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"), 185 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"), 186 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"), 187 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"), 188 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"), 189 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), 190 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), 191 18, 2, "gpio", "uart"), 192 }; 193 194 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { 195 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"), 196 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"), 197 PIN_GRP_GPIO_0("gpio2_2", 2, 1), 198 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), 199 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"), 200 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"), 201 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ 202 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), 203 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), 204 PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"), 205 PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12), 206 "ptp", "mii"), 207 PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13), 208 "ptp", "mii"), 209 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), 210 "mii", "mii_err"), 211 }; 212 213 static const struct armada_37xx_pin_data armada_37xx_pin_nb = { 214 .nr_pins = 36, 215 .name = "GPIO1", 216 .groups = armada_37xx_nb_groups, 217 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups), 218 }; 219 220 static const struct armada_37xx_pin_data armada_37xx_pin_sb = { 221 .nr_pins = 30, 222 .name = "GPIO2", 223 .groups = armada_37xx_sb_groups, 224 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups), 225 }; 226 227 static inline void armada_37xx_update_reg(unsigned int *reg, 228 unsigned int *offset) 229 { 230 /* We never have more than 2 registers */ 231 if (*offset >= GPIO_PER_REG) { 232 *offset -= GPIO_PER_REG; 233 *reg += sizeof(u32); 234 } 235 } 236 237 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin( 238 struct armada_37xx_pinctrl *info, int pin, int *grp) 239 { 240 while (*grp < info->ngroups) { 241 struct armada_37xx_pin_group *group = &info->groups[*grp]; 242 int j; 243 244 *grp = *grp + 1; 245 for (j = 0; j < (group->npins + group->extra_npins); j++) 246 if (group->pins[j] == pin) 247 return group; 248 } 249 return NULL; 250 } 251 252 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev, 253 unsigned int selector, unsigned long *config) 254 { 255 return -ENOTSUPP; 256 } 257 258 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev, 259 unsigned int selector, unsigned long *configs, 260 unsigned int num_configs) 261 { 262 return -ENOTSUPP; 263 } 264 265 static const struct pinconf_ops armada_37xx_pinconf_ops = { 266 .is_generic = true, 267 .pin_config_group_get = armada_37xx_pin_config_group_get, 268 .pin_config_group_set = armada_37xx_pin_config_group_set, 269 }; 270 271 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev) 272 { 273 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 274 275 return info->ngroups; 276 } 277 278 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev, 279 unsigned int group) 280 { 281 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 282 283 return info->groups[group].name; 284 } 285 286 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev, 287 unsigned int selector, 288 const unsigned int **pins, 289 unsigned int *npins) 290 { 291 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 292 293 if (selector >= info->ngroups) 294 return -EINVAL; 295 296 *pins = info->groups[selector].pins; 297 *npins = info->groups[selector].npins + 298 info->groups[selector].extra_npins; 299 300 return 0; 301 } 302 303 static const struct pinctrl_ops armada_37xx_pctrl_ops = { 304 .get_groups_count = armada_37xx_get_groups_count, 305 .get_group_name = armada_37xx_get_group_name, 306 .get_group_pins = armada_37xx_get_group_pins, 307 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 308 .dt_free_map = pinctrl_utils_free_map, 309 }; 310 311 /* 312 * Pinmux_ops handling 313 */ 314 315 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 316 { 317 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 318 319 return info->nfuncs; 320 } 321 322 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev, 323 unsigned int selector) 324 { 325 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 326 327 return info->funcs[selector].name; 328 } 329 330 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev, 331 unsigned int selector, 332 const char * const **groups, 333 unsigned int * const num_groups) 334 { 335 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 336 337 *groups = info->funcs[selector].groups; 338 *num_groups = info->funcs[selector].ngroups; 339 340 return 0; 341 } 342 343 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev, 344 const char *name, 345 struct armada_37xx_pin_group *grp) 346 { 347 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 348 struct device *dev = info->dev; 349 unsigned int reg = SELECTION; 350 unsigned int mask = grp->reg_mask; 351 int func, val; 352 353 dev_dbg(dev, "enable function %s group %s\n", name, grp->name); 354 355 func = match_string(grp->funcs, NB_FUNCS, name); 356 if (func < 0) 357 return -ENOTSUPP; 358 359 val = grp->val[func]; 360 361 return regmap_update_bits(info->regmap, reg, mask, val); 362 } 363 364 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev, 365 unsigned int selector, 366 unsigned int group) 367 { 368 369 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 370 struct armada_37xx_pin_group *grp = &info->groups[group]; 371 const char *name = info->funcs[selector].name; 372 373 return armada_37xx_pmx_set_by_name(pctldev, name, grp); 374 } 375 376 static inline void armada_37xx_irq_update_reg(unsigned int *reg, 377 struct irq_data *d) 378 { 379 int offset = irqd_to_hwirq(d); 380 381 armada_37xx_update_reg(reg, &offset); 382 } 383 384 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip, 385 unsigned int offset) 386 { 387 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 388 unsigned int reg = OUTPUT_EN; 389 unsigned int mask; 390 391 armada_37xx_update_reg(®, &offset); 392 mask = BIT(offset); 393 394 return regmap_update_bits(info->regmap, reg, mask, 0); 395 } 396 397 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip, 398 unsigned int offset) 399 { 400 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 401 unsigned int reg = OUTPUT_EN; 402 unsigned int val, mask; 403 int ret; 404 405 armada_37xx_update_reg(®, &offset); 406 mask = BIT(offset); 407 ret = regmap_read(info->regmap, reg, &val); 408 if (ret) 409 return ret; 410 411 if (val & mask) 412 return GPIO_LINE_DIRECTION_OUT; 413 414 return GPIO_LINE_DIRECTION_IN; 415 } 416 417 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip, 418 unsigned int offset, int value) 419 { 420 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 421 unsigned int en_offset = offset; 422 unsigned int reg = OUTPUT_VAL; 423 unsigned int mask, val, ret; 424 425 armada_37xx_update_reg(®, &offset); 426 mask = BIT(offset); 427 val = value ? mask : 0; 428 429 ret = regmap_update_bits(info->regmap, reg, mask, val); 430 if (ret) 431 return ret; 432 433 reg = OUTPUT_EN; 434 armada_37xx_update_reg(®, &en_offset); 435 436 return regmap_update_bits(info->regmap, reg, mask, mask); 437 } 438 439 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 440 { 441 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 442 unsigned int reg = INPUT_VAL; 443 unsigned int val, mask; 444 int ret; 445 446 armada_37xx_update_reg(®, &offset); 447 mask = BIT(offset); 448 449 ret = regmap_read(info->regmap, reg, &val); 450 if (ret) 451 return ret; 452 453 return (val & mask) != 0; 454 } 455 456 static int armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 457 int value) 458 { 459 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 460 unsigned int reg = OUTPUT_VAL; 461 unsigned int mask, val; 462 463 armada_37xx_update_reg(®, &offset); 464 mask = BIT(offset); 465 val = value ? mask : 0; 466 467 return regmap_update_bits(info->regmap, reg, mask, val); 468 } 469 470 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 471 struct pinctrl_gpio_range *range, 472 unsigned int offset, bool input) 473 { 474 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 475 struct gpio_chip *chip = range->gc; 476 int ret; 477 478 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 479 offset, range->name, offset, input ? "input" : "output"); 480 481 if (input) 482 ret = armada_37xx_gpio_direction_input(chip, offset); 483 else 484 ret = armada_37xx_gpio_direction_output(chip, offset, 0); 485 486 return ret; 487 } 488 489 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev, 490 struct pinctrl_gpio_range *range, 491 unsigned int offset) 492 { 493 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 494 struct armada_37xx_pin_group *group; 495 int grp = 0; 496 int ret; 497 498 dev_dbg(info->dev, "requesting gpio %d\n", offset); 499 500 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp))) { 501 ret = armada_37xx_pmx_set_by_name(pctldev, "gpio", group); 502 if (ret) 503 return ret; 504 } 505 506 return 0; 507 } 508 509 static const struct pinmux_ops armada_37xx_pmx_ops = { 510 .get_functions_count = armada_37xx_pmx_get_funcs_count, 511 .get_function_name = armada_37xx_pmx_get_func_name, 512 .get_function_groups = armada_37xx_pmx_get_groups, 513 .set_mux = armada_37xx_pmx_set, 514 .gpio_request_enable = armada_37xx_gpio_request_enable, 515 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction, 516 }; 517 518 static const struct gpio_chip armada_37xx_gpiolib_chip = { 519 .request = gpiochip_generic_request, 520 .free = gpiochip_generic_free, 521 .set = armada_37xx_gpio_set, 522 .get = armada_37xx_gpio_get, 523 .get_direction = armada_37xx_gpio_get_direction, 524 .direction_input = armada_37xx_gpio_direction_input, 525 .direction_output = armada_37xx_gpio_direction_output, 526 .owner = THIS_MODULE, 527 }; 528 529 static void armada_37xx_irq_ack(struct irq_data *d) 530 { 531 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 532 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 533 u32 reg = IRQ_STATUS; 534 unsigned long flags; 535 536 armada_37xx_irq_update_reg(®, d); 537 raw_spin_lock_irqsave(&info->irq_lock, flags); 538 writel(d->mask, info->base + reg); 539 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 540 } 541 542 static void armada_37xx_irq_mask(struct irq_data *d) 543 { 544 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 545 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 546 u32 val, reg = IRQ_EN; 547 unsigned long flags; 548 549 armada_37xx_irq_update_reg(®, d); 550 raw_spin_lock_irqsave(&info->irq_lock, flags); 551 val = readl(info->base + reg); 552 writel(val & ~d->mask, info->base + reg); 553 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 554 gpiochip_disable_irq(chip, irqd_to_hwirq(d)); 555 } 556 557 static void armada_37xx_irq_unmask(struct irq_data *d) 558 { 559 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 560 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 561 u32 val, reg = IRQ_EN; 562 unsigned long flags; 563 564 gpiochip_enable_irq(chip, irqd_to_hwirq(d)); 565 armada_37xx_irq_update_reg(®, d); 566 raw_spin_lock_irqsave(&info->irq_lock, flags); 567 val = readl(info->base + reg); 568 writel(val | d->mask, info->base + reg); 569 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 570 } 571 572 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on) 573 { 574 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 575 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 576 u32 val, reg = IRQ_WKUP; 577 unsigned long flags; 578 579 armada_37xx_irq_update_reg(®, d); 580 raw_spin_lock_irqsave(&info->irq_lock, flags); 581 val = readl(info->base + reg); 582 if (on) 583 val |= (BIT(d->hwirq % GPIO_PER_REG)); 584 else 585 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); 586 writel(val, info->base + reg); 587 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 588 589 return 0; 590 } 591 592 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type) 593 { 594 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 595 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 596 u32 val, reg = IRQ_POL; 597 unsigned long flags; 598 599 raw_spin_lock_irqsave(&info->irq_lock, flags); 600 armada_37xx_irq_update_reg(®, d); 601 val = readl(info->base + reg); 602 switch (type) { 603 case IRQ_TYPE_EDGE_RISING: 604 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); 605 break; 606 case IRQ_TYPE_EDGE_FALLING: 607 val |= (BIT(d->hwirq % GPIO_PER_REG)); 608 break; 609 case IRQ_TYPE_EDGE_BOTH: { 610 u32 in_val, in_reg = INPUT_VAL; 611 612 armada_37xx_irq_update_reg(&in_reg, d); 613 regmap_read(info->regmap, in_reg, &in_val); 614 615 /* Set initial polarity based on current input level. */ 616 if (in_val & BIT(d->hwirq % GPIO_PER_REG)) 617 val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */ 618 else 619 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */ 620 break; 621 } 622 default: 623 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 624 return -EINVAL; 625 } 626 writel(val, info->base + reg); 627 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 628 629 return 0; 630 } 631 632 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info, 633 u32 pin_idx) 634 { 635 u32 reg_idx = pin_idx / GPIO_PER_REG; 636 u32 bit_num = pin_idx % GPIO_PER_REG; 637 u32 p, l, ret; 638 unsigned long flags; 639 640 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l); 641 642 raw_spin_lock_irqsave(&info->irq_lock, flags); 643 p = readl(info->base + IRQ_POL + 4 * reg_idx); 644 if ((p ^ l) & (1 << bit_num)) { 645 /* 646 * For the gpios which are used for both-edge irqs, when their 647 * interrupts happen, their input levels are changed, 648 * yet their interrupt polarities are kept in old values, we 649 * should synchronize their interrupt polarities; for example, 650 * at first a gpio's input level is low and its interrupt 651 * polarity control is "Detect rising edge", then the gpio has 652 * a interrupt , its level turns to high, we should change its 653 * polarity control to "Detect falling edge" correspondingly. 654 */ 655 p ^= 1 << bit_num; 656 writel(p, info->base + IRQ_POL + 4 * reg_idx); 657 ret = 0; 658 } else { 659 /* Spurious irq */ 660 ret = -1; 661 } 662 663 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 664 return ret; 665 } 666 667 static void armada_37xx_irq_handler(struct irq_desc *desc) 668 { 669 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 670 struct irq_chip *chip = irq_desc_get_chip(desc); 671 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc); 672 struct irq_domain *d = gc->irq.domain; 673 int i; 674 675 chained_irq_enter(chip, desc); 676 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) { 677 u32 status; 678 unsigned long flags; 679 680 raw_spin_lock_irqsave(&info->irq_lock, flags); 681 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i); 682 /* Manage only the interrupt that was enabled */ 683 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 684 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 685 while (status) { 686 u32 hwirq = ffs(status) - 1; 687 u32 virq = irq_find_mapping(d, hwirq + 688 i * GPIO_PER_REG); 689 u32 t = irq_get_trigger_type(virq); 690 691 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 692 /* Swap polarity (race with GPIO line) */ 693 if (armada_37xx_edge_both_irq_swap_pol(info, 694 hwirq + i * GPIO_PER_REG)) { 695 /* 696 * For spurious irq, which gpio level 697 * is not as expected after incoming 698 * edge, just ack the gpio irq. 699 */ 700 writel(1 << hwirq, 701 info->base + 702 IRQ_STATUS + 4 * i); 703 goto update_status; 704 } 705 } 706 707 generic_handle_irq(virq); 708 709 update_status: 710 /* Update status in case a new IRQ appears */ 711 raw_spin_lock_irqsave(&info->irq_lock, flags); 712 status = readl_relaxed(info->base + 713 IRQ_STATUS + 4 * i); 714 /* Manage only the interrupt that was enabled */ 715 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 716 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 717 } 718 } 719 chained_irq_exit(chip, desc); 720 } 721 722 static unsigned int armada_37xx_irq_startup(struct irq_data *d) 723 { 724 /* 725 * The mask field is a "precomputed bitmask for accessing the 726 * chip registers" which was introduced for the generic 727 * irqchip framework. As we don't use this framework, we can 728 * reuse this field for our own usage. 729 */ 730 d->mask = BIT(d->hwirq % GPIO_PER_REG); 731 732 armada_37xx_irq_unmask(d); 733 734 return 0; 735 } 736 737 static void armada_37xx_irq_print_chip(struct irq_data *d, struct seq_file *p) 738 { 739 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 740 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 741 742 seq_puts(p, info->data->name); 743 } 744 745 static const struct irq_chip armada_37xx_irqchip = { 746 .irq_ack = armada_37xx_irq_ack, 747 .irq_mask = armada_37xx_irq_mask, 748 .irq_unmask = armada_37xx_irq_unmask, 749 .irq_set_wake = armada_37xx_irq_set_wake, 750 .irq_set_type = armada_37xx_irq_set_type, 751 .irq_startup = armada_37xx_irq_startup, 752 .irq_print_chip = armada_37xx_irq_print_chip, 753 .flags = IRQCHIP_IMMUTABLE, 754 GPIOCHIP_IRQ_RESOURCE_HELPERS, 755 }; 756 757 static int armada_37xx_irqchip_register(struct platform_device *pdev, 758 struct armada_37xx_pinctrl *info) 759 { 760 struct gpio_chip *gc = &info->gpio_chip; 761 struct gpio_irq_chip *girq = &gc->irq; 762 struct device_node *np = to_of_node(gc->fwnode); 763 struct device *dev = &pdev->dev; 764 unsigned int i, nr_irq_parent; 765 766 raw_spin_lock_init(&info->irq_lock); 767 768 nr_irq_parent = of_irq_count(np); 769 if (!nr_irq_parent) { 770 dev_err(dev, "invalid or no IRQ\n"); 771 return 0; 772 } 773 774 info->base = devm_platform_ioremap_resource(pdev, 1); 775 if (IS_ERR(info->base)) 776 return PTR_ERR(info->base); 777 778 gpio_irq_chip_set_chip(girq, &armada_37xx_irqchip); 779 girq->parent_handler = armada_37xx_irq_handler; 780 /* 781 * Many interrupts are connected to the parent interrupt 782 * controller. But we do not take advantage of this and use 783 * the chained irq with all of them. 784 */ 785 girq->num_parents = nr_irq_parent; 786 girq->parents = devm_kcalloc(dev, nr_irq_parent, sizeof(*girq->parents), GFP_KERNEL); 787 if (!girq->parents) 788 return -ENOMEM; 789 for (i = 0; i < nr_irq_parent; i++) { 790 int irq = irq_of_parse_and_map(np, i); 791 792 if (!irq) 793 continue; 794 girq->parents[i] = irq; 795 } 796 girq->default_type = IRQ_TYPE_NONE; 797 girq->handler = handle_edge_irq; 798 799 return 0; 800 } 801 802 static int armada_37xx_gpiochip_register(struct platform_device *pdev, 803 struct armada_37xx_pinctrl *info) 804 { 805 struct device *dev = &pdev->dev; 806 struct fwnode_handle *fwnode; 807 struct gpio_chip *gc; 808 int ret; 809 810 fwnode = gpiochip_node_get_first(dev); 811 if (!fwnode) 812 return -ENODEV; 813 814 info->gpio_chip = armada_37xx_gpiolib_chip; 815 816 gc = &info->gpio_chip; 817 gc->ngpio = info->data->nr_pins; 818 gc->parent = dev; 819 gc->base = -1; 820 gc->fwnode = fwnode; 821 gc->label = info->data->name; 822 823 ret = armada_37xx_irqchip_register(pdev, info); 824 if (ret) 825 return ret; 826 827 return devm_gpiochip_add_data(dev, gc, info); 828 } 829 830 /** 831 * armada_37xx_add_function() - Add a new function to the list 832 * @funcs: array of function to add the new one 833 * @funcsize: size of the remaining space for the function 834 * @name: name of the function to add 835 * 836 * If it is a new function then create it by adding its name else 837 * increment the number of group associated to this function. 838 */ 839 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs, 840 int *funcsize, const char *name) 841 { 842 if (*funcsize <= 0) 843 return -EOVERFLOW; 844 845 while (funcs->ngroups) { 846 /* function already there */ 847 if (strcmp(funcs->name, name) == 0) { 848 funcs->ngroups++; 849 850 return -EEXIST; 851 } 852 funcs++; 853 } 854 855 /* append new unique function */ 856 funcs->name = name; 857 funcs->ngroups = 1; 858 (*funcsize)--; 859 860 return 0; 861 } 862 863 /** 864 * armada_37xx_fill_group() - complete the group array 865 * @info: info driver instance 866 * 867 * Based on the data available from the armada_37xx_pin_group array 868 * completes the last member of the struct for each function: the list 869 * of the groups associated to this function. 870 * 871 */ 872 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) 873 { 874 int n, num = 0, funcsize = info->data->nr_pins; 875 struct device *dev = info->dev; 876 877 for (n = 0; n < info->ngroups; n++) { 878 struct armada_37xx_pin_group *grp = &info->groups[n]; 879 int i, j, f; 880 881 grp->pins = devm_kcalloc(dev, grp->npins + grp->extra_npins, 882 sizeof(*grp->pins), 883 GFP_KERNEL); 884 if (!grp->pins) 885 return -ENOMEM; 886 887 for (i = 0; i < grp->npins; i++) 888 grp->pins[i] = grp->start_pin + i; 889 890 for (j = 0; j < grp->extra_npins; j++) 891 grp->pins[i+j] = grp->extra_pin + j; 892 893 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) { 894 int ret; 895 /* check for unique functions and count groups */ 896 ret = armada_37xx_add_function(info->funcs, &funcsize, 897 grp->funcs[f]); 898 if (ret == -EOVERFLOW) 899 dev_err(dev, "More functions than pins(%d)\n", 900 info->data->nr_pins); 901 if (ret < 0) 902 continue; 903 num++; 904 } 905 } 906 907 info->nfuncs = num; 908 909 return 0; 910 } 911 912 /** 913 * armada_37xx_fill_func() - complete the funcs array 914 * @info: info driver instance 915 * 916 * Based on the data available from the armada_37xx_pin_group array 917 * completes the last two member of the struct for each group: 918 * - the list of the pins included in the group 919 * - the list of pinmux functions that can be selected for this group 920 * 921 */ 922 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info) 923 { 924 struct armada_37xx_pmx_func *funcs = info->funcs; 925 struct device *dev = info->dev; 926 int n; 927 928 for (n = 0; n < info->nfuncs; n++) { 929 const char *name = funcs[n].name; 930 const char **groups; 931 int g; 932 933 funcs[n].groups = devm_kcalloc(dev, funcs[n].ngroups, 934 sizeof(*(funcs[n].groups)), 935 GFP_KERNEL); 936 if (!funcs[n].groups) 937 return -ENOMEM; 938 939 groups = funcs[n].groups; 940 941 for (g = 0; g < info->ngroups; g++) { 942 struct armada_37xx_pin_group *gp = &info->groups[g]; 943 int f; 944 945 f = match_string(gp->funcs, NB_FUNCS, name); 946 if (f < 0) 947 continue; 948 949 *groups = gp->name; 950 groups++; 951 } 952 } 953 return 0; 954 } 955 956 static int armada_37xx_pinctrl_register(struct platform_device *pdev, 957 struct armada_37xx_pinctrl *info) 958 { 959 const struct armada_37xx_pin_data *pin_data = info->data; 960 struct pinctrl_desc *ctrldesc = &info->pctl; 961 struct pinctrl_pin_desc *pindesc, *pdesc; 962 struct device *dev = &pdev->dev; 963 char **pin_names; 964 int pin, ret; 965 966 info->groups = pin_data->groups; 967 info->ngroups = pin_data->ngroups; 968 969 ctrldesc->name = "armada_37xx-pinctrl"; 970 ctrldesc->owner = THIS_MODULE; 971 ctrldesc->pctlops = &armada_37xx_pctrl_ops; 972 ctrldesc->pmxops = &armada_37xx_pmx_ops; 973 ctrldesc->confops = &armada_37xx_pinconf_ops; 974 975 pindesc = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*pindesc), GFP_KERNEL); 976 if (!pindesc) 977 return -ENOMEM; 978 979 ctrldesc->pins = pindesc; 980 ctrldesc->npins = pin_data->nr_pins; 981 982 pin_names = devm_kasprintf_strarray(dev, pin_data->name, pin_data->nr_pins); 983 if (IS_ERR(pin_names)) 984 return PTR_ERR(pin_names); 985 986 pdesc = pindesc; 987 for (pin = 0; pin < pin_data->nr_pins; pin++) { 988 pdesc->number = pin; 989 pdesc->name = pin_names[pin]; 990 pdesc++; 991 } 992 993 /* 994 * we allocate functions for number of pins and hope there are 995 * fewer unique functions than pins available 996 */ 997 info->funcs = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*info->funcs), GFP_KERNEL); 998 if (!info->funcs) 999 return -ENOMEM; 1000 1001 ret = armada_37xx_fill_group(info); 1002 if (ret) 1003 return ret; 1004 1005 ret = armada_37xx_fill_func(info); 1006 if (ret) 1007 return ret; 1008 1009 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); 1010 if (IS_ERR(info->pctl_dev)) 1011 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); 1012 1013 return 0; 1014 } 1015 1016 static int armada_3700_pinctrl_suspend(struct device *dev) 1017 { 1018 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev); 1019 1020 /* Save GPIO state */ 1021 regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l); 1022 regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h); 1023 regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l); 1024 regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32), 1025 &info->pm.out_val_h); 1026 1027 info->pm.irq_en_l = readl(info->base + IRQ_EN); 1028 info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32)); 1029 info->pm.irq_pol_l = readl(info->base + IRQ_POL); 1030 info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32)); 1031 1032 /* Save pinctrl state */ 1033 regmap_read(info->regmap, SELECTION, &info->pm.selection); 1034 1035 return 0; 1036 } 1037 1038 static int armada_3700_pinctrl_resume(struct device *dev) 1039 { 1040 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev); 1041 struct gpio_chip *gc; 1042 struct irq_domain *d; 1043 int i; 1044 1045 /* Restore GPIO state */ 1046 regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l); 1047 regmap_write(info->regmap, OUTPUT_EN + sizeof(u32), 1048 info->pm.out_en_h); 1049 regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l); 1050 regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32), 1051 info->pm.out_val_h); 1052 1053 /* 1054 * Input levels may change during suspend, which is not monitored at 1055 * that time. GPIOs used for both-edge IRQs may not be synchronized 1056 * anymore with their polarities (rising/falling edge) and must be 1057 * re-configured manually. 1058 */ 1059 gc = &info->gpio_chip; 1060 d = gc->irq.domain; 1061 for (i = 0; i < gc->ngpio; i++) { 1062 u32 irq_bit = BIT(i % GPIO_PER_REG); 1063 u32 mask, *irq_pol, input_reg, virq, type, level; 1064 1065 if (i < GPIO_PER_REG) { 1066 mask = info->pm.irq_en_l; 1067 irq_pol = &info->pm.irq_pol_l; 1068 input_reg = INPUT_VAL; 1069 } else { 1070 mask = info->pm.irq_en_h; 1071 irq_pol = &info->pm.irq_pol_h; 1072 input_reg = INPUT_VAL + sizeof(u32); 1073 } 1074 1075 if (!(mask & irq_bit)) 1076 continue; 1077 1078 virq = irq_find_mapping(d, i); 1079 type = irq_get_trigger_type(virq); 1080 1081 /* 1082 * Synchronize level and polarity for both-edge irqs: 1083 * - a high input level expects a falling edge, 1084 * - a low input level exepects a rising edge. 1085 */ 1086 if ((type & IRQ_TYPE_SENSE_MASK) == 1087 IRQ_TYPE_EDGE_BOTH) { 1088 regmap_read(info->regmap, input_reg, &level); 1089 if ((*irq_pol ^ level) & irq_bit) 1090 *irq_pol ^= irq_bit; 1091 } 1092 } 1093 1094 writel(info->pm.irq_en_l, info->base + IRQ_EN); 1095 writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32)); 1096 writel(info->pm.irq_pol_l, info->base + IRQ_POL); 1097 writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32)); 1098 1099 /* Restore pinctrl state */ 1100 regmap_write(info->regmap, SELECTION, info->pm.selection); 1101 1102 return 0; 1103 } 1104 1105 /* 1106 * Since pinctrl is an infrastructure module, its resume should be issued prior 1107 * to other IO drivers. 1108 */ 1109 static DEFINE_NOIRQ_DEV_PM_OPS(armada_3700_pinctrl_pm_ops, 1110 armada_3700_pinctrl_suspend, armada_3700_pinctrl_resume); 1111 1112 static const struct of_device_id armada_37xx_pinctrl_of_match[] = { 1113 { 1114 .compatible = "marvell,armada3710-sb-pinctrl", 1115 .data = &armada_37xx_pin_sb, 1116 }, 1117 { 1118 .compatible = "marvell,armada3710-nb-pinctrl", 1119 .data = &armada_37xx_pin_nb, 1120 }, 1121 { }, 1122 }; 1123 1124 static const struct regmap_config armada_37xx_pinctrl_regmap_config = { 1125 .reg_bits = 32, 1126 .val_bits = 32, 1127 .reg_stride = 4, 1128 .use_raw_spinlock = true, 1129 }; 1130 1131 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev) 1132 { 1133 struct armada_37xx_pinctrl *info; 1134 struct device *dev = &pdev->dev; 1135 struct regmap *regmap; 1136 void __iomem *base; 1137 int ret; 1138 1139 base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 1140 if (IS_ERR(base)) { 1141 dev_err(dev, "failed to ioremap base address: %pe\n", base); 1142 return PTR_ERR(base); 1143 } 1144 1145 regmap = devm_regmap_init_mmio(dev, base, 1146 &armada_37xx_pinctrl_regmap_config); 1147 if (IS_ERR(regmap)) { 1148 dev_err(dev, "failed to create regmap: %pe\n", regmap); 1149 return PTR_ERR(regmap); 1150 } 1151 1152 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1153 if (!info) 1154 return -ENOMEM; 1155 1156 info->dev = dev; 1157 info->regmap = regmap; 1158 info->data = of_device_get_match_data(dev); 1159 1160 ret = armada_37xx_pinctrl_register(pdev, info); 1161 if (ret) 1162 return ret; 1163 1164 ret = armada_37xx_gpiochip_register(pdev, info); 1165 if (ret) 1166 return ret; 1167 1168 platform_set_drvdata(pdev, info); 1169 1170 return 0; 1171 } 1172 1173 static struct platform_driver armada_37xx_pinctrl_driver = { 1174 .driver = { 1175 .name = "armada-37xx-pinctrl", 1176 .of_match_table = armada_37xx_pinctrl_of_match, 1177 .pm = pm_sleep_ptr(&armada_3700_pinctrl_pm_ops), 1178 }, 1179 }; 1180 1181 builtin_platform_driver_probe(armada_37xx_pinctrl_driver, 1182 armada_37xx_pinctrl_probe); 1183