1 /* 2 * Marvell 37xx SoC pinctrl driver 3 * 4 * Copyright (C) 2017 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2 or later. This program is licensed "as is" 10 * without any warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/gpio/driver.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/platform_device.h> 24 #include <linux/property.h> 25 #include <linux/regmap.h> 26 #include <linux/slab.h> 27 #include <linux/string_helpers.h> 28 29 #include "../pinctrl-utils.h" 30 31 #define OUTPUT_EN 0x0 32 #define INPUT_VAL 0x10 33 #define OUTPUT_VAL 0x18 34 #define OUTPUT_CTL 0x20 35 #define SELECTION 0x30 36 37 #define IRQ_EN 0x0 38 #define IRQ_POL 0x08 39 #define IRQ_STATUS 0x10 40 #define IRQ_WKUP 0x18 41 42 #define NB_FUNCS 3 43 #define GPIO_PER_REG 32 44 45 /** 46 * struct armada_37xx_pin_group: represents group of pins of a pinmux function. 47 * The pins of a pinmux groups are composed of one or two groups of contiguous 48 * pins. 49 * @name: Name of the pin group, used to lookup the group. 50 * @start_pin: Index of the first pin of the main range of pins belonging to 51 * the group 52 * @npins: Number of pins included in the first range 53 * @reg_mask: Bit mask matching the group in the selection register 54 * @val: Value to write to the registers for a given function 55 * @extra_pin: Index of the first pin of the optional second range of pins 56 * belonging to the group 57 * @extra_npins:Number of pins included in the second optional range 58 * @funcs: A list of pinmux functions that can be selected for this group. 59 * @pins: List of the pins included in the group 60 */ 61 struct armada_37xx_pin_group { 62 const char *name; 63 unsigned int start_pin; 64 unsigned int npins; 65 u32 reg_mask; 66 u32 val[NB_FUNCS]; 67 unsigned int extra_pin; 68 unsigned int extra_npins; 69 const char *funcs[NB_FUNCS]; 70 unsigned int *pins; 71 }; 72 73 struct armada_37xx_pin_data { 74 u8 nr_pins; 75 char *name; 76 struct armada_37xx_pin_group *groups; 77 int ngroups; 78 }; 79 80 struct armada_37xx_pmx_func { 81 const char *name; 82 const char **groups; 83 unsigned int ngroups; 84 }; 85 86 struct armada_37xx_pm_state { 87 u32 out_en_l; 88 u32 out_en_h; 89 u32 out_val_l; 90 u32 out_val_h; 91 u32 irq_en_l; 92 u32 irq_en_h; 93 u32 irq_pol_l; 94 u32 irq_pol_h; 95 u32 selection; 96 }; 97 98 struct armada_37xx_pinctrl { 99 struct regmap *regmap; 100 void __iomem *base; 101 const struct armada_37xx_pin_data *data; 102 struct device *dev; 103 struct gpio_chip gpio_chip; 104 struct irq_chip irq_chip; 105 spinlock_t irq_lock; 106 struct pinctrl_desc pctl; 107 struct pinctrl_dev *pctl_dev; 108 struct armada_37xx_pin_group *groups; 109 unsigned int ngroups; 110 struct armada_37xx_pmx_func *funcs; 111 unsigned int nfuncs; 112 struct armada_37xx_pm_state pm; 113 }; 114 115 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \ 116 { \ 117 .name = _name, \ 118 .start_pin = _start, \ 119 .npins = _nr, \ 120 .reg_mask = _mask, \ 121 .val = {0, _mask}, \ 122 .funcs = {_func1, _func2} \ 123 } 124 125 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \ 126 { \ 127 .name = _name, \ 128 .start_pin = _start, \ 129 .npins = _nr, \ 130 .reg_mask = _mask, \ 131 .val = {0, _mask}, \ 132 .funcs = {_func1, "gpio"} \ 133 } 134 135 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \ 136 { \ 137 .name = _name, \ 138 .start_pin = _start, \ 139 .npins = _nr, \ 140 .reg_mask = _mask, \ 141 .val = {_val1, _val2}, \ 142 .funcs = {_func1, "gpio"} \ 143 } 144 145 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \ 146 { \ 147 .name = _name, \ 148 .start_pin = _start, \ 149 .npins = _nr, \ 150 .reg_mask = _mask, \ 151 .val = {_v1, _v2, _v3}, \ 152 .funcs = {_f1, _f2, "gpio"} \ 153 } 154 155 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \ 156 _f1, _f2) \ 157 { \ 158 .name = _name, \ 159 .start_pin = _start, \ 160 .npins = _nr, \ 161 .reg_mask = _mask, \ 162 .val = {_v1, _v2}, \ 163 .extra_pin = _start2, \ 164 .extra_npins = _nr2, \ 165 .funcs = {_f1, _f2} \ 166 } 167 168 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { 169 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"), 170 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"), 171 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"), 172 PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3), 173 "pwm", "led"), 174 PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4), 175 "pwm", "led"), 176 PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5), 177 "pwm", "led"), 178 PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6), 179 "pwm", "led"), 180 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"), 181 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"), 182 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"), 183 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"), 184 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"), 185 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"), 186 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"), 187 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"), 188 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"), 189 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"), 190 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), 191 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), 192 18, 2, "gpio", "uart"), 193 }; 194 195 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { 196 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"), 197 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"), 198 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), 199 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"), 200 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"), 201 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ 202 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), 203 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), 204 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), 205 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), 206 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), 207 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), 208 "mii", "mii_err"), 209 }; 210 211 static const struct armada_37xx_pin_data armada_37xx_pin_nb = { 212 .nr_pins = 36, 213 .name = "GPIO1", 214 .groups = armada_37xx_nb_groups, 215 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups), 216 }; 217 218 static const struct armada_37xx_pin_data armada_37xx_pin_sb = { 219 .nr_pins = 30, 220 .name = "GPIO2", 221 .groups = armada_37xx_sb_groups, 222 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups), 223 }; 224 225 static inline void armada_37xx_update_reg(unsigned int *reg, 226 unsigned int *offset) 227 { 228 /* We never have more than 2 registers */ 229 if (*offset >= GPIO_PER_REG) { 230 *offset -= GPIO_PER_REG; 231 *reg += sizeof(u32); 232 } 233 } 234 235 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin( 236 struct armada_37xx_pinctrl *info, int pin, int *grp) 237 { 238 while (*grp < info->ngroups) { 239 struct armada_37xx_pin_group *group = &info->groups[*grp]; 240 int j; 241 242 *grp = *grp + 1; 243 for (j = 0; j < (group->npins + group->extra_npins); j++) 244 if (group->pins[j] == pin) 245 return group; 246 } 247 return NULL; 248 } 249 250 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev, 251 unsigned int selector, unsigned long *config) 252 { 253 return -ENOTSUPP; 254 } 255 256 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev, 257 unsigned int selector, unsigned long *configs, 258 unsigned int num_configs) 259 { 260 return -ENOTSUPP; 261 } 262 263 static const struct pinconf_ops armada_37xx_pinconf_ops = { 264 .is_generic = true, 265 .pin_config_group_get = armada_37xx_pin_config_group_get, 266 .pin_config_group_set = armada_37xx_pin_config_group_set, 267 }; 268 269 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev) 270 { 271 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 272 273 return info->ngroups; 274 } 275 276 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev, 277 unsigned int group) 278 { 279 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 280 281 return info->groups[group].name; 282 } 283 284 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev, 285 unsigned int selector, 286 const unsigned int **pins, 287 unsigned int *npins) 288 { 289 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 290 291 if (selector >= info->ngroups) 292 return -EINVAL; 293 294 *pins = info->groups[selector].pins; 295 *npins = info->groups[selector].npins + 296 info->groups[selector].extra_npins; 297 298 return 0; 299 } 300 301 static const struct pinctrl_ops armada_37xx_pctrl_ops = { 302 .get_groups_count = armada_37xx_get_groups_count, 303 .get_group_name = armada_37xx_get_group_name, 304 .get_group_pins = armada_37xx_get_group_pins, 305 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 306 .dt_free_map = pinctrl_utils_free_map, 307 }; 308 309 /* 310 * Pinmux_ops handling 311 */ 312 313 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 314 { 315 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 316 317 return info->nfuncs; 318 } 319 320 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev, 321 unsigned int selector) 322 { 323 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 324 325 return info->funcs[selector].name; 326 } 327 328 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev, 329 unsigned int selector, 330 const char * const **groups, 331 unsigned int * const num_groups) 332 { 333 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 334 335 *groups = info->funcs[selector].groups; 336 *num_groups = info->funcs[selector].ngroups; 337 338 return 0; 339 } 340 341 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev, 342 const char *name, 343 struct armada_37xx_pin_group *grp) 344 { 345 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 346 struct device *dev = info->dev; 347 unsigned int reg = SELECTION; 348 unsigned int mask = grp->reg_mask; 349 int func, val; 350 351 dev_dbg(dev, "enable function %s group %s\n", name, grp->name); 352 353 func = match_string(grp->funcs, NB_FUNCS, name); 354 if (func < 0) 355 return -ENOTSUPP; 356 357 val = grp->val[func]; 358 359 regmap_update_bits(info->regmap, reg, mask, val); 360 361 return 0; 362 } 363 364 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev, 365 unsigned int selector, 366 unsigned int group) 367 { 368 369 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 370 struct armada_37xx_pin_group *grp = &info->groups[group]; 371 const char *name = info->funcs[selector].name; 372 373 return armada_37xx_pmx_set_by_name(pctldev, name, grp); 374 } 375 376 static inline void armada_37xx_irq_update_reg(unsigned int *reg, 377 struct irq_data *d) 378 { 379 int offset = irqd_to_hwirq(d); 380 381 armada_37xx_update_reg(reg, &offset); 382 } 383 384 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip, 385 unsigned int offset) 386 { 387 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 388 unsigned int reg = OUTPUT_EN; 389 unsigned int mask; 390 391 armada_37xx_update_reg(®, &offset); 392 mask = BIT(offset); 393 394 return regmap_update_bits(info->regmap, reg, mask, 0); 395 } 396 397 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip, 398 unsigned int offset) 399 { 400 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 401 unsigned int reg = OUTPUT_EN; 402 unsigned int val, mask; 403 404 armada_37xx_update_reg(®, &offset); 405 mask = BIT(offset); 406 regmap_read(info->regmap, reg, &val); 407 408 if (val & mask) 409 return GPIO_LINE_DIRECTION_OUT; 410 411 return GPIO_LINE_DIRECTION_IN; 412 } 413 414 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip, 415 unsigned int offset, int value) 416 { 417 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 418 unsigned int reg = OUTPUT_EN; 419 unsigned int mask, val, ret; 420 421 armada_37xx_update_reg(®, &offset); 422 mask = BIT(offset); 423 424 ret = regmap_update_bits(info->regmap, reg, mask, mask); 425 426 if (ret) 427 return ret; 428 429 reg = OUTPUT_VAL; 430 val = value ? mask : 0; 431 regmap_update_bits(info->regmap, reg, mask, val); 432 433 return 0; 434 } 435 436 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 437 { 438 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 439 unsigned int reg = INPUT_VAL; 440 unsigned int val, mask; 441 442 armada_37xx_update_reg(®, &offset); 443 mask = BIT(offset); 444 445 regmap_read(info->regmap, reg, &val); 446 447 return (val & mask) != 0; 448 } 449 450 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 451 int value) 452 { 453 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 454 unsigned int reg = OUTPUT_VAL; 455 unsigned int mask, val; 456 457 armada_37xx_update_reg(®, &offset); 458 mask = BIT(offset); 459 val = value ? mask : 0; 460 461 regmap_update_bits(info->regmap, reg, mask, val); 462 } 463 464 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 465 struct pinctrl_gpio_range *range, 466 unsigned int offset, bool input) 467 { 468 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 469 struct gpio_chip *chip = range->gc; 470 471 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 472 offset, range->name, offset, input ? "input" : "output"); 473 474 if (input) 475 armada_37xx_gpio_direction_input(chip, offset); 476 else 477 armada_37xx_gpio_direction_output(chip, offset, 0); 478 479 return 0; 480 } 481 482 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev, 483 struct pinctrl_gpio_range *range, 484 unsigned int offset) 485 { 486 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 487 struct armada_37xx_pin_group *group; 488 int grp = 0; 489 490 dev_dbg(info->dev, "requesting gpio %d\n", offset); 491 492 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp))) 493 armada_37xx_pmx_set_by_name(pctldev, "gpio", group); 494 495 return 0; 496 } 497 498 static const struct pinmux_ops armada_37xx_pmx_ops = { 499 .get_functions_count = armada_37xx_pmx_get_funcs_count, 500 .get_function_name = armada_37xx_pmx_get_func_name, 501 .get_function_groups = armada_37xx_pmx_get_groups, 502 .set_mux = armada_37xx_pmx_set, 503 .gpio_request_enable = armada_37xx_gpio_request_enable, 504 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction, 505 }; 506 507 static const struct gpio_chip armada_37xx_gpiolib_chip = { 508 .request = gpiochip_generic_request, 509 .free = gpiochip_generic_free, 510 .set = armada_37xx_gpio_set, 511 .get = armada_37xx_gpio_get, 512 .get_direction = armada_37xx_gpio_get_direction, 513 .direction_input = armada_37xx_gpio_direction_input, 514 .direction_output = armada_37xx_gpio_direction_output, 515 .owner = THIS_MODULE, 516 }; 517 518 static void armada_37xx_irq_ack(struct irq_data *d) 519 { 520 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 521 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 522 u32 reg = IRQ_STATUS; 523 unsigned long flags; 524 525 armada_37xx_irq_update_reg(®, d); 526 spin_lock_irqsave(&info->irq_lock, flags); 527 writel(d->mask, info->base + reg); 528 spin_unlock_irqrestore(&info->irq_lock, flags); 529 } 530 531 static void armada_37xx_irq_mask(struct irq_data *d) 532 { 533 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 534 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 535 u32 val, reg = IRQ_EN; 536 unsigned long flags; 537 538 armada_37xx_irq_update_reg(®, d); 539 spin_lock_irqsave(&info->irq_lock, flags); 540 val = readl(info->base + reg); 541 writel(val & ~d->mask, info->base + reg); 542 spin_unlock_irqrestore(&info->irq_lock, flags); 543 } 544 545 static void armada_37xx_irq_unmask(struct irq_data *d) 546 { 547 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 548 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 549 u32 val, reg = IRQ_EN; 550 unsigned long flags; 551 552 armada_37xx_irq_update_reg(®, d); 553 spin_lock_irqsave(&info->irq_lock, flags); 554 val = readl(info->base + reg); 555 writel(val | d->mask, info->base + reg); 556 spin_unlock_irqrestore(&info->irq_lock, flags); 557 } 558 559 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on) 560 { 561 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 562 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 563 u32 val, reg = IRQ_WKUP; 564 unsigned long flags; 565 566 armada_37xx_irq_update_reg(®, d); 567 spin_lock_irqsave(&info->irq_lock, flags); 568 val = readl(info->base + reg); 569 if (on) 570 val |= (BIT(d->hwirq % GPIO_PER_REG)); 571 else 572 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); 573 writel(val, info->base + reg); 574 spin_unlock_irqrestore(&info->irq_lock, flags); 575 576 return 0; 577 } 578 579 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type) 580 { 581 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 582 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 583 u32 val, reg = IRQ_POL; 584 unsigned long flags; 585 586 spin_lock_irqsave(&info->irq_lock, flags); 587 armada_37xx_irq_update_reg(®, d); 588 val = readl(info->base + reg); 589 switch (type) { 590 case IRQ_TYPE_EDGE_RISING: 591 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); 592 break; 593 case IRQ_TYPE_EDGE_FALLING: 594 val |= (BIT(d->hwirq % GPIO_PER_REG)); 595 break; 596 case IRQ_TYPE_EDGE_BOTH: { 597 u32 in_val, in_reg = INPUT_VAL; 598 599 armada_37xx_irq_update_reg(&in_reg, d); 600 regmap_read(info->regmap, in_reg, &in_val); 601 602 /* Set initial polarity based on current input level. */ 603 if (in_val & BIT(d->hwirq % GPIO_PER_REG)) 604 val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */ 605 else 606 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */ 607 break; 608 } 609 default: 610 spin_unlock_irqrestore(&info->irq_lock, flags); 611 return -EINVAL; 612 } 613 writel(val, info->base + reg); 614 spin_unlock_irqrestore(&info->irq_lock, flags); 615 616 return 0; 617 } 618 619 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info, 620 u32 pin_idx) 621 { 622 u32 reg_idx = pin_idx / GPIO_PER_REG; 623 u32 bit_num = pin_idx % GPIO_PER_REG; 624 u32 p, l, ret; 625 unsigned long flags; 626 627 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l); 628 629 spin_lock_irqsave(&info->irq_lock, flags); 630 p = readl(info->base + IRQ_POL + 4 * reg_idx); 631 if ((p ^ l) & (1 << bit_num)) { 632 /* 633 * For the gpios which are used for both-edge irqs, when their 634 * interrupts happen, their input levels are changed, 635 * yet their interrupt polarities are kept in old values, we 636 * should synchronize their interrupt polarities; for example, 637 * at first a gpio's input level is low and its interrupt 638 * polarity control is "Detect rising edge", then the gpio has 639 * a interrupt , its level turns to high, we should change its 640 * polarity control to "Detect falling edge" correspondingly. 641 */ 642 p ^= 1 << bit_num; 643 writel(p, info->base + IRQ_POL + 4 * reg_idx); 644 ret = 0; 645 } else { 646 /* Spurious irq */ 647 ret = -1; 648 } 649 650 spin_unlock_irqrestore(&info->irq_lock, flags); 651 return ret; 652 } 653 654 static void armada_37xx_irq_handler(struct irq_desc *desc) 655 { 656 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 657 struct irq_chip *chip = irq_desc_get_chip(desc); 658 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc); 659 struct irq_domain *d = gc->irq.domain; 660 int i; 661 662 chained_irq_enter(chip, desc); 663 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) { 664 u32 status; 665 unsigned long flags; 666 667 spin_lock_irqsave(&info->irq_lock, flags); 668 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i); 669 /* Manage only the interrupt that was enabled */ 670 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 671 spin_unlock_irqrestore(&info->irq_lock, flags); 672 while (status) { 673 u32 hwirq = ffs(status) - 1; 674 u32 virq = irq_find_mapping(d, hwirq + 675 i * GPIO_PER_REG); 676 u32 t = irq_get_trigger_type(virq); 677 678 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 679 /* Swap polarity (race with GPIO line) */ 680 if (armada_37xx_edge_both_irq_swap_pol(info, 681 hwirq + i * GPIO_PER_REG)) { 682 /* 683 * For spurious irq, which gpio level 684 * is not as expected after incoming 685 * edge, just ack the gpio irq. 686 */ 687 writel(1 << hwirq, 688 info->base + 689 IRQ_STATUS + 4 * i); 690 goto update_status; 691 } 692 } 693 694 generic_handle_irq(virq); 695 696 update_status: 697 /* Update status in case a new IRQ appears */ 698 spin_lock_irqsave(&info->irq_lock, flags); 699 status = readl_relaxed(info->base + 700 IRQ_STATUS + 4 * i); 701 /* Manage only the interrupt that was enabled */ 702 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 703 spin_unlock_irqrestore(&info->irq_lock, flags); 704 } 705 } 706 chained_irq_exit(chip, desc); 707 } 708 709 static unsigned int armada_37xx_irq_startup(struct irq_data *d) 710 { 711 /* 712 * The mask field is a "precomputed bitmask for accessing the 713 * chip registers" which was introduced for the generic 714 * irqchip framework. As we don't use this framework, we can 715 * reuse this field for our own usage. 716 */ 717 d->mask = BIT(d->hwirq % GPIO_PER_REG); 718 719 armada_37xx_irq_unmask(d); 720 721 return 0; 722 } 723 724 static int armada_37xx_irqchip_register(struct platform_device *pdev, 725 struct armada_37xx_pinctrl *info) 726 { 727 struct gpio_chip *gc = &info->gpio_chip; 728 struct irq_chip *irqchip = &info->irq_chip; 729 struct gpio_irq_chip *girq = &gc->irq; 730 struct device_node *np = to_of_node(gc->fwnode); 731 struct device *dev = &pdev->dev; 732 unsigned int i, nr_irq_parent; 733 734 spin_lock_init(&info->irq_lock); 735 736 nr_irq_parent = of_irq_count(np); 737 if (!nr_irq_parent) { 738 dev_err(dev, "invalid or no IRQ\n"); 739 return 0; 740 } 741 742 info->base = devm_platform_ioremap_resource(pdev, 1); 743 if (IS_ERR(info->base)) 744 return PTR_ERR(info->base); 745 746 irqchip->irq_ack = armada_37xx_irq_ack; 747 irqchip->irq_mask = armada_37xx_irq_mask; 748 irqchip->irq_unmask = armada_37xx_irq_unmask; 749 irqchip->irq_set_wake = armada_37xx_irq_set_wake; 750 irqchip->irq_set_type = armada_37xx_irq_set_type; 751 irqchip->irq_startup = armada_37xx_irq_startup; 752 irqchip->name = info->data->name; 753 girq->chip = irqchip; 754 girq->parent_handler = armada_37xx_irq_handler; 755 /* 756 * Many interrupts are connected to the parent interrupt 757 * controller. But we do not take advantage of this and use 758 * the chained irq with all of them. 759 */ 760 girq->num_parents = nr_irq_parent; 761 girq->parents = devm_kcalloc(dev, nr_irq_parent, sizeof(*girq->parents), GFP_KERNEL); 762 if (!girq->parents) 763 return -ENOMEM; 764 for (i = 0; i < nr_irq_parent; i++) { 765 int irq = irq_of_parse_and_map(np, i); 766 767 if (!irq) 768 continue; 769 girq->parents[i] = irq; 770 } 771 girq->default_type = IRQ_TYPE_NONE; 772 girq->handler = handle_edge_irq; 773 774 return 0; 775 } 776 777 static int armada_37xx_gpiochip_register(struct platform_device *pdev, 778 struct armada_37xx_pinctrl *info) 779 { 780 struct device *dev = &pdev->dev; 781 struct fwnode_handle *fwnode; 782 struct gpio_chip *gc; 783 int ret; 784 785 fwnode = gpiochip_node_get_first(dev); 786 if (!fwnode) 787 return -ENODEV; 788 789 info->gpio_chip = armada_37xx_gpiolib_chip; 790 791 gc = &info->gpio_chip; 792 gc->ngpio = info->data->nr_pins; 793 gc->parent = dev; 794 gc->base = -1; 795 gc->fwnode = fwnode; 796 gc->label = info->data->name; 797 798 ret = armada_37xx_irqchip_register(pdev, info); 799 if (ret) 800 return ret; 801 802 return devm_gpiochip_add_data(dev, gc, info); 803 } 804 805 /** 806 * armada_37xx_add_function() - Add a new function to the list 807 * @funcs: array of function to add the new one 808 * @funcsize: size of the remaining space for the function 809 * @name: name of the function to add 810 * 811 * If it is a new function then create it by adding its name else 812 * increment the number of group associated to this function. 813 */ 814 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs, 815 int *funcsize, const char *name) 816 { 817 int i = 0; 818 819 if (*funcsize <= 0) 820 return -EOVERFLOW; 821 822 while (funcs->ngroups) { 823 /* function already there */ 824 if (strcmp(funcs->name, name) == 0) { 825 funcs->ngroups++; 826 827 return -EEXIST; 828 } 829 funcs++; 830 i++; 831 } 832 833 /* append new unique function */ 834 funcs->name = name; 835 funcs->ngroups = 1; 836 (*funcsize)--; 837 838 return 0; 839 } 840 841 /** 842 * armada_37xx_fill_group() - complete the group array 843 * @info: info driver instance 844 * 845 * Based on the data available from the armada_37xx_pin_group array 846 * completes the last member of the struct for each function: the list 847 * of the groups associated to this function. 848 * 849 */ 850 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) 851 { 852 int n, num = 0, funcsize = info->data->nr_pins; 853 struct device *dev = info->dev; 854 855 for (n = 0; n < info->ngroups; n++) { 856 struct armada_37xx_pin_group *grp = &info->groups[n]; 857 int i, j, f; 858 859 grp->pins = devm_kcalloc(dev, grp->npins + grp->extra_npins, 860 sizeof(*grp->pins), 861 GFP_KERNEL); 862 if (!grp->pins) 863 return -ENOMEM; 864 865 for (i = 0; i < grp->npins; i++) 866 grp->pins[i] = grp->start_pin + i; 867 868 for (j = 0; j < grp->extra_npins; j++) 869 grp->pins[i+j] = grp->extra_pin + j; 870 871 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) { 872 int ret; 873 /* check for unique functions and count groups */ 874 ret = armada_37xx_add_function(info->funcs, &funcsize, 875 grp->funcs[f]); 876 if (ret == -EOVERFLOW) 877 dev_err(dev, "More functions than pins(%d)\n", 878 info->data->nr_pins); 879 if (ret < 0) 880 continue; 881 num++; 882 } 883 } 884 885 info->nfuncs = num; 886 887 return 0; 888 } 889 890 /** 891 * armada_37xx_fill_func() - complete the funcs array 892 * @info: info driver instance 893 * 894 * Based on the data available from the armada_37xx_pin_group array 895 * completes the last two member of the struct for each group: 896 * - the list of the pins included in the group 897 * - the list of pinmux functions that can be selected for this group 898 * 899 */ 900 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info) 901 { 902 struct armada_37xx_pmx_func *funcs = info->funcs; 903 struct device *dev = info->dev; 904 int n; 905 906 for (n = 0; n < info->nfuncs; n++) { 907 const char *name = funcs[n].name; 908 const char **groups; 909 int g; 910 911 funcs[n].groups = devm_kcalloc(dev, funcs[n].ngroups, 912 sizeof(*(funcs[n].groups)), 913 GFP_KERNEL); 914 if (!funcs[n].groups) 915 return -ENOMEM; 916 917 groups = funcs[n].groups; 918 919 for (g = 0; g < info->ngroups; g++) { 920 struct armada_37xx_pin_group *gp = &info->groups[g]; 921 int f; 922 923 f = match_string(gp->funcs, NB_FUNCS, name); 924 if (f < 0) 925 continue; 926 927 *groups = gp->name; 928 groups++; 929 } 930 } 931 return 0; 932 } 933 934 static int armada_37xx_pinctrl_register(struct platform_device *pdev, 935 struct armada_37xx_pinctrl *info) 936 { 937 const struct armada_37xx_pin_data *pin_data = info->data; 938 struct pinctrl_desc *ctrldesc = &info->pctl; 939 struct pinctrl_pin_desc *pindesc, *pdesc; 940 struct device *dev = &pdev->dev; 941 char **pin_names; 942 int pin, ret; 943 944 info->groups = pin_data->groups; 945 info->ngroups = pin_data->ngroups; 946 947 ctrldesc->name = "armada_37xx-pinctrl"; 948 ctrldesc->owner = THIS_MODULE; 949 ctrldesc->pctlops = &armada_37xx_pctrl_ops; 950 ctrldesc->pmxops = &armada_37xx_pmx_ops; 951 ctrldesc->confops = &armada_37xx_pinconf_ops; 952 953 pindesc = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*pindesc), GFP_KERNEL); 954 if (!pindesc) 955 return -ENOMEM; 956 957 ctrldesc->pins = pindesc; 958 ctrldesc->npins = pin_data->nr_pins; 959 960 pin_names = devm_kasprintf_strarray(dev, pin_data->name, pin_data->nr_pins); 961 if (IS_ERR(pin_names)) 962 return PTR_ERR(pin_names); 963 964 pdesc = pindesc; 965 for (pin = 0; pin < pin_data->nr_pins; pin++) { 966 pdesc->number = pin; 967 pdesc->name = pin_names[pin]; 968 pdesc++; 969 } 970 971 /* 972 * we allocate functions for number of pins and hope there are 973 * fewer unique functions than pins available 974 */ 975 info->funcs = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*info->funcs), GFP_KERNEL); 976 if (!info->funcs) 977 return -ENOMEM; 978 979 ret = armada_37xx_fill_group(info); 980 if (ret) 981 return ret; 982 983 ret = armada_37xx_fill_func(info); 984 if (ret) 985 return ret; 986 987 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); 988 if (IS_ERR(info->pctl_dev)) 989 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); 990 991 return 0; 992 } 993 994 #if defined(CONFIG_PM) 995 static int armada_3700_pinctrl_suspend(struct device *dev) 996 { 997 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev); 998 999 /* Save GPIO state */ 1000 regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l); 1001 regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h); 1002 regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l); 1003 regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32), 1004 &info->pm.out_val_h); 1005 1006 info->pm.irq_en_l = readl(info->base + IRQ_EN); 1007 info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32)); 1008 info->pm.irq_pol_l = readl(info->base + IRQ_POL); 1009 info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32)); 1010 1011 /* Save pinctrl state */ 1012 regmap_read(info->regmap, SELECTION, &info->pm.selection); 1013 1014 return 0; 1015 } 1016 1017 static int armada_3700_pinctrl_resume(struct device *dev) 1018 { 1019 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev); 1020 struct gpio_chip *gc; 1021 struct irq_domain *d; 1022 int i; 1023 1024 /* Restore GPIO state */ 1025 regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l); 1026 regmap_write(info->regmap, OUTPUT_EN + sizeof(u32), 1027 info->pm.out_en_h); 1028 regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l); 1029 regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32), 1030 info->pm.out_val_h); 1031 1032 /* 1033 * Input levels may change during suspend, which is not monitored at 1034 * that time. GPIOs used for both-edge IRQs may not be synchronized 1035 * anymore with their polarities (rising/falling edge) and must be 1036 * re-configured manually. 1037 */ 1038 gc = &info->gpio_chip; 1039 d = gc->irq.domain; 1040 for (i = 0; i < gc->ngpio; i++) { 1041 u32 irq_bit = BIT(i % GPIO_PER_REG); 1042 u32 mask, *irq_pol, input_reg, virq, type, level; 1043 1044 if (i < GPIO_PER_REG) { 1045 mask = info->pm.irq_en_l; 1046 irq_pol = &info->pm.irq_pol_l; 1047 input_reg = INPUT_VAL; 1048 } else { 1049 mask = info->pm.irq_en_h; 1050 irq_pol = &info->pm.irq_pol_h; 1051 input_reg = INPUT_VAL + sizeof(u32); 1052 } 1053 1054 if (!(mask & irq_bit)) 1055 continue; 1056 1057 virq = irq_find_mapping(d, i); 1058 type = irq_get_trigger_type(virq); 1059 1060 /* 1061 * Synchronize level and polarity for both-edge irqs: 1062 * - a high input level expects a falling edge, 1063 * - a low input level exepects a rising edge. 1064 */ 1065 if ((type & IRQ_TYPE_SENSE_MASK) == 1066 IRQ_TYPE_EDGE_BOTH) { 1067 regmap_read(info->regmap, input_reg, &level); 1068 if ((*irq_pol ^ level) & irq_bit) 1069 *irq_pol ^= irq_bit; 1070 } 1071 } 1072 1073 writel(info->pm.irq_en_l, info->base + IRQ_EN); 1074 writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32)); 1075 writel(info->pm.irq_pol_l, info->base + IRQ_POL); 1076 writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32)); 1077 1078 /* Restore pinctrl state */ 1079 regmap_write(info->regmap, SELECTION, info->pm.selection); 1080 1081 return 0; 1082 } 1083 1084 /* 1085 * Since pinctrl is an infrastructure module, its resume should be issued prior 1086 * to other IO drivers. 1087 */ 1088 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = { 1089 .suspend_noirq = armada_3700_pinctrl_suspend, 1090 .resume_noirq = armada_3700_pinctrl_resume, 1091 }; 1092 1093 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops) 1094 #else 1095 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL 1096 #endif /* CONFIG_PM */ 1097 1098 static const struct of_device_id armada_37xx_pinctrl_of_match[] = { 1099 { 1100 .compatible = "marvell,armada3710-sb-pinctrl", 1101 .data = &armada_37xx_pin_sb, 1102 }, 1103 { 1104 .compatible = "marvell,armada3710-nb-pinctrl", 1105 .data = &armada_37xx_pin_nb, 1106 }, 1107 { }, 1108 }; 1109 1110 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev) 1111 { 1112 struct armada_37xx_pinctrl *info; 1113 struct device *dev = &pdev->dev; 1114 struct device_node *np = dev->of_node; 1115 struct regmap *regmap; 1116 int ret; 1117 1118 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1119 if (!info) 1120 return -ENOMEM; 1121 1122 info->dev = dev; 1123 1124 regmap = syscon_node_to_regmap(np); 1125 if (IS_ERR(regmap)) 1126 return dev_err_probe(dev, PTR_ERR(regmap), "cannot get regmap\n"); 1127 info->regmap = regmap; 1128 1129 info->data = of_device_get_match_data(dev); 1130 1131 ret = armada_37xx_pinctrl_register(pdev, info); 1132 if (ret) 1133 return ret; 1134 1135 ret = armada_37xx_gpiochip_register(pdev, info); 1136 if (ret) 1137 return ret; 1138 1139 platform_set_drvdata(pdev, info); 1140 1141 return 0; 1142 } 1143 1144 static struct platform_driver armada_37xx_pinctrl_driver = { 1145 .driver = { 1146 .name = "armada-37xx-pinctrl", 1147 .of_match_table = armada_37xx_pinctrl_of_match, 1148 .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS, 1149 }, 1150 }; 1151 1152 builtin_platform_driver_probe(armada_37xx_pinctrl_driver, 1153 armada_37xx_pinctrl_probe); 1154