1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell ac5 pinctrl driver based on mvebu pinctrl core 4 * 5 * Copyright (C) 2021 Marvell 6 * 7 * Noam Liron <lnoam@marvell.com> 8 */ 9 10 #include <linux/err.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/platform_device.h> 14 #include <linux/of.h> 15 #include <linux/pinctrl/pinctrl.h> 16 17 #include "pinctrl-mvebu.h" 18 19 static struct mvebu_mpp_mode ac5_mpp_modes[] = { 20 MPP_MODE(0, 21 MPP_FUNCTION(0, "gpio", NULL), 22 MPP_FUNCTION(1, "sdio", "d0"), 23 MPP_FUNCTION(2, "nand", "io4")), 24 MPP_MODE(1, 25 MPP_FUNCTION(0, "gpio", NULL), 26 MPP_FUNCTION(1, "sdio", "d1"), 27 MPP_FUNCTION(2, "nand", "io3")), 28 MPP_MODE(2, 29 MPP_FUNCTION(0, "gpio", NULL), 30 MPP_FUNCTION(1, "sdio", "d2"), 31 MPP_FUNCTION(2, "nand", "io2")), 32 MPP_MODE(3, 33 MPP_FUNCTION(0, "gpio", NULL), 34 MPP_FUNCTION(1, "sdio", "d3"), 35 MPP_FUNCTION(2, "nand", "io7")), 36 MPP_MODE(4, 37 MPP_FUNCTION(0, "gpio", NULL), 38 MPP_FUNCTION(1, "sdio", "d4"), 39 MPP_FUNCTION(2, "nand", "io6"), 40 MPP_FUNCTION(3, "uart3", "txd"), 41 MPP_FUNCTION(4, "uart2", "txd")), 42 MPP_MODE(5, 43 MPP_FUNCTION(0, "gpio", NULL), 44 MPP_FUNCTION(1, "sdio", "d5"), 45 MPP_FUNCTION(2, "nand", "io5"), 46 MPP_FUNCTION(3, "uart3", "rxd"), 47 MPP_FUNCTION(4, "uart2", "rxd")), 48 MPP_MODE(6, 49 MPP_FUNCTION(0, "gpio", NULL), 50 MPP_FUNCTION(1, "sdio", "d6"), 51 MPP_FUNCTION(2, "nand", "io0"), 52 MPP_FUNCTION(3, "i2c1", "sck")), 53 MPP_MODE(7, 54 MPP_FUNCTION(0, "gpio", NULL), 55 MPP_FUNCTION(1, "sdio", "d7"), 56 MPP_FUNCTION(2, "nand", "io1"), 57 MPP_FUNCTION(3, "i2c1", "sda")), 58 MPP_MODE(8, 59 MPP_FUNCTION(0, "gpio", NULL), 60 MPP_FUNCTION(1, "sdio", "clk"), 61 MPP_FUNCTION(2, "nand", "wen")), 62 MPP_MODE(9, 63 MPP_FUNCTION(0, "gpio", NULL), 64 MPP_FUNCTION(1, "sdio", "cmd"), 65 MPP_FUNCTION(2, "nand", "ale")), 66 MPP_MODE(10, 67 MPP_FUNCTION(0, "gpio", NULL), 68 MPP_FUNCTION(1, "sdio", "ds"), 69 MPP_FUNCTION(2, "nand", "cle")), 70 MPP_MODE(11, 71 MPP_FUNCTION(0, "gpio", NULL), 72 MPP_FUNCTION(1, "sdio", "rst"), 73 MPP_FUNCTION(2, "nand", "cen")), 74 MPP_MODE(12, 75 MPP_FUNCTION(0, "gpio", NULL), 76 MPP_FUNCTION(1, "spi0", "clk")), 77 MPP_MODE(13, 78 MPP_FUNCTION(0, "gpio", NULL), 79 MPP_FUNCTION(1, "spi0", "csn")), 80 MPP_MODE(14, 81 MPP_FUNCTION(0, "gpio", NULL), 82 MPP_FUNCTION(1, "spi0", "mosi")), 83 MPP_MODE(15, 84 MPP_FUNCTION(0, "gpio", NULL), 85 MPP_FUNCTION(1, "spi0", "miso")), 86 MPP_MODE(16, 87 MPP_FUNCTION(0, "gpio", NULL), 88 MPP_FUNCTION(1, "spi0", "wpn"), 89 MPP_FUNCTION(2, "nand", "ren"), 90 MPP_FUNCTION(3, "uart1", "txd")), 91 MPP_MODE(17, 92 MPP_FUNCTION(0, "gpio", NULL), 93 MPP_FUNCTION(1, "spi0", "hold"), 94 MPP_FUNCTION(2, "nand", "rb"), 95 MPP_FUNCTION(3, "uart1", "rxd")), 96 MPP_MODE(18, 97 MPP_FUNCTION(0, "gpio", NULL), 98 MPP_FUNCTION(1, "tsen_int", NULL), 99 MPP_FUNCTION(2, "uart2", "rxd"), 100 MPP_FUNCTION(3, "wd_int", NULL)), 101 MPP_MODE(19, 102 MPP_FUNCTION(0, "gpio", NULL), 103 MPP_FUNCTION(1, "dev_init_done", NULL), 104 MPP_FUNCTION(2, "uart2", "txd")), 105 MPP_MODE(20, 106 MPP_FUNCTION(0, "gpio", NULL), 107 MPP_FUNCTION(2, "i2c1", "sck"), 108 MPP_FUNCTION(3, "spi1", "clk"), 109 MPP_FUNCTION(4, "uart3", "txd")), 110 MPP_MODE(21, 111 MPP_FUNCTION(0, "gpio", NULL), 112 MPP_FUNCTION(2, "i2c1", "sda"), 113 MPP_FUNCTION(3, "spi1", "csn"), 114 MPP_FUNCTION(4, "uart3", "rxd")), 115 MPP_MODE(22, 116 MPP_FUNCTION(0, "gpio", NULL), 117 MPP_FUNCTION(3, "spi1", "mosi")), 118 MPP_MODE(23, 119 MPP_FUNCTION(0, "gpio", NULL), 120 MPP_FUNCTION(3, "spi1", "miso")), 121 MPP_MODE(24, 122 MPP_FUNCTION(0, "gpio", NULL), 123 MPP_FUNCTION(1, "wd_int", NULL), 124 MPP_FUNCTION(2, "uart2", "txd"), 125 MPP_FUNCTION(3, "uartsd", "txd")), 126 MPP_MODE(25, 127 MPP_FUNCTION(0, "gpio", NULL), 128 MPP_FUNCTION(1, "int_out", NULL), 129 MPP_FUNCTION(2, "uart2", "rxd"), 130 MPP_FUNCTION(3, "uartsd", "rxd")), 131 MPP_MODE(26, 132 MPP_FUNCTION(0, "gpio", NULL), 133 MPP_FUNCTION(1, "i2c0", "sck"), 134 MPP_FUNCTION(2, "ptp", "clk1"), 135 MPP_FUNCTION(3, "uart3", "txd")), 136 MPP_MODE(27, 137 MPP_FUNCTION(0, "gpio", NULL), 138 MPP_FUNCTION(1, "i2c0", "sda"), 139 MPP_FUNCTION(2, "ptp", "pulse"), 140 MPP_FUNCTION(3, "uart3", "rxd")), 141 MPP_MODE(28, 142 MPP_FUNCTION(0, "gpio", NULL), 143 MPP_FUNCTION(1, "xg", "mdio"), 144 MPP_FUNCTION(2, "ge", "mdio"), 145 MPP_FUNCTION(3, "uart3", "txd")), 146 MPP_MODE(29, 147 MPP_FUNCTION(0, "gpio", NULL), 148 MPP_FUNCTION(1, "xg", "mdio"), 149 MPP_FUNCTION(2, "ge", "mdio"), 150 MPP_FUNCTION(3, "uart3", "rxd")), 151 MPP_MODE(30, 152 MPP_FUNCTION(0, "gpio", NULL), 153 MPP_FUNCTION(1, "xg", "mdio"), 154 MPP_FUNCTION(2, "ge", "mdio"), 155 MPP_FUNCTION(3, "ge", "mdio")), 156 MPP_MODE(31, 157 MPP_FUNCTION(0, "gpio", NULL), 158 MPP_FUNCTION(1, "xg", "mdio"), 159 MPP_FUNCTION(2, "ge", "mdio"), 160 MPP_FUNCTION(3, "ge", "mdio")), 161 MPP_MODE(32, 162 MPP_FUNCTION(0, "gpio", NULL), 163 MPP_FUNCTION(1, "uart0", "txd")), 164 MPP_MODE(33, 165 MPP_FUNCTION(0, "gpio", NULL), 166 MPP_FUNCTION(1, "uart0", "rxd"), 167 MPP_FUNCTION(2, "ptp", "clk1"), 168 MPP_FUNCTION(3, "ptp", "pulse")), 169 MPP_MODE(34, 170 MPP_FUNCTION(0, "gpio", NULL), 171 MPP_FUNCTION(1, "ge", "mdio"), 172 MPP_FUNCTION(2, "uart3", "rxd")), 173 MPP_MODE(35, 174 MPP_FUNCTION(0, "gpio", NULL), 175 MPP_FUNCTION(1, "ge", "mdio"), 176 MPP_FUNCTION(2, "uart3", "txd"), 177 MPP_FUNCTION(3, "pcie", "rstoutn")), 178 MPP_MODE(36, 179 MPP_FUNCTION(0, "gpio", NULL), 180 MPP_FUNCTION(1, "ptp", "clk0_tp"), 181 MPP_FUNCTION(2, "ptp", "clk1_tp")), 182 MPP_MODE(37, 183 MPP_FUNCTION(0, "gpio", NULL), 184 MPP_FUNCTION(1, "ptp", "pulse_tp"), 185 MPP_FUNCTION(2, "wd_int", NULL)), 186 MPP_MODE(38, 187 MPP_FUNCTION(0, "gpio", NULL), 188 MPP_FUNCTION(1, "synce", "clk_out0")), 189 MPP_MODE(39, 190 MPP_FUNCTION(0, "gpio", NULL), 191 MPP_FUNCTION(1, "synce", "clk_out1")), 192 MPP_MODE(40, 193 MPP_FUNCTION(0, "gpio", NULL), 194 MPP_FUNCTION(1, "ptp", "pclk_out0"), 195 MPP_FUNCTION(2, "ptp", "pclk_out1")), 196 MPP_MODE(41, 197 MPP_FUNCTION(0, "gpio", NULL), 198 MPP_FUNCTION(1, "ptp", "ref_clk"), 199 MPP_FUNCTION(2, "ptp", "clk1"), 200 MPP_FUNCTION(3, "ptp", "pulse"), 201 MPP_FUNCTION(4, "uart2", "txd"), 202 MPP_FUNCTION(5, "i2c1", "sck")), 203 MPP_MODE(42, 204 MPP_FUNCTION(0, "gpio", NULL), 205 MPP_FUNCTION(1, "ptp", "clk0"), 206 MPP_FUNCTION(2, "ptp", "clk1"), 207 MPP_FUNCTION(3, "ptp", "pulse"), 208 MPP_FUNCTION(4, "uart2", "rxd"), 209 MPP_FUNCTION(5, "i2c1", "sda")), 210 MPP_MODE(43, 211 MPP_FUNCTION(0, "gpio", NULL), 212 MPP_FUNCTION(1, "led", "clk")), 213 MPP_MODE(44, 214 MPP_FUNCTION(0, "gpio", NULL), 215 MPP_FUNCTION(1, "led", "stb")), 216 MPP_MODE(45, 217 MPP_FUNCTION(0, "gpio", NULL), 218 MPP_FUNCTION(1, "led", "data")), 219 }; 220 221 static struct mvebu_pinctrl_soc_info ac5_pinctrl_info; 222 223 static const struct of_device_id ac5_pinctrl_of_match[] = { 224 { 225 .compatible = "marvell,ac5-pinctrl", 226 }, 227 { }, 228 }; 229 230 static const struct mvebu_mpp_ctrl ac5_mpp_controls[] = { 231 MPP_FUNC_CTRL(0, 45, NULL, mvebu_mmio_mpp_ctrl), }; 232 233 static struct pinctrl_gpio_range ac5_mpp_gpio_ranges[] = { 234 MPP_GPIO_RANGE(0, 0, 0, 46), }; 235 236 static int ac5_pinctrl_probe(struct platform_device *pdev) 237 { 238 struct mvebu_pinctrl_soc_info *soc = &ac5_pinctrl_info; 239 240 soc->variant = 0; /* no variants for ac5 */ 241 soc->controls = ac5_mpp_controls; 242 soc->ncontrols = ARRAY_SIZE(ac5_mpp_controls); 243 soc->gpioranges = ac5_mpp_gpio_ranges; 244 soc->ngpioranges = ARRAY_SIZE(ac5_mpp_gpio_ranges); 245 soc->modes = ac5_mpp_modes; 246 soc->nmodes = ac5_mpp_controls[0].npins; 247 248 pdev->dev.platform_data = soc; 249 250 return mvebu_pinctrl_simple_mmio_probe(pdev); 251 } 252 253 static struct platform_driver ac5_pinctrl_driver = { 254 .driver = { 255 .name = "ac5-pinctrl", 256 .of_match_table = of_match_ptr(ac5_pinctrl_of_match), 257 }, 258 .probe = ac5_pinctrl_probe, 259 }; 260 builtin_platform_driver(ac5_pinctrl_driver); 261