1 /* 2 * Pin controller and GPIO driver for Amlogic Meson SoCs 3 * 4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * You should have received a copy of the GNU General Public License 11 * along with this program. If not, see <http://www.gnu.org/licenses/>. 12 */ 13 14 /* 15 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, 16 * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and 17 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a 18 * variable number of pins. 19 * 20 * The AO bank is special because it belongs to the Always-On power 21 * domain which can't be powered off; the bank also uses a set of 22 * registers different from the other banks. 23 * 24 * For each pin controller there are 4 different register ranges that 25 * control the following properties of the pins: 26 * 1) pin muxing 27 * 2) pull enable/disable 28 * 3) pull up/down 29 * 4) GPIO direction, output value, input value 30 * 31 * In some cases the register ranges for pull enable and pull 32 * direction are the same and thus there are only 3 register ranges. 33 * 34 * Since Meson G12A SoC, the ao register ranges for gpio, pull enable 35 * and pull direction are the same, so there are only 2 register ranges. 36 * 37 * For the pull and GPIO configuration every bank uses a contiguous 38 * set of bits in the register sets described above; the same register 39 * can be shared by more banks with different offsets. 40 * 41 * In addition to this there are some registers shared between all 42 * banks that control the IRQ functionality. This feature is not 43 * supported at the moment by the driver. 44 */ 45 46 #include <linux/device.h> 47 #include <linux/gpio/driver.h> 48 #include <linux/init.h> 49 #include <linux/io.h> 50 #include <linux/of.h> 51 #include <linux/of_address.h> 52 #include <linux/of_device.h> 53 #include <linux/pinctrl/pinconf-generic.h> 54 #include <linux/pinctrl/pinconf.h> 55 #include <linux/pinctrl/pinctrl.h> 56 #include <linux/pinctrl/pinmux.h> 57 #include <linux/platform_device.h> 58 #include <linux/regmap.h> 59 #include <linux/seq_file.h> 60 61 #include "../core.h" 62 #include "../pinctrl-utils.h" 63 #include "pinctrl-meson.h" 64 65 /** 66 * meson_get_bank() - find the bank containing a given pin 67 * 68 * @pc: the pinctrl instance 69 * @pin: the pin number 70 * @bank: the found bank 71 * 72 * Return: 0 on success, a negative value on error 73 */ 74 static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, 75 struct meson_bank **bank) 76 { 77 int i; 78 79 for (i = 0; i < pc->data->num_banks; i++) { 80 if (pin >= pc->data->banks[i].first && 81 pin <= pc->data->banks[i].last) { 82 *bank = &pc->data->banks[i]; 83 return 0; 84 } 85 } 86 87 return -EINVAL; 88 } 89 90 /** 91 * meson_calc_reg_and_bit() - calculate register and bit for a pin 92 * 93 * @bank: the bank containing the pin 94 * @pin: the pin number 95 * @reg_type: the type of register needed (pull-enable, pull, etc...) 96 * @reg: the computed register offset 97 * @bit: the computed bit 98 */ 99 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, 100 enum meson_reg_type reg_type, 101 unsigned int *reg, unsigned int *bit) 102 { 103 struct meson_reg_desc *desc = &bank->regs[reg_type]; 104 105 *reg = desc->reg * 4; 106 *bit = desc->bit + pin - bank->first; 107 } 108 109 static int meson_get_groups_count(struct pinctrl_dev *pcdev) 110 { 111 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 112 113 return pc->data->num_groups; 114 } 115 116 static const char *meson_get_group_name(struct pinctrl_dev *pcdev, 117 unsigned selector) 118 { 119 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 120 121 return pc->data->groups[selector].name; 122 } 123 124 static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, 125 const unsigned **pins, unsigned *num_pins) 126 { 127 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 128 129 *pins = pc->data->groups[selector].pins; 130 *num_pins = pc->data->groups[selector].num_pins; 131 132 return 0; 133 } 134 135 static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, 136 unsigned offset) 137 { 138 seq_printf(s, " %s", dev_name(pcdev->dev)); 139 } 140 141 static const struct pinctrl_ops meson_pctrl_ops = { 142 .get_groups_count = meson_get_groups_count, 143 .get_group_name = meson_get_group_name, 144 .get_group_pins = meson_get_group_pins, 145 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 146 .dt_free_map = pinctrl_utils_free_map, 147 .pin_dbg_show = meson_pin_dbg_show, 148 }; 149 150 int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) 151 { 152 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 153 154 return pc->data->num_funcs; 155 } 156 157 const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, 158 unsigned selector) 159 { 160 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 161 162 return pc->data->funcs[selector].name; 163 } 164 165 int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, 166 const char * const **groups, 167 unsigned * const num_groups) 168 { 169 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 170 171 *groups = pc->data->funcs[selector].groups; 172 *num_groups = pc->data->funcs[selector].num_groups; 173 174 return 0; 175 } 176 177 static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc, 178 unsigned int pin, 179 unsigned int reg_type, 180 bool arg) 181 { 182 struct meson_bank *bank; 183 unsigned int reg, bit; 184 int ret; 185 186 ret = meson_get_bank(pc, pin, &bank); 187 if (ret) 188 return ret; 189 190 meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); 191 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 192 arg ? BIT(bit) : 0); 193 } 194 195 static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc, 196 unsigned int pin, 197 unsigned int reg_type) 198 { 199 struct meson_bank *bank; 200 unsigned int reg, bit, val; 201 int ret; 202 203 ret = meson_get_bank(pc, pin, &bank); 204 if (ret) 205 return ret; 206 207 meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); 208 ret = regmap_read(pc->reg_gpio, reg, &val); 209 if (ret) 210 return ret; 211 212 return BIT(bit) & val ? 1 : 0; 213 } 214 215 static int meson_pinconf_set_output(struct meson_pinctrl *pc, 216 unsigned int pin, 217 bool out) 218 { 219 return meson_pinconf_set_gpio_bit(pc, pin, REG_DIR, !out); 220 } 221 222 static int meson_pinconf_get_output(struct meson_pinctrl *pc, 223 unsigned int pin) 224 { 225 int ret = meson_pinconf_get_gpio_bit(pc, pin, REG_DIR); 226 227 if (ret < 0) 228 return ret; 229 230 return !ret; 231 } 232 233 static int meson_pinconf_set_drive(struct meson_pinctrl *pc, 234 unsigned int pin, 235 bool high) 236 { 237 return meson_pinconf_set_gpio_bit(pc, pin, REG_OUT, high); 238 } 239 240 static int meson_pinconf_get_drive(struct meson_pinctrl *pc, 241 unsigned int pin) 242 { 243 return meson_pinconf_get_gpio_bit(pc, pin, REG_OUT); 244 } 245 246 static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc, 247 unsigned int pin, 248 bool high) 249 { 250 int ret; 251 252 ret = meson_pinconf_set_output(pc, pin, true); 253 if (ret) 254 return ret; 255 256 return meson_pinconf_set_drive(pc, pin, high); 257 } 258 259 static int meson_pinconf_disable_bias(struct meson_pinctrl *pc, 260 unsigned int pin) 261 { 262 struct meson_bank *bank; 263 unsigned int reg, bit = 0; 264 int ret; 265 266 ret = meson_get_bank(pc, pin, &bank); 267 if (ret) 268 return ret; 269 270 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 271 ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0); 272 if (ret) 273 return ret; 274 275 return 0; 276 } 277 278 static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin, 279 bool pull_up) 280 { 281 struct meson_bank *bank; 282 unsigned int reg, bit, val = 0; 283 int ret; 284 285 ret = meson_get_bank(pc, pin, &bank); 286 if (ret) 287 return ret; 288 289 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 290 if (pull_up) 291 val = BIT(bit); 292 293 ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val); 294 if (ret) 295 return ret; 296 297 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 298 ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit)); 299 if (ret) 300 return ret; 301 302 return 0; 303 } 304 305 static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc, 306 unsigned int pin, 307 u16 drive_strength_ua) 308 { 309 struct meson_bank *bank; 310 unsigned int reg, bit, ds_val; 311 int ret; 312 313 if (!pc->reg_ds) { 314 dev_err(pc->dev, "drive-strength not supported\n"); 315 return -ENOTSUPP; 316 } 317 318 ret = meson_get_bank(pc, pin, &bank); 319 if (ret) 320 return ret; 321 322 meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); 323 bit = bit << 1; 324 325 if (drive_strength_ua <= 500) { 326 ds_val = MESON_PINCONF_DRV_500UA; 327 } else if (drive_strength_ua <= 2500) { 328 ds_val = MESON_PINCONF_DRV_2500UA; 329 } else if (drive_strength_ua <= 3000) { 330 ds_val = MESON_PINCONF_DRV_3000UA; 331 } else if (drive_strength_ua <= 4000) { 332 ds_val = MESON_PINCONF_DRV_4000UA; 333 } else { 334 dev_warn_once(pc->dev, 335 "pin %u: invalid drive-strength : %d , default to 4mA\n", 336 pin, drive_strength_ua); 337 ds_val = MESON_PINCONF_DRV_4000UA; 338 } 339 340 ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit); 341 if (ret) 342 return ret; 343 344 return 0; 345 } 346 347 static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, 348 unsigned long *configs, unsigned num_configs) 349 { 350 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 351 enum pin_config_param param; 352 unsigned int arg = 0; 353 int i, ret; 354 355 for (i = 0; i < num_configs; i++) { 356 param = pinconf_to_config_param(configs[i]); 357 358 switch (param) { 359 case PIN_CONFIG_DRIVE_STRENGTH_UA: 360 case PIN_CONFIG_OUTPUT_ENABLE: 361 case PIN_CONFIG_OUTPUT: 362 arg = pinconf_to_config_argument(configs[i]); 363 break; 364 365 default: 366 break; 367 } 368 369 switch (param) { 370 case PIN_CONFIG_BIAS_DISABLE: 371 ret = meson_pinconf_disable_bias(pc, pin); 372 break; 373 case PIN_CONFIG_BIAS_PULL_UP: 374 ret = meson_pinconf_enable_bias(pc, pin, true); 375 break; 376 case PIN_CONFIG_BIAS_PULL_DOWN: 377 ret = meson_pinconf_enable_bias(pc, pin, false); 378 break; 379 case PIN_CONFIG_DRIVE_STRENGTH_UA: 380 ret = meson_pinconf_set_drive_strength(pc, pin, arg); 381 break; 382 case PIN_CONFIG_OUTPUT_ENABLE: 383 ret = meson_pinconf_set_output(pc, pin, arg); 384 break; 385 case PIN_CONFIG_OUTPUT: 386 ret = meson_pinconf_set_output_drive(pc, pin, arg); 387 break; 388 default: 389 ret = -ENOTSUPP; 390 } 391 392 if (ret) 393 return ret; 394 } 395 396 return 0; 397 } 398 399 static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) 400 { 401 struct meson_bank *bank; 402 unsigned int reg, bit, val; 403 int ret, conf; 404 405 ret = meson_get_bank(pc, pin, &bank); 406 if (ret) 407 return ret; 408 409 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 410 411 ret = regmap_read(pc->reg_pullen, reg, &val); 412 if (ret) 413 return ret; 414 415 if (!(val & BIT(bit))) { 416 conf = PIN_CONFIG_BIAS_DISABLE; 417 } else { 418 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 419 420 ret = regmap_read(pc->reg_pull, reg, &val); 421 if (ret) 422 return ret; 423 424 if (val & BIT(bit)) 425 conf = PIN_CONFIG_BIAS_PULL_UP; 426 else 427 conf = PIN_CONFIG_BIAS_PULL_DOWN; 428 } 429 430 return conf; 431 } 432 433 static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc, 434 unsigned int pin, 435 u16 *drive_strength_ua) 436 { 437 struct meson_bank *bank; 438 unsigned int reg, bit; 439 unsigned int val; 440 int ret; 441 442 if (!pc->reg_ds) 443 return -ENOTSUPP; 444 445 ret = meson_get_bank(pc, pin, &bank); 446 if (ret) 447 return ret; 448 449 meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); 450 451 ret = regmap_read(pc->reg_ds, reg, &val); 452 if (ret) 453 return ret; 454 455 switch ((val >> bit) & 0x3) { 456 case MESON_PINCONF_DRV_500UA: 457 *drive_strength_ua = 500; 458 break; 459 case MESON_PINCONF_DRV_2500UA: 460 *drive_strength_ua = 2500; 461 break; 462 case MESON_PINCONF_DRV_3000UA: 463 *drive_strength_ua = 3000; 464 break; 465 case MESON_PINCONF_DRV_4000UA: 466 *drive_strength_ua = 4000; 467 break; 468 default: 469 return -EINVAL; 470 } 471 472 return 0; 473 } 474 475 static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, 476 unsigned long *config) 477 { 478 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 479 enum pin_config_param param = pinconf_to_config_param(*config); 480 u16 arg; 481 int ret; 482 483 switch (param) { 484 case PIN_CONFIG_BIAS_DISABLE: 485 case PIN_CONFIG_BIAS_PULL_DOWN: 486 case PIN_CONFIG_BIAS_PULL_UP: 487 if (meson_pinconf_get_pull(pc, pin) == param) 488 arg = 1; 489 else 490 return -EINVAL; 491 break; 492 case PIN_CONFIG_DRIVE_STRENGTH_UA: 493 ret = meson_pinconf_get_drive_strength(pc, pin, &arg); 494 if (ret) 495 return ret; 496 break; 497 case PIN_CONFIG_OUTPUT_ENABLE: 498 ret = meson_pinconf_get_output(pc, pin); 499 if (ret <= 0) 500 return -EINVAL; 501 arg = 1; 502 break; 503 case PIN_CONFIG_OUTPUT: 504 ret = meson_pinconf_get_output(pc, pin); 505 if (ret <= 0) 506 return -EINVAL; 507 508 ret = meson_pinconf_get_drive(pc, pin); 509 if (ret < 0) 510 return -EINVAL; 511 512 arg = ret; 513 break; 514 515 default: 516 return -ENOTSUPP; 517 } 518 519 *config = pinconf_to_config_packed(param, arg); 520 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); 521 522 return 0; 523 } 524 525 static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, 526 unsigned int num_group, 527 unsigned long *configs, unsigned num_configs) 528 { 529 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 530 struct meson_pmx_group *group = &pc->data->groups[num_group]; 531 int i; 532 533 dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); 534 535 for (i = 0; i < group->num_pins; i++) { 536 meson_pinconf_set(pcdev, group->pins[i], configs, 537 num_configs); 538 } 539 540 return 0; 541 } 542 543 static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, 544 unsigned int group, unsigned long *config) 545 { 546 return -ENOTSUPP; 547 } 548 549 static const struct pinconf_ops meson_pinconf_ops = { 550 .pin_config_get = meson_pinconf_get, 551 .pin_config_set = meson_pinconf_set, 552 .pin_config_group_get = meson_pinconf_group_get, 553 .pin_config_group_set = meson_pinconf_group_set, 554 .is_generic = true, 555 }; 556 557 static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 558 { 559 return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false); 560 } 561 562 static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 563 int value) 564 { 565 return meson_pinconf_set_output_drive(gpiochip_get_data(chip), 566 gpio, value); 567 } 568 569 static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) 570 { 571 meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value); 572 } 573 574 static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) 575 { 576 struct meson_pinctrl *pc = gpiochip_get_data(chip); 577 unsigned int reg, bit, val; 578 struct meson_bank *bank; 579 int ret; 580 581 ret = meson_get_bank(pc, gpio, &bank); 582 if (ret) 583 return ret; 584 585 meson_calc_reg_and_bit(bank, gpio, REG_IN, ®, &bit); 586 regmap_read(pc->reg_gpio, reg, &val); 587 588 return !!(val & BIT(bit)); 589 } 590 591 static int meson_gpiolib_register(struct meson_pinctrl *pc) 592 { 593 int ret; 594 595 pc->chip.label = pc->data->name; 596 pc->chip.parent = pc->dev; 597 pc->chip.request = gpiochip_generic_request; 598 pc->chip.free = gpiochip_generic_free; 599 pc->chip.direction_input = meson_gpio_direction_input; 600 pc->chip.direction_output = meson_gpio_direction_output; 601 pc->chip.get = meson_gpio_get; 602 pc->chip.set = meson_gpio_set; 603 pc->chip.base = -1; 604 pc->chip.ngpio = pc->data->num_pins; 605 pc->chip.can_sleep = false; 606 pc->chip.of_node = pc->of_node; 607 pc->chip.of_gpio_n_cells = 2; 608 609 ret = gpiochip_add_data(&pc->chip, pc); 610 if (ret) { 611 dev_err(pc->dev, "can't add gpio chip %s\n", 612 pc->data->name); 613 return ret; 614 } 615 616 return 0; 617 } 618 619 static struct regmap_config meson_regmap_config = { 620 .reg_bits = 32, 621 .val_bits = 32, 622 .reg_stride = 4, 623 }; 624 625 static struct regmap *meson_map_resource(struct meson_pinctrl *pc, 626 struct device_node *node, char *name) 627 { 628 struct resource res; 629 void __iomem *base; 630 int i; 631 632 i = of_property_match_string(node, "reg-names", name); 633 if (of_address_to_resource(node, i, &res)) 634 return ERR_PTR(-ENOENT); 635 636 base = devm_ioremap_resource(pc->dev, &res); 637 if (IS_ERR(base)) 638 return ERR_CAST(base); 639 640 meson_regmap_config.max_register = resource_size(&res) - 4; 641 meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, 642 "%pOFn-%s", node, 643 name); 644 if (!meson_regmap_config.name) 645 return ERR_PTR(-ENOMEM); 646 647 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); 648 } 649 650 static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, 651 struct device_node *node) 652 { 653 struct device_node *np, *gpio_np = NULL; 654 655 for_each_child_of_node(node, np) { 656 if (!of_find_property(np, "gpio-controller", NULL)) 657 continue; 658 if (gpio_np) { 659 dev_err(pc->dev, "multiple gpio nodes\n"); 660 return -EINVAL; 661 } 662 gpio_np = np; 663 } 664 665 if (!gpio_np) { 666 dev_err(pc->dev, "no gpio node found\n"); 667 return -EINVAL; 668 } 669 670 pc->of_node = gpio_np; 671 672 pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); 673 if (IS_ERR(pc->reg_mux)) { 674 dev_err(pc->dev, "mux registers not found\n"); 675 return PTR_ERR(pc->reg_mux); 676 } 677 678 pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio"); 679 if (IS_ERR(pc->reg_gpio)) { 680 dev_err(pc->dev, "gpio registers not found\n"); 681 return PTR_ERR(pc->reg_gpio); 682 } 683 684 pc->reg_pull = meson_map_resource(pc, gpio_np, "pull"); 685 /* Use gpio region if pull one is not present */ 686 if (IS_ERR(pc->reg_pull)) 687 pc->reg_pull = pc->reg_gpio; 688 689 pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable"); 690 /* Use pull region if pull-enable one is not present */ 691 if (IS_ERR(pc->reg_pullen)) 692 pc->reg_pullen = pc->reg_pull; 693 694 pc->reg_ds = meson_map_resource(pc, gpio_np, "ds"); 695 if (IS_ERR(pc->reg_ds)) { 696 dev_dbg(pc->dev, "ds registers not found - skipping\n"); 697 pc->reg_ds = NULL; 698 } 699 700 return 0; 701 } 702 703 int meson_pinctrl_probe(struct platform_device *pdev) 704 { 705 struct device *dev = &pdev->dev; 706 struct meson_pinctrl *pc; 707 int ret; 708 709 pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); 710 if (!pc) 711 return -ENOMEM; 712 713 pc->dev = dev; 714 pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev); 715 716 ret = meson_pinctrl_parse_dt(pc, dev->of_node); 717 if (ret) 718 return ret; 719 720 pc->desc.name = "pinctrl-meson"; 721 pc->desc.owner = THIS_MODULE; 722 pc->desc.pctlops = &meson_pctrl_ops; 723 pc->desc.pmxops = pc->data->pmx_ops; 724 pc->desc.confops = &meson_pinconf_ops; 725 pc->desc.pins = pc->data->pins; 726 pc->desc.npins = pc->data->num_pins; 727 728 pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc); 729 if (IS_ERR(pc->pcdev)) { 730 dev_err(pc->dev, "can't register pinctrl device"); 731 return PTR_ERR(pc->pcdev); 732 } 733 734 return meson_gpiolib_register(pc); 735 } 736