1 /* 2 * Pin controller and GPIO driver for Amlogic Meson SoCs 3 * 4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * You should have received a copy of the GNU General Public License 11 * along with this program. If not, see <http://www.gnu.org/licenses/>. 12 */ 13 14 /* 15 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, 16 * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and 17 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a 18 * variable number of pins. 19 * 20 * The AO bank is special because it belongs to the Always-On power 21 * domain which can't be powered off; the bank also uses a set of 22 * registers different from the other banks. 23 * 24 * For each pin controller there are 4 different register ranges that 25 * control the following properties of the pins: 26 * 1) pin muxing 27 * 2) pull enable/disable 28 * 3) pull up/down 29 * 4) GPIO direction, output value, input value 30 * 31 * In some cases the register ranges for pull enable and pull 32 * direction are the same and thus there are only 3 register ranges. 33 * 34 * Since Meson G12A SoC, the ao register ranges for gpio, pull enable 35 * and pull direction are the same, so there are only 2 register ranges. 36 * 37 * For the pull and GPIO configuration every bank uses a contiguous 38 * set of bits in the register sets described above; the same register 39 * can be shared by more banks with different offsets. 40 * 41 * In addition to this there are some registers shared between all 42 * banks that control the IRQ functionality. This feature is not 43 * supported at the moment by the driver. 44 */ 45 46 #include <linux/device.h> 47 #include <linux/gpio/driver.h> 48 #include <linux/init.h> 49 #include <linux/io.h> 50 #include <linux/of.h> 51 #include <linux/of_address.h> 52 #include <linux/of_device.h> 53 #include <linux/pinctrl/pinconf-generic.h> 54 #include <linux/pinctrl/pinconf.h> 55 #include <linux/pinctrl/pinctrl.h> 56 #include <linux/pinctrl/pinmux.h> 57 #include <linux/platform_device.h> 58 #include <linux/regmap.h> 59 #include <linux/seq_file.h> 60 61 #include "../core.h" 62 #include "../pinctrl-utils.h" 63 #include "pinctrl-meson.h" 64 65 /** 66 * meson_get_bank() - find the bank containing a given pin 67 * 68 * @pc: the pinctrl instance 69 * @pin: the pin number 70 * @bank: the found bank 71 * 72 * Return: 0 on success, a negative value on error 73 */ 74 static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, 75 struct meson_bank **bank) 76 { 77 int i; 78 79 for (i = 0; i < pc->data->num_banks; i++) { 80 if (pin >= pc->data->banks[i].first && 81 pin <= pc->data->banks[i].last) { 82 *bank = &pc->data->banks[i]; 83 return 0; 84 } 85 } 86 87 return -EINVAL; 88 } 89 90 /** 91 * meson_calc_reg_and_bit() - calculate register and bit for a pin 92 * 93 * @bank: the bank containing the pin 94 * @pin: the pin number 95 * @reg_type: the type of register needed (pull-enable, pull, etc...) 96 * @reg: the computed register offset 97 * @bit: the computed bit 98 */ 99 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, 100 enum meson_reg_type reg_type, 101 unsigned int *reg, unsigned int *bit) 102 { 103 struct meson_reg_desc *desc = &bank->regs[reg_type]; 104 105 *reg = desc->reg * 4; 106 *bit = desc->bit + pin - bank->first; 107 } 108 109 static int meson_get_groups_count(struct pinctrl_dev *pcdev) 110 { 111 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 112 113 return pc->data->num_groups; 114 } 115 116 static const char *meson_get_group_name(struct pinctrl_dev *pcdev, 117 unsigned selector) 118 { 119 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 120 121 return pc->data->groups[selector].name; 122 } 123 124 static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, 125 const unsigned **pins, unsigned *num_pins) 126 { 127 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 128 129 *pins = pc->data->groups[selector].pins; 130 *num_pins = pc->data->groups[selector].num_pins; 131 132 return 0; 133 } 134 135 static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, 136 unsigned offset) 137 { 138 seq_printf(s, " %s", dev_name(pcdev->dev)); 139 } 140 141 static const struct pinctrl_ops meson_pctrl_ops = { 142 .get_groups_count = meson_get_groups_count, 143 .get_group_name = meson_get_group_name, 144 .get_group_pins = meson_get_group_pins, 145 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 146 .dt_free_map = pinctrl_utils_free_map, 147 .pin_dbg_show = meson_pin_dbg_show, 148 }; 149 150 int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) 151 { 152 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 153 154 return pc->data->num_funcs; 155 } 156 157 const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, 158 unsigned selector) 159 { 160 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 161 162 return pc->data->funcs[selector].name; 163 } 164 165 int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, 166 const char * const **groups, 167 unsigned * const num_groups) 168 { 169 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 170 171 *groups = pc->data->funcs[selector].groups; 172 *num_groups = pc->data->funcs[selector].num_groups; 173 174 return 0; 175 } 176 177 static int meson_pinconf_disable_bias(struct meson_pinctrl *pc, 178 unsigned int pin) 179 { 180 struct meson_bank *bank; 181 unsigned int reg, bit = 0; 182 int ret; 183 184 ret = meson_get_bank(pc, pin, &bank); 185 if (ret) 186 return ret; 187 188 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 189 ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0); 190 if (ret) 191 return ret; 192 193 return 0; 194 } 195 196 static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin, 197 bool pull_up) 198 { 199 struct meson_bank *bank; 200 unsigned int reg, bit, val = 0; 201 int ret; 202 203 ret = meson_get_bank(pc, pin, &bank); 204 if (ret) 205 return ret; 206 207 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 208 if (pull_up) 209 val = BIT(bit); 210 211 ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val); 212 if (ret) 213 return ret; 214 215 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 216 ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit)); 217 if (ret) 218 return ret; 219 220 return 0; 221 } 222 223 static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, 224 unsigned long *configs, unsigned num_configs) 225 { 226 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 227 enum pin_config_param param; 228 int i, ret; 229 230 for (i = 0; i < num_configs; i++) { 231 param = pinconf_to_config_param(configs[i]); 232 233 switch (param) { 234 case PIN_CONFIG_BIAS_DISABLE: 235 ret = meson_pinconf_disable_bias(pc, pin); 236 if (ret) 237 return ret; 238 break; 239 case PIN_CONFIG_BIAS_PULL_UP: 240 ret = meson_pinconf_enable_bias(pc, pin, true); 241 if (ret) 242 return ret; 243 break; 244 case PIN_CONFIG_BIAS_PULL_DOWN: 245 ret = meson_pinconf_enable_bias(pc, pin, false); 246 if (ret) 247 return ret; 248 break; 249 default: 250 return -ENOTSUPP; 251 } 252 } 253 254 return 0; 255 } 256 257 static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) 258 { 259 struct meson_bank *bank; 260 unsigned int reg, bit, val; 261 int ret, conf; 262 263 ret = meson_get_bank(pc, pin, &bank); 264 if (ret) 265 return ret; 266 267 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 268 269 ret = regmap_read(pc->reg_pullen, reg, &val); 270 if (ret) 271 return ret; 272 273 if (!(val & BIT(bit))) { 274 conf = PIN_CONFIG_BIAS_DISABLE; 275 } else { 276 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 277 278 ret = regmap_read(pc->reg_pull, reg, &val); 279 if (ret) 280 return ret; 281 282 if (val & BIT(bit)) 283 conf = PIN_CONFIG_BIAS_PULL_UP; 284 else 285 conf = PIN_CONFIG_BIAS_PULL_DOWN; 286 } 287 288 return conf; 289 } 290 291 static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, 292 unsigned long *config) 293 { 294 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 295 enum pin_config_param param = pinconf_to_config_param(*config); 296 u16 arg; 297 298 switch (param) { 299 case PIN_CONFIG_BIAS_DISABLE: 300 case PIN_CONFIG_BIAS_PULL_DOWN: 301 case PIN_CONFIG_BIAS_PULL_UP: 302 if (meson_pinconf_get_pull(pc, pin) == param) 303 arg = 1; 304 else 305 return -EINVAL; 306 break; 307 default: 308 return -ENOTSUPP; 309 } 310 311 *config = pinconf_to_config_packed(param, arg); 312 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); 313 314 return 0; 315 } 316 317 static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, 318 unsigned int num_group, 319 unsigned long *configs, unsigned num_configs) 320 { 321 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 322 struct meson_pmx_group *group = &pc->data->groups[num_group]; 323 int i; 324 325 dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); 326 327 for (i = 0; i < group->num_pins; i++) { 328 meson_pinconf_set(pcdev, group->pins[i], configs, 329 num_configs); 330 } 331 332 return 0; 333 } 334 335 static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, 336 unsigned int group, unsigned long *config) 337 { 338 return -ENOTSUPP; 339 } 340 341 static const struct pinconf_ops meson_pinconf_ops = { 342 .pin_config_get = meson_pinconf_get, 343 .pin_config_set = meson_pinconf_set, 344 .pin_config_group_get = meson_pinconf_group_get, 345 .pin_config_group_set = meson_pinconf_group_set, 346 .is_generic = true, 347 }; 348 349 static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 350 { 351 struct meson_pinctrl *pc = gpiochip_get_data(chip); 352 unsigned int reg, bit; 353 struct meson_bank *bank; 354 int ret; 355 356 ret = meson_get_bank(pc, gpio, &bank); 357 if (ret) 358 return ret; 359 360 meson_calc_reg_and_bit(bank, gpio, REG_DIR, ®, &bit); 361 362 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit)); 363 } 364 365 static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 366 int value) 367 { 368 struct meson_pinctrl *pc = gpiochip_get_data(chip); 369 unsigned int reg, bit; 370 struct meson_bank *bank; 371 int ret; 372 373 ret = meson_get_bank(pc, gpio, &bank); 374 if (ret) 375 return ret; 376 377 meson_calc_reg_and_bit(bank, gpio, REG_DIR, ®, &bit); 378 ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0); 379 if (ret) 380 return ret; 381 382 meson_calc_reg_and_bit(bank, gpio, REG_OUT, ®, &bit); 383 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 384 value ? BIT(bit) : 0); 385 } 386 387 static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) 388 { 389 struct meson_pinctrl *pc = gpiochip_get_data(chip); 390 unsigned int reg, bit; 391 struct meson_bank *bank; 392 int ret; 393 394 ret = meson_get_bank(pc, gpio, &bank); 395 if (ret) 396 return; 397 398 meson_calc_reg_and_bit(bank, gpio, REG_OUT, ®, &bit); 399 regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 400 value ? BIT(bit) : 0); 401 } 402 403 static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) 404 { 405 struct meson_pinctrl *pc = gpiochip_get_data(chip); 406 unsigned int reg, bit, val; 407 struct meson_bank *bank; 408 int ret; 409 410 ret = meson_get_bank(pc, gpio, &bank); 411 if (ret) 412 return ret; 413 414 meson_calc_reg_and_bit(bank, gpio, REG_IN, ®, &bit); 415 regmap_read(pc->reg_gpio, reg, &val); 416 417 return !!(val & BIT(bit)); 418 } 419 420 static int meson_gpiolib_register(struct meson_pinctrl *pc) 421 { 422 int ret; 423 424 pc->chip.label = pc->data->name; 425 pc->chip.parent = pc->dev; 426 pc->chip.request = gpiochip_generic_request; 427 pc->chip.free = gpiochip_generic_free; 428 pc->chip.direction_input = meson_gpio_direction_input; 429 pc->chip.direction_output = meson_gpio_direction_output; 430 pc->chip.get = meson_gpio_get; 431 pc->chip.set = meson_gpio_set; 432 pc->chip.base = -1; 433 pc->chip.ngpio = pc->data->num_pins; 434 pc->chip.can_sleep = false; 435 pc->chip.of_node = pc->of_node; 436 pc->chip.of_gpio_n_cells = 2; 437 438 ret = gpiochip_add_data(&pc->chip, pc); 439 if (ret) { 440 dev_err(pc->dev, "can't add gpio chip %s\n", 441 pc->data->name); 442 return ret; 443 } 444 445 return 0; 446 } 447 448 static struct regmap_config meson_regmap_config = { 449 .reg_bits = 32, 450 .val_bits = 32, 451 .reg_stride = 4, 452 }; 453 454 static struct regmap *meson_map_resource(struct meson_pinctrl *pc, 455 struct device_node *node, char *name) 456 { 457 struct resource res; 458 void __iomem *base; 459 int i; 460 461 i = of_property_match_string(node, "reg-names", name); 462 if (of_address_to_resource(node, i, &res)) 463 return ERR_PTR(-ENOENT); 464 465 base = devm_ioremap_resource(pc->dev, &res); 466 if (IS_ERR(base)) 467 return ERR_CAST(base); 468 469 meson_regmap_config.max_register = resource_size(&res) - 4; 470 meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, 471 "%pOFn-%s", node, 472 name); 473 if (!meson_regmap_config.name) 474 return ERR_PTR(-ENOMEM); 475 476 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); 477 } 478 479 static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, 480 struct device_node *node) 481 { 482 struct device_node *np, *gpio_np = NULL; 483 484 for_each_child_of_node(node, np) { 485 if (!of_find_property(np, "gpio-controller", NULL)) 486 continue; 487 if (gpio_np) { 488 dev_err(pc->dev, "multiple gpio nodes\n"); 489 return -EINVAL; 490 } 491 gpio_np = np; 492 } 493 494 if (!gpio_np) { 495 dev_err(pc->dev, "no gpio node found\n"); 496 return -EINVAL; 497 } 498 499 pc->of_node = gpio_np; 500 501 pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); 502 if (IS_ERR(pc->reg_mux)) { 503 dev_err(pc->dev, "mux registers not found\n"); 504 return PTR_ERR(pc->reg_mux); 505 } 506 507 pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio"); 508 if (IS_ERR(pc->reg_gpio)) { 509 dev_err(pc->dev, "gpio registers not found\n"); 510 return PTR_ERR(pc->reg_gpio); 511 } 512 513 pc->reg_pull = meson_map_resource(pc, gpio_np, "pull"); 514 /* Use gpio region if pull one is not present */ 515 if (IS_ERR(pc->reg_pull)) 516 pc->reg_pull = pc->reg_gpio; 517 518 pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable"); 519 /* Use pull region if pull-enable one is not present */ 520 if (IS_ERR(pc->reg_pullen)) 521 pc->reg_pullen = pc->reg_pull; 522 523 pc->reg_ds = meson_map_resource(pc, gpio_np, "ds"); 524 if (IS_ERR(pc->reg_ds)) { 525 dev_dbg(pc->dev, "ds registers not found - skipping\n"); 526 pc->reg_ds = NULL; 527 } 528 529 return 0; 530 } 531 532 int meson_pinctrl_probe(struct platform_device *pdev) 533 { 534 struct device *dev = &pdev->dev; 535 struct meson_pinctrl *pc; 536 int ret; 537 538 pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); 539 if (!pc) 540 return -ENOMEM; 541 542 pc->dev = dev; 543 pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev); 544 545 ret = meson_pinctrl_parse_dt(pc, dev->of_node); 546 if (ret) 547 return ret; 548 549 pc->desc.name = "pinctrl-meson"; 550 pc->desc.owner = THIS_MODULE; 551 pc->desc.pctlops = &meson_pctrl_ops; 552 pc->desc.pmxops = pc->data->pmx_ops; 553 pc->desc.confops = &meson_pinconf_ops; 554 pc->desc.pins = pc->data->pins; 555 pc->desc.npins = pc->data->num_pins; 556 557 pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc); 558 if (IS_ERR(pc->pcdev)) { 559 dev_err(pc->dev, "can't register pinctrl device"); 560 return PTR_ERR(pc->pcdev); 561 } 562 563 return meson_gpiolib_register(pc); 564 } 565