1 /* 2 * Pin controller and GPIO driver for Amlogic Meson SoCs 3 * 4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * You should have received a copy of the GNU General Public License 11 * along with this program. If not, see <http://www.gnu.org/licenses/>. 12 */ 13 14 /* 15 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, 16 * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and 17 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a 18 * variable number of pins. 19 * 20 * The AO bank is special because it belongs to the Always-On power 21 * domain which can't be powered off; the bank also uses a set of 22 * registers different from the other banks. 23 * 24 * For each pin controller there are 4 different register ranges that 25 * control the following properties of the pins: 26 * 1) pin muxing 27 * 2) pull enable/disable 28 * 3) pull up/down 29 * 4) GPIO direction, output value, input value 30 * 31 * In some cases the register ranges for pull enable and pull 32 * direction are the same and thus there are only 3 register ranges. 33 * 34 * Since Meson G12A SoC, the ao register ranges for gpio, pull enable 35 * and pull direction are the same, so there are only 2 register ranges. 36 * 37 * For the pull and GPIO configuration every bank uses a contiguous 38 * set of bits in the register sets described above; the same register 39 * can be shared by more banks with different offsets. 40 * 41 * In addition to this there are some registers shared between all 42 * banks that control the IRQ functionality. This feature is not 43 * supported at the moment by the driver. 44 */ 45 46 #include <linux/device.h> 47 #include <linux/gpio/driver.h> 48 #include <linux/init.h> 49 #include <linux/io.h> 50 #include <linux/of.h> 51 #include <linux/of_address.h> 52 #include <linux/of_device.h> 53 #include <linux/pinctrl/pinconf-generic.h> 54 #include <linux/pinctrl/pinconf.h> 55 #include <linux/pinctrl/pinctrl.h> 56 #include <linux/pinctrl/pinmux.h> 57 #include <linux/platform_device.h> 58 #include <linux/regmap.h> 59 #include <linux/seq_file.h> 60 61 #include "../core.h" 62 #include "../pinctrl-utils.h" 63 #include "pinctrl-meson.h" 64 65 /** 66 * meson_get_bank() - find the bank containing a given pin 67 * 68 * @pc: the pinctrl instance 69 * @pin: the pin number 70 * @bank: the found bank 71 * 72 * Return: 0 on success, a negative value on error 73 */ 74 static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, 75 struct meson_bank **bank) 76 { 77 int i; 78 79 for (i = 0; i < pc->data->num_banks; i++) { 80 if (pin >= pc->data->banks[i].first && 81 pin <= pc->data->banks[i].last) { 82 *bank = &pc->data->banks[i]; 83 return 0; 84 } 85 } 86 87 return -EINVAL; 88 } 89 90 /** 91 * meson_calc_reg_and_bit() - calculate register and bit for a pin 92 * 93 * @bank: the bank containing the pin 94 * @pin: the pin number 95 * @reg_type: the type of register needed (pull-enable, pull, etc...) 96 * @reg: the computed register offset 97 * @bit: the computed bit 98 */ 99 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, 100 enum meson_reg_type reg_type, 101 unsigned int *reg, unsigned int *bit) 102 { 103 struct meson_reg_desc *desc = &bank->regs[reg_type]; 104 105 *reg = desc->reg * 4; 106 *bit = desc->bit + pin - bank->first; 107 } 108 109 static int meson_get_groups_count(struct pinctrl_dev *pcdev) 110 { 111 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 112 113 return pc->data->num_groups; 114 } 115 116 static const char *meson_get_group_name(struct pinctrl_dev *pcdev, 117 unsigned selector) 118 { 119 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 120 121 return pc->data->groups[selector].name; 122 } 123 124 static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, 125 const unsigned **pins, unsigned *num_pins) 126 { 127 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 128 129 *pins = pc->data->groups[selector].pins; 130 *num_pins = pc->data->groups[selector].num_pins; 131 132 return 0; 133 } 134 135 static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, 136 unsigned offset) 137 { 138 seq_printf(s, " %s", dev_name(pcdev->dev)); 139 } 140 141 static const struct pinctrl_ops meson_pctrl_ops = { 142 .get_groups_count = meson_get_groups_count, 143 .get_group_name = meson_get_group_name, 144 .get_group_pins = meson_get_group_pins, 145 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 146 .dt_free_map = pinctrl_utils_free_map, 147 .pin_dbg_show = meson_pin_dbg_show, 148 }; 149 150 int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) 151 { 152 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 153 154 return pc->data->num_funcs; 155 } 156 157 const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, 158 unsigned selector) 159 { 160 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 161 162 return pc->data->funcs[selector].name; 163 } 164 165 int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, 166 const char * const **groups, 167 unsigned * const num_groups) 168 { 169 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 170 171 *groups = pc->data->funcs[selector].groups; 172 *num_groups = pc->data->funcs[selector].num_groups; 173 174 return 0; 175 } 176 177 static int meson_pinconf_disable_bias(struct meson_pinctrl *pc, 178 unsigned int pin) 179 { 180 struct meson_bank *bank; 181 unsigned int reg, bit = 0; 182 int ret; 183 184 ret = meson_get_bank(pc, pin, &bank); 185 if (ret) 186 return ret; 187 188 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 189 ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0); 190 if (ret) 191 return ret; 192 193 return 0; 194 } 195 196 static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin, 197 bool pull_up) 198 { 199 struct meson_bank *bank; 200 unsigned int reg, bit, val = 0; 201 int ret; 202 203 ret = meson_get_bank(pc, pin, &bank); 204 if (ret) 205 return ret; 206 207 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 208 if (pull_up) 209 val = BIT(bit); 210 211 ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val); 212 if (ret) 213 return ret; 214 215 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 216 ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit)); 217 if (ret) 218 return ret; 219 220 return 0; 221 } 222 223 static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc, 224 unsigned int pin, 225 u16 drive_strength_ua) 226 { 227 struct meson_bank *bank; 228 unsigned int reg, bit, ds_val; 229 int ret; 230 231 if (!pc->reg_ds) { 232 dev_err(pc->dev, "drive-strength not supported\n"); 233 return -ENOTSUPP; 234 } 235 236 ret = meson_get_bank(pc, pin, &bank); 237 if (ret) 238 return ret; 239 240 meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); 241 bit = bit << 1; 242 243 if (drive_strength_ua <= 500) { 244 ds_val = MESON_PINCONF_DRV_500UA; 245 } else if (drive_strength_ua <= 2500) { 246 ds_val = MESON_PINCONF_DRV_2500UA; 247 } else if (drive_strength_ua <= 3000) { 248 ds_val = MESON_PINCONF_DRV_3000UA; 249 } else if (drive_strength_ua <= 4000) { 250 ds_val = MESON_PINCONF_DRV_4000UA; 251 } else { 252 dev_warn_once(pc->dev, 253 "pin %u: invalid drive-strength : %d , default to 4mA\n", 254 pin, drive_strength_ua); 255 ds_val = MESON_PINCONF_DRV_4000UA; 256 } 257 258 ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit); 259 if (ret) 260 return ret; 261 262 return 0; 263 } 264 265 static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, 266 unsigned long *configs, unsigned num_configs) 267 { 268 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 269 enum pin_config_param param; 270 unsigned int drive_strength_ua; 271 int i, ret; 272 273 for (i = 0; i < num_configs; i++) { 274 param = pinconf_to_config_param(configs[i]); 275 276 switch (param) { 277 case PIN_CONFIG_BIAS_DISABLE: 278 ret = meson_pinconf_disable_bias(pc, pin); 279 if (ret) 280 return ret; 281 break; 282 case PIN_CONFIG_BIAS_PULL_UP: 283 ret = meson_pinconf_enable_bias(pc, pin, true); 284 if (ret) 285 return ret; 286 break; 287 case PIN_CONFIG_BIAS_PULL_DOWN: 288 ret = meson_pinconf_enable_bias(pc, pin, false); 289 if (ret) 290 return ret; 291 break; 292 case PIN_CONFIG_DRIVE_STRENGTH_UA: 293 drive_strength_ua = 294 pinconf_to_config_argument(configs[i]); 295 ret = meson_pinconf_set_drive_strength 296 (pc, pin, drive_strength_ua); 297 if (ret) 298 return ret; 299 break; 300 default: 301 return -ENOTSUPP; 302 } 303 } 304 305 return 0; 306 } 307 308 static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) 309 { 310 struct meson_bank *bank; 311 unsigned int reg, bit, val; 312 int ret, conf; 313 314 ret = meson_get_bank(pc, pin, &bank); 315 if (ret) 316 return ret; 317 318 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 319 320 ret = regmap_read(pc->reg_pullen, reg, &val); 321 if (ret) 322 return ret; 323 324 if (!(val & BIT(bit))) { 325 conf = PIN_CONFIG_BIAS_DISABLE; 326 } else { 327 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 328 329 ret = regmap_read(pc->reg_pull, reg, &val); 330 if (ret) 331 return ret; 332 333 if (val & BIT(bit)) 334 conf = PIN_CONFIG_BIAS_PULL_UP; 335 else 336 conf = PIN_CONFIG_BIAS_PULL_DOWN; 337 } 338 339 return conf; 340 } 341 342 static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc, 343 unsigned int pin, 344 u16 *drive_strength_ua) 345 { 346 struct meson_bank *bank; 347 unsigned int reg, bit; 348 unsigned int val; 349 int ret; 350 351 if (!pc->reg_ds) 352 return -ENOTSUPP; 353 354 ret = meson_get_bank(pc, pin, &bank); 355 if (ret) 356 return ret; 357 358 meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); 359 360 ret = regmap_read(pc->reg_ds, reg, &val); 361 if (ret) 362 return ret; 363 364 switch ((val >> bit) & 0x3) { 365 case MESON_PINCONF_DRV_500UA: 366 *drive_strength_ua = 500; 367 break; 368 case MESON_PINCONF_DRV_2500UA: 369 *drive_strength_ua = 2500; 370 break; 371 case MESON_PINCONF_DRV_3000UA: 372 *drive_strength_ua = 3000; 373 break; 374 case MESON_PINCONF_DRV_4000UA: 375 *drive_strength_ua = 4000; 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 return 0; 382 } 383 384 static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, 385 unsigned long *config) 386 { 387 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 388 enum pin_config_param param = pinconf_to_config_param(*config); 389 u16 arg; 390 int ret; 391 392 switch (param) { 393 case PIN_CONFIG_BIAS_DISABLE: 394 case PIN_CONFIG_BIAS_PULL_DOWN: 395 case PIN_CONFIG_BIAS_PULL_UP: 396 if (meson_pinconf_get_pull(pc, pin) == param) 397 arg = 1; 398 else 399 return -EINVAL; 400 break; 401 case PIN_CONFIG_DRIVE_STRENGTH_UA: 402 ret = meson_pinconf_get_drive_strength(pc, pin, &arg); 403 if (ret) 404 return ret; 405 break; 406 default: 407 return -ENOTSUPP; 408 } 409 410 *config = pinconf_to_config_packed(param, arg); 411 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); 412 413 return 0; 414 } 415 416 static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, 417 unsigned int num_group, 418 unsigned long *configs, unsigned num_configs) 419 { 420 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 421 struct meson_pmx_group *group = &pc->data->groups[num_group]; 422 int i; 423 424 dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); 425 426 for (i = 0; i < group->num_pins; i++) { 427 meson_pinconf_set(pcdev, group->pins[i], configs, 428 num_configs); 429 } 430 431 return 0; 432 } 433 434 static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, 435 unsigned int group, unsigned long *config) 436 { 437 return -ENOTSUPP; 438 } 439 440 static const struct pinconf_ops meson_pinconf_ops = { 441 .pin_config_get = meson_pinconf_get, 442 .pin_config_set = meson_pinconf_set, 443 .pin_config_group_get = meson_pinconf_group_get, 444 .pin_config_group_set = meson_pinconf_group_set, 445 .is_generic = true, 446 }; 447 448 static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 449 { 450 struct meson_pinctrl *pc = gpiochip_get_data(chip); 451 unsigned int reg, bit; 452 struct meson_bank *bank; 453 int ret; 454 455 ret = meson_get_bank(pc, gpio, &bank); 456 if (ret) 457 return ret; 458 459 meson_calc_reg_and_bit(bank, gpio, REG_DIR, ®, &bit); 460 461 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit)); 462 } 463 464 static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 465 int value) 466 { 467 struct meson_pinctrl *pc = gpiochip_get_data(chip); 468 unsigned int reg, bit; 469 struct meson_bank *bank; 470 int ret; 471 472 ret = meson_get_bank(pc, gpio, &bank); 473 if (ret) 474 return ret; 475 476 meson_calc_reg_and_bit(bank, gpio, REG_DIR, ®, &bit); 477 ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0); 478 if (ret) 479 return ret; 480 481 meson_calc_reg_and_bit(bank, gpio, REG_OUT, ®, &bit); 482 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 483 value ? BIT(bit) : 0); 484 } 485 486 static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) 487 { 488 struct meson_pinctrl *pc = gpiochip_get_data(chip); 489 unsigned int reg, bit; 490 struct meson_bank *bank; 491 int ret; 492 493 ret = meson_get_bank(pc, gpio, &bank); 494 if (ret) 495 return; 496 497 meson_calc_reg_and_bit(bank, gpio, REG_OUT, ®, &bit); 498 regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 499 value ? BIT(bit) : 0); 500 } 501 502 static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) 503 { 504 struct meson_pinctrl *pc = gpiochip_get_data(chip); 505 unsigned int reg, bit, val; 506 struct meson_bank *bank; 507 int ret; 508 509 ret = meson_get_bank(pc, gpio, &bank); 510 if (ret) 511 return ret; 512 513 meson_calc_reg_and_bit(bank, gpio, REG_IN, ®, &bit); 514 regmap_read(pc->reg_gpio, reg, &val); 515 516 return !!(val & BIT(bit)); 517 } 518 519 static int meson_gpiolib_register(struct meson_pinctrl *pc) 520 { 521 int ret; 522 523 pc->chip.label = pc->data->name; 524 pc->chip.parent = pc->dev; 525 pc->chip.request = gpiochip_generic_request; 526 pc->chip.free = gpiochip_generic_free; 527 pc->chip.direction_input = meson_gpio_direction_input; 528 pc->chip.direction_output = meson_gpio_direction_output; 529 pc->chip.get = meson_gpio_get; 530 pc->chip.set = meson_gpio_set; 531 pc->chip.base = -1; 532 pc->chip.ngpio = pc->data->num_pins; 533 pc->chip.can_sleep = false; 534 pc->chip.of_node = pc->of_node; 535 pc->chip.of_gpio_n_cells = 2; 536 537 ret = gpiochip_add_data(&pc->chip, pc); 538 if (ret) { 539 dev_err(pc->dev, "can't add gpio chip %s\n", 540 pc->data->name); 541 return ret; 542 } 543 544 return 0; 545 } 546 547 static struct regmap_config meson_regmap_config = { 548 .reg_bits = 32, 549 .val_bits = 32, 550 .reg_stride = 4, 551 }; 552 553 static struct regmap *meson_map_resource(struct meson_pinctrl *pc, 554 struct device_node *node, char *name) 555 { 556 struct resource res; 557 void __iomem *base; 558 int i; 559 560 i = of_property_match_string(node, "reg-names", name); 561 if (of_address_to_resource(node, i, &res)) 562 return ERR_PTR(-ENOENT); 563 564 base = devm_ioremap_resource(pc->dev, &res); 565 if (IS_ERR(base)) 566 return ERR_CAST(base); 567 568 meson_regmap_config.max_register = resource_size(&res) - 4; 569 meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, 570 "%pOFn-%s", node, 571 name); 572 if (!meson_regmap_config.name) 573 return ERR_PTR(-ENOMEM); 574 575 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); 576 } 577 578 static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, 579 struct device_node *node) 580 { 581 struct device_node *np, *gpio_np = NULL; 582 583 for_each_child_of_node(node, np) { 584 if (!of_find_property(np, "gpio-controller", NULL)) 585 continue; 586 if (gpio_np) { 587 dev_err(pc->dev, "multiple gpio nodes\n"); 588 return -EINVAL; 589 } 590 gpio_np = np; 591 } 592 593 if (!gpio_np) { 594 dev_err(pc->dev, "no gpio node found\n"); 595 return -EINVAL; 596 } 597 598 pc->of_node = gpio_np; 599 600 pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); 601 if (IS_ERR(pc->reg_mux)) { 602 dev_err(pc->dev, "mux registers not found\n"); 603 return PTR_ERR(pc->reg_mux); 604 } 605 606 pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio"); 607 if (IS_ERR(pc->reg_gpio)) { 608 dev_err(pc->dev, "gpio registers not found\n"); 609 return PTR_ERR(pc->reg_gpio); 610 } 611 612 pc->reg_pull = meson_map_resource(pc, gpio_np, "pull"); 613 /* Use gpio region if pull one is not present */ 614 if (IS_ERR(pc->reg_pull)) 615 pc->reg_pull = pc->reg_gpio; 616 617 pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable"); 618 /* Use pull region if pull-enable one is not present */ 619 if (IS_ERR(pc->reg_pullen)) 620 pc->reg_pullen = pc->reg_pull; 621 622 pc->reg_ds = meson_map_resource(pc, gpio_np, "ds"); 623 if (IS_ERR(pc->reg_ds)) { 624 dev_dbg(pc->dev, "ds registers not found - skipping\n"); 625 pc->reg_ds = NULL; 626 } 627 628 return 0; 629 } 630 631 int meson_pinctrl_probe(struct platform_device *pdev) 632 { 633 struct device *dev = &pdev->dev; 634 struct meson_pinctrl *pc; 635 int ret; 636 637 pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); 638 if (!pc) 639 return -ENOMEM; 640 641 pc->dev = dev; 642 pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev); 643 644 ret = meson_pinctrl_parse_dt(pc, dev->of_node); 645 if (ret) 646 return ret; 647 648 pc->desc.name = "pinctrl-meson"; 649 pc->desc.owner = THIS_MODULE; 650 pc->desc.pctlops = &meson_pctrl_ops; 651 pc->desc.pmxops = pc->data->pmx_ops; 652 pc->desc.confops = &meson_pinconf_ops; 653 pc->desc.pins = pc->data->pins; 654 pc->desc.npins = pc->data->num_pins; 655 656 pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc); 657 if (IS_ERR(pc->pcdev)) { 658 dev_err(pc->dev, "can't register pinctrl device"); 659 return PTR_ERR(pc->pcdev); 660 } 661 662 return meson_gpiolib_register(pc); 663 } 664