1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Pin controller and GPIO driver for Amlogic Meson SoCs 4 * 5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6 */ 7 8 /* 9 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, 10 * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and 11 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a 12 * variable number of pins. 13 * 14 * The AO bank is special because it belongs to the Always-On power 15 * domain which can't be powered off; the bank also uses a set of 16 * registers different from the other banks. 17 * 18 * For each pin controller there are 4 different register ranges that 19 * control the following properties of the pins: 20 * 1) pin muxing 21 * 2) pull enable/disable 22 * 3) pull up/down 23 * 4) GPIO direction, output value, input value 24 * 25 * In some cases the register ranges for pull enable and pull 26 * direction are the same and thus there are only 3 register ranges. 27 * 28 * Since Meson G12A SoC, the ao register ranges for gpio, pull enable 29 * and pull direction are the same, so there are only 2 register ranges. 30 * 31 * For the pull and GPIO configuration every bank uses a contiguous 32 * set of bits in the register sets described above; the same register 33 * can be shared by more banks with different offsets. 34 * 35 * In addition to this there are some registers shared between all 36 * banks that control the IRQ functionality. This feature is not 37 * supported at the moment by the driver. 38 */ 39 40 #include <linux/device.h> 41 #include <linux/gpio/driver.h> 42 #include <linux/init.h> 43 #include <linux/io.h> 44 #include <linux/of.h> 45 #include <linux/of_address.h> 46 #include <linux/of_device.h> 47 #include <linux/pinctrl/pinconf-generic.h> 48 #include <linux/pinctrl/pinconf.h> 49 #include <linux/pinctrl/pinctrl.h> 50 #include <linux/pinctrl/pinmux.h> 51 #include <linux/platform_device.h> 52 #include <linux/regmap.h> 53 #include <linux/seq_file.h> 54 55 #include "../core.h" 56 #include "../pinctrl-utils.h" 57 #include "pinctrl-meson.h" 58 59 /** 60 * meson_get_bank() - find the bank containing a given pin 61 * 62 * @pc: the pinctrl instance 63 * @pin: the pin number 64 * @bank: the found bank 65 * 66 * Return: 0 on success, a negative value on error 67 */ 68 static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, 69 struct meson_bank **bank) 70 { 71 int i; 72 73 for (i = 0; i < pc->data->num_banks; i++) { 74 if (pin >= pc->data->banks[i].first && 75 pin <= pc->data->banks[i].last) { 76 *bank = &pc->data->banks[i]; 77 return 0; 78 } 79 } 80 81 return -EINVAL; 82 } 83 84 /** 85 * meson_calc_reg_and_bit() - calculate register and bit for a pin 86 * 87 * @bank: the bank containing the pin 88 * @pin: the pin number 89 * @reg_type: the type of register needed (pull-enable, pull, etc...) 90 * @reg: the computed register offset 91 * @bit: the computed bit 92 */ 93 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, 94 enum meson_reg_type reg_type, 95 unsigned int *reg, unsigned int *bit) 96 { 97 struct meson_reg_desc *desc = &bank->regs[reg_type]; 98 99 *reg = desc->reg * 4; 100 *bit = desc->bit + pin - bank->first; 101 } 102 103 static int meson_get_groups_count(struct pinctrl_dev *pcdev) 104 { 105 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 106 107 return pc->data->num_groups; 108 } 109 110 static const char *meson_get_group_name(struct pinctrl_dev *pcdev, 111 unsigned selector) 112 { 113 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 114 115 return pc->data->groups[selector].name; 116 } 117 118 static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, 119 const unsigned **pins, unsigned *num_pins) 120 { 121 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 122 123 *pins = pc->data->groups[selector].pins; 124 *num_pins = pc->data->groups[selector].num_pins; 125 126 return 0; 127 } 128 129 static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, 130 unsigned offset) 131 { 132 seq_printf(s, " %s", dev_name(pcdev->dev)); 133 } 134 135 static const struct pinctrl_ops meson_pctrl_ops = { 136 .get_groups_count = meson_get_groups_count, 137 .get_group_name = meson_get_group_name, 138 .get_group_pins = meson_get_group_pins, 139 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 140 .dt_free_map = pinctrl_utils_free_map, 141 .pin_dbg_show = meson_pin_dbg_show, 142 }; 143 144 int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) 145 { 146 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 147 148 return pc->data->num_funcs; 149 } 150 151 const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, 152 unsigned selector) 153 { 154 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 155 156 return pc->data->funcs[selector].name; 157 } 158 159 int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, 160 const char * const **groups, 161 unsigned * const num_groups) 162 { 163 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 164 165 *groups = pc->data->funcs[selector].groups; 166 *num_groups = pc->data->funcs[selector].num_groups; 167 168 return 0; 169 } 170 171 static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc, 172 unsigned int pin, 173 unsigned int reg_type, 174 bool arg) 175 { 176 struct meson_bank *bank; 177 unsigned int reg, bit; 178 int ret; 179 180 ret = meson_get_bank(pc, pin, &bank); 181 if (ret) 182 return ret; 183 184 meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); 185 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 186 arg ? BIT(bit) : 0); 187 } 188 189 static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc, 190 unsigned int pin, 191 unsigned int reg_type) 192 { 193 struct meson_bank *bank; 194 unsigned int reg, bit, val; 195 int ret; 196 197 ret = meson_get_bank(pc, pin, &bank); 198 if (ret) 199 return ret; 200 201 meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); 202 ret = regmap_read(pc->reg_gpio, reg, &val); 203 if (ret) 204 return ret; 205 206 return BIT(bit) & val ? 1 : 0; 207 } 208 209 static int meson_pinconf_set_output(struct meson_pinctrl *pc, 210 unsigned int pin, 211 bool out) 212 { 213 return meson_pinconf_set_gpio_bit(pc, pin, REG_DIR, !out); 214 } 215 216 static int meson_pinconf_get_output(struct meson_pinctrl *pc, 217 unsigned int pin) 218 { 219 int ret = meson_pinconf_get_gpio_bit(pc, pin, REG_DIR); 220 221 if (ret < 0) 222 return ret; 223 224 return !ret; 225 } 226 227 static int meson_pinconf_set_drive(struct meson_pinctrl *pc, 228 unsigned int pin, 229 bool high) 230 { 231 return meson_pinconf_set_gpio_bit(pc, pin, REG_OUT, high); 232 } 233 234 static int meson_pinconf_get_drive(struct meson_pinctrl *pc, 235 unsigned int pin) 236 { 237 return meson_pinconf_get_gpio_bit(pc, pin, REG_OUT); 238 } 239 240 static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc, 241 unsigned int pin, 242 bool high) 243 { 244 int ret; 245 246 ret = meson_pinconf_set_output(pc, pin, true); 247 if (ret) 248 return ret; 249 250 return meson_pinconf_set_drive(pc, pin, high); 251 } 252 253 static int meson_pinconf_disable_bias(struct meson_pinctrl *pc, 254 unsigned int pin) 255 { 256 struct meson_bank *bank; 257 unsigned int reg, bit = 0; 258 int ret; 259 260 ret = meson_get_bank(pc, pin, &bank); 261 if (ret) 262 return ret; 263 264 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 265 ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0); 266 if (ret) 267 return ret; 268 269 return 0; 270 } 271 272 static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin, 273 bool pull_up) 274 { 275 struct meson_bank *bank; 276 unsigned int reg, bit, val = 0; 277 int ret; 278 279 ret = meson_get_bank(pc, pin, &bank); 280 if (ret) 281 return ret; 282 283 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 284 if (pull_up) 285 val = BIT(bit); 286 287 ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val); 288 if (ret) 289 return ret; 290 291 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 292 ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit)); 293 if (ret) 294 return ret; 295 296 return 0; 297 } 298 299 static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc, 300 unsigned int pin, 301 u16 drive_strength_ua) 302 { 303 struct meson_bank *bank; 304 unsigned int reg, bit, ds_val; 305 int ret; 306 307 if (!pc->reg_ds) { 308 dev_err(pc->dev, "drive-strength not supported\n"); 309 return -ENOTSUPP; 310 } 311 312 ret = meson_get_bank(pc, pin, &bank); 313 if (ret) 314 return ret; 315 316 meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); 317 bit = bit << 1; 318 319 if (drive_strength_ua <= 500) { 320 ds_val = MESON_PINCONF_DRV_500UA; 321 } else if (drive_strength_ua <= 2500) { 322 ds_val = MESON_PINCONF_DRV_2500UA; 323 } else if (drive_strength_ua <= 3000) { 324 ds_val = MESON_PINCONF_DRV_3000UA; 325 } else if (drive_strength_ua <= 4000) { 326 ds_val = MESON_PINCONF_DRV_4000UA; 327 } else { 328 dev_warn_once(pc->dev, 329 "pin %u: invalid drive-strength : %d , default to 4mA\n", 330 pin, drive_strength_ua); 331 ds_val = MESON_PINCONF_DRV_4000UA; 332 } 333 334 ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit); 335 if (ret) 336 return ret; 337 338 return 0; 339 } 340 341 static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, 342 unsigned long *configs, unsigned num_configs) 343 { 344 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 345 enum pin_config_param param; 346 unsigned int arg = 0; 347 int i, ret; 348 349 for (i = 0; i < num_configs; i++) { 350 param = pinconf_to_config_param(configs[i]); 351 352 switch (param) { 353 case PIN_CONFIG_DRIVE_STRENGTH_UA: 354 case PIN_CONFIG_OUTPUT_ENABLE: 355 case PIN_CONFIG_OUTPUT: 356 arg = pinconf_to_config_argument(configs[i]); 357 break; 358 359 default: 360 break; 361 } 362 363 switch (param) { 364 case PIN_CONFIG_BIAS_DISABLE: 365 ret = meson_pinconf_disable_bias(pc, pin); 366 break; 367 case PIN_CONFIG_BIAS_PULL_UP: 368 ret = meson_pinconf_enable_bias(pc, pin, true); 369 break; 370 case PIN_CONFIG_BIAS_PULL_DOWN: 371 ret = meson_pinconf_enable_bias(pc, pin, false); 372 break; 373 case PIN_CONFIG_DRIVE_STRENGTH_UA: 374 ret = meson_pinconf_set_drive_strength(pc, pin, arg); 375 break; 376 case PIN_CONFIG_OUTPUT_ENABLE: 377 ret = meson_pinconf_set_output(pc, pin, arg); 378 break; 379 case PIN_CONFIG_OUTPUT: 380 ret = meson_pinconf_set_output_drive(pc, pin, arg); 381 break; 382 default: 383 ret = -ENOTSUPP; 384 } 385 386 if (ret) 387 return ret; 388 } 389 390 return 0; 391 } 392 393 static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) 394 { 395 struct meson_bank *bank; 396 unsigned int reg, bit, val; 397 int ret, conf; 398 399 ret = meson_get_bank(pc, pin, &bank); 400 if (ret) 401 return ret; 402 403 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 404 405 ret = regmap_read(pc->reg_pullen, reg, &val); 406 if (ret) 407 return ret; 408 409 if (!(val & BIT(bit))) { 410 conf = PIN_CONFIG_BIAS_DISABLE; 411 } else { 412 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 413 414 ret = regmap_read(pc->reg_pull, reg, &val); 415 if (ret) 416 return ret; 417 418 if (val & BIT(bit)) 419 conf = PIN_CONFIG_BIAS_PULL_UP; 420 else 421 conf = PIN_CONFIG_BIAS_PULL_DOWN; 422 } 423 424 return conf; 425 } 426 427 static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc, 428 unsigned int pin, 429 u16 *drive_strength_ua) 430 { 431 struct meson_bank *bank; 432 unsigned int reg, bit; 433 unsigned int val; 434 int ret; 435 436 if (!pc->reg_ds) 437 return -ENOTSUPP; 438 439 ret = meson_get_bank(pc, pin, &bank); 440 if (ret) 441 return ret; 442 443 meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); 444 445 ret = regmap_read(pc->reg_ds, reg, &val); 446 if (ret) 447 return ret; 448 449 switch ((val >> bit) & 0x3) { 450 case MESON_PINCONF_DRV_500UA: 451 *drive_strength_ua = 500; 452 break; 453 case MESON_PINCONF_DRV_2500UA: 454 *drive_strength_ua = 2500; 455 break; 456 case MESON_PINCONF_DRV_3000UA: 457 *drive_strength_ua = 3000; 458 break; 459 case MESON_PINCONF_DRV_4000UA: 460 *drive_strength_ua = 4000; 461 break; 462 default: 463 return -EINVAL; 464 } 465 466 return 0; 467 } 468 469 static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, 470 unsigned long *config) 471 { 472 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 473 enum pin_config_param param = pinconf_to_config_param(*config); 474 u16 arg; 475 int ret; 476 477 switch (param) { 478 case PIN_CONFIG_BIAS_DISABLE: 479 case PIN_CONFIG_BIAS_PULL_DOWN: 480 case PIN_CONFIG_BIAS_PULL_UP: 481 if (meson_pinconf_get_pull(pc, pin) == param) 482 arg = 1; 483 else 484 return -EINVAL; 485 break; 486 case PIN_CONFIG_DRIVE_STRENGTH_UA: 487 ret = meson_pinconf_get_drive_strength(pc, pin, &arg); 488 if (ret) 489 return ret; 490 break; 491 case PIN_CONFIG_OUTPUT_ENABLE: 492 ret = meson_pinconf_get_output(pc, pin); 493 if (ret <= 0) 494 return -EINVAL; 495 arg = 1; 496 break; 497 case PIN_CONFIG_OUTPUT: 498 ret = meson_pinconf_get_output(pc, pin); 499 if (ret <= 0) 500 return -EINVAL; 501 502 ret = meson_pinconf_get_drive(pc, pin); 503 if (ret < 0) 504 return -EINVAL; 505 506 arg = ret; 507 break; 508 509 default: 510 return -ENOTSUPP; 511 } 512 513 *config = pinconf_to_config_packed(param, arg); 514 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); 515 516 return 0; 517 } 518 519 static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, 520 unsigned int num_group, 521 unsigned long *configs, unsigned num_configs) 522 { 523 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 524 struct meson_pmx_group *group = &pc->data->groups[num_group]; 525 int i; 526 527 dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); 528 529 for (i = 0; i < group->num_pins; i++) { 530 meson_pinconf_set(pcdev, group->pins[i], configs, 531 num_configs); 532 } 533 534 return 0; 535 } 536 537 static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, 538 unsigned int group, unsigned long *config) 539 { 540 return -ENOTSUPP; 541 } 542 543 static const struct pinconf_ops meson_pinconf_ops = { 544 .pin_config_get = meson_pinconf_get, 545 .pin_config_set = meson_pinconf_set, 546 .pin_config_group_get = meson_pinconf_group_get, 547 .pin_config_group_set = meson_pinconf_group_set, 548 .is_generic = true, 549 }; 550 551 static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 552 { 553 return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false); 554 } 555 556 static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 557 int value) 558 { 559 return meson_pinconf_set_output_drive(gpiochip_get_data(chip), 560 gpio, value); 561 } 562 563 static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) 564 { 565 meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value); 566 } 567 568 static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) 569 { 570 struct meson_pinctrl *pc = gpiochip_get_data(chip); 571 unsigned int reg, bit, val; 572 struct meson_bank *bank; 573 int ret; 574 575 ret = meson_get_bank(pc, gpio, &bank); 576 if (ret) 577 return ret; 578 579 meson_calc_reg_and_bit(bank, gpio, REG_IN, ®, &bit); 580 regmap_read(pc->reg_gpio, reg, &val); 581 582 return !!(val & BIT(bit)); 583 } 584 585 static int meson_gpiolib_register(struct meson_pinctrl *pc) 586 { 587 int ret; 588 589 pc->chip.label = pc->data->name; 590 pc->chip.parent = pc->dev; 591 pc->chip.request = gpiochip_generic_request; 592 pc->chip.free = gpiochip_generic_free; 593 pc->chip.direction_input = meson_gpio_direction_input; 594 pc->chip.direction_output = meson_gpio_direction_output; 595 pc->chip.get = meson_gpio_get; 596 pc->chip.set = meson_gpio_set; 597 pc->chip.base = -1; 598 pc->chip.ngpio = pc->data->num_pins; 599 pc->chip.can_sleep = false; 600 pc->chip.of_node = pc->of_node; 601 pc->chip.of_gpio_n_cells = 2; 602 603 ret = gpiochip_add_data(&pc->chip, pc); 604 if (ret) { 605 dev_err(pc->dev, "can't add gpio chip %s\n", 606 pc->data->name); 607 return ret; 608 } 609 610 return 0; 611 } 612 613 static struct regmap_config meson_regmap_config = { 614 .reg_bits = 32, 615 .val_bits = 32, 616 .reg_stride = 4, 617 }; 618 619 static struct regmap *meson_map_resource(struct meson_pinctrl *pc, 620 struct device_node *node, char *name) 621 { 622 struct resource res; 623 void __iomem *base; 624 int i; 625 626 i = of_property_match_string(node, "reg-names", name); 627 if (of_address_to_resource(node, i, &res)) 628 return ERR_PTR(-ENOENT); 629 630 base = devm_ioremap_resource(pc->dev, &res); 631 if (IS_ERR(base)) 632 return ERR_CAST(base); 633 634 meson_regmap_config.max_register = resource_size(&res) - 4; 635 meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, 636 "%pOFn-%s", node, 637 name); 638 if (!meson_regmap_config.name) 639 return ERR_PTR(-ENOMEM); 640 641 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); 642 } 643 644 static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, 645 struct device_node *node) 646 { 647 struct device_node *np, *gpio_np = NULL; 648 649 for_each_child_of_node(node, np) { 650 if (!of_find_property(np, "gpio-controller", NULL)) 651 continue; 652 if (gpio_np) { 653 dev_err(pc->dev, "multiple gpio nodes\n"); 654 return -EINVAL; 655 } 656 gpio_np = np; 657 } 658 659 if (!gpio_np) { 660 dev_err(pc->dev, "no gpio node found\n"); 661 return -EINVAL; 662 } 663 664 pc->of_node = gpio_np; 665 666 pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); 667 if (IS_ERR(pc->reg_mux)) { 668 dev_err(pc->dev, "mux registers not found\n"); 669 return PTR_ERR(pc->reg_mux); 670 } 671 672 pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio"); 673 if (IS_ERR(pc->reg_gpio)) { 674 dev_err(pc->dev, "gpio registers not found\n"); 675 return PTR_ERR(pc->reg_gpio); 676 } 677 678 pc->reg_pull = meson_map_resource(pc, gpio_np, "pull"); 679 /* Use gpio region if pull one is not present */ 680 if (IS_ERR(pc->reg_pull)) 681 pc->reg_pull = pc->reg_gpio; 682 683 pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable"); 684 /* Use pull region if pull-enable one is not present */ 685 if (IS_ERR(pc->reg_pullen)) 686 pc->reg_pullen = pc->reg_pull; 687 688 pc->reg_ds = meson_map_resource(pc, gpio_np, "ds"); 689 if (IS_ERR(pc->reg_ds)) { 690 dev_dbg(pc->dev, "ds registers not found - skipping\n"); 691 pc->reg_ds = NULL; 692 } 693 694 return 0; 695 } 696 697 int meson_pinctrl_probe(struct platform_device *pdev) 698 { 699 struct device *dev = &pdev->dev; 700 struct meson_pinctrl *pc; 701 int ret; 702 703 pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); 704 if (!pc) 705 return -ENOMEM; 706 707 pc->dev = dev; 708 pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev); 709 710 ret = meson_pinctrl_parse_dt(pc, dev->of_node); 711 if (ret) 712 return ret; 713 714 pc->desc.name = "pinctrl-meson"; 715 pc->desc.owner = THIS_MODULE; 716 pc->desc.pctlops = &meson_pctrl_ops; 717 pc->desc.pmxops = pc->data->pmx_ops; 718 pc->desc.confops = &meson_pinconf_ops; 719 pc->desc.pins = pc->data->pins; 720 pc->desc.npins = pc->data->num_pins; 721 722 pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc); 723 if (IS_ERR(pc->pcdev)) { 724 dev_err(pc->dev, "can't register pinctrl device"); 725 return PTR_ERR(pc->pcdev); 726 } 727 728 return meson_gpiolib_register(pc); 729 } 730