1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2024 Amlogic, Inc. All rights reserved. 4 * Author: Xianwei Zhao <xianwei.zhao@amlogic.com> 5 */ 6 7 #include <linux/err.h> 8 #include <linux/gpio/driver.h> 9 #include <linux/init.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/seq_file.h> 17 #include <linux/slab.h> 18 #include <linux/string_helpers.h> 19 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <dt-bindings/pinctrl/amlogic,pinctrl.h> 25 26 #include "../core.h" 27 #include "../pinconf.h" 28 29 #define gpio_chip_to_bank(chip) \ 30 container_of(chip, struct aml_gpio_bank, gpio_chip) 31 32 #define AML_REG_PULLEN 0 33 #define AML_REG_PULL 1 34 #define AML_REG_DIR 2 35 #define AML_REG_OUT 3 36 #define AML_REG_IN 4 37 #define AML_REG_DS 5 38 #define AML_NUM_REG 6 39 40 enum aml_pinconf_drv { 41 PINCONF_DRV_500UA, 42 PINCONF_DRV_2500UA, 43 PINCONF_DRV_3000UA, 44 PINCONF_DRV_4000UA, 45 }; 46 47 struct aml_pio_control { 48 u32 gpio_offset; 49 u32 reg_offset[AML_NUM_REG]; 50 u32 bit_offset[AML_NUM_REG]; 51 }; 52 53 struct aml_reg_bit { 54 u32 bank_id; 55 u32 reg_offs[AML_NUM_REG]; 56 u32 bit_offs[AML_NUM_REG]; 57 }; 58 59 struct aml_pctl_data { 60 unsigned int number; 61 struct aml_reg_bit rb_offs[]; 62 }; 63 64 struct aml_pmx_func { 65 const char *name; 66 const char **groups; 67 unsigned int ngroups; 68 }; 69 70 struct aml_pctl_group { 71 const char *name; 72 unsigned int npins; 73 unsigned int *pins; 74 unsigned int *func; 75 }; 76 77 struct aml_gpio_bank { 78 struct gpio_chip gpio_chip; 79 struct aml_pio_control pc; 80 u32 bank_id; 81 unsigned int pin_base; 82 struct regmap *reg_mux; 83 struct regmap *reg_gpio; 84 struct regmap *reg_ds; 85 }; 86 87 struct aml_pinctrl { 88 struct device *dev; 89 struct pinctrl_dev *pctl; 90 struct aml_gpio_bank *banks; 91 int nbanks; 92 struct aml_pmx_func *functions; 93 int nfunctions; 94 struct aml_pctl_group *groups; 95 int ngroups; 96 97 const struct aml_pctl_data *data; 98 }; 99 100 static const unsigned int aml_bit_strides[AML_NUM_REG] = { 101 1, 1, 1, 1, 1, 2 102 }; 103 104 static const unsigned int aml_def_regoffs[AML_NUM_REG] = { 105 3, 4, 2, 1, 0, 7 106 }; 107 108 static const char *aml_bank_name[31] = { 109 "GPIOA", "GPIOB", "GPIOC", "GPIOD", "GPIOE", "GPIOF", "GPIOG", 110 "GPIOH", "GPIOI", "GPIOJ", "GPIOK", "GPIOL", "GPIOM", "GPION", 111 "GPIOO", "GPIOP", "GPIOQ", "GPIOR", "GPIOS", "GPIOT", "GPIOU", 112 "GPIOV", "GPIOW", "GPIOX", "GPIOY", "GPIOZ", "GPIODV", "GPIOAO", 113 "GPIOCC", "TEST_N", "ANALOG" 114 }; 115 116 static int aml_pmx_calc_reg_and_offset(struct pinctrl_gpio_range *range, 117 unsigned int pin, unsigned int *reg, 118 unsigned int *offset) 119 { 120 unsigned int shift; 121 122 shift = (pin - range->pin_base) << 2; 123 *reg = (shift / 32) * 4; 124 *offset = shift % 32; 125 126 return 0; 127 } 128 129 static int aml_pctl_set_function(struct aml_pinctrl *info, 130 struct pinctrl_gpio_range *range, 131 int pin_id, int func) 132 { 133 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 134 int reg; 135 int offset; 136 137 if (!bank->reg_mux) 138 return 0; 139 140 aml_pmx_calc_reg_and_offset(range, pin_id, ®, &offset); 141 return regmap_update_bits(bank->reg_mux, reg, 142 0xf << offset, (func & 0xf) << offset); 143 } 144 145 static int aml_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 146 { 147 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 148 149 return info->nfunctions; 150 } 151 152 static const char *aml_pmx_get_fname(struct pinctrl_dev *pctldev, 153 unsigned int selector) 154 { 155 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 156 157 return info->functions[selector].name; 158 } 159 160 static int aml_pmx_get_groups(struct pinctrl_dev *pctldev, 161 unsigned int selector, 162 const char * const **grps, 163 unsigned * const ngrps) 164 { 165 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 166 167 *grps = info->functions[selector].groups; 168 *ngrps = info->functions[selector].ngroups; 169 170 return 0; 171 } 172 173 static int aml_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned int fselector, 174 unsigned int group_id) 175 { 176 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 177 struct aml_pctl_group *group = &info->groups[group_id]; 178 struct pinctrl_gpio_range *range; 179 int i; 180 181 for (i = 0; i < group->npins; i++) { 182 range = pinctrl_find_gpio_range_from_pin(pctldev, group->pins[i]); 183 aml_pctl_set_function(info, range, group->pins[i], group->func[i]); 184 } 185 186 return 0; 187 } 188 189 static int aml_pmx_request_gpio(struct pinctrl_dev *pctldev, 190 struct pinctrl_gpio_range *range, 191 unsigned int pin) 192 { 193 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 194 195 return aml_pctl_set_function(info, range, pin, 0); 196 } 197 198 static const struct pinmux_ops aml_pmx_ops = { 199 .set_mux = aml_pmx_set_mux, 200 .get_functions_count = aml_pmx_get_funcs_count, 201 .get_function_name = aml_pmx_get_fname, 202 .get_function_groups = aml_pmx_get_groups, 203 .gpio_request_enable = aml_pmx_request_gpio, 204 }; 205 206 static int aml_calc_reg_and_bit(struct pinctrl_gpio_range *range, 207 unsigned int pin, 208 unsigned int reg_type, 209 unsigned int *reg, unsigned int *bit) 210 { 211 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 212 213 *bit = (pin - range->pin_base) * aml_bit_strides[reg_type] 214 + bank->pc.bit_offset[reg_type]; 215 *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; 216 *bit &= 0x1f; 217 218 return 0; 219 } 220 221 static int aml_pinconf_get_pull(struct aml_pinctrl *info, unsigned int pin) 222 { 223 struct pinctrl_gpio_range *range = 224 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 225 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 226 unsigned int reg, bit, val; 227 int ret, conf; 228 229 aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); 230 231 ret = regmap_read(bank->reg_gpio, reg, &val); 232 if (ret) 233 return ret; 234 235 if (!(val & BIT(bit))) { 236 conf = PIN_CONFIG_BIAS_DISABLE; 237 } else { 238 aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); 239 240 ret = regmap_read(bank->reg_gpio, reg, &val); 241 if (ret) 242 return ret; 243 244 if (val & BIT(bit)) 245 conf = PIN_CONFIG_BIAS_PULL_UP; 246 else 247 conf = PIN_CONFIG_BIAS_PULL_DOWN; 248 } 249 250 return conf; 251 } 252 253 static int aml_pinconf_get_drive_strength(struct aml_pinctrl *info, 254 unsigned int pin, 255 u16 *drive_strength_ua) 256 { 257 struct pinctrl_gpio_range *range = 258 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 259 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 260 unsigned int reg, bit; 261 unsigned int val; 262 int ret; 263 264 if (!bank->reg_ds) 265 return -EOPNOTSUPP; 266 267 aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); 268 ret = regmap_read(bank->reg_ds, reg, &val); 269 if (ret) 270 return ret; 271 272 switch ((val >> bit) & 0x3) { 273 case PINCONF_DRV_500UA: 274 *drive_strength_ua = 500; 275 break; 276 case PINCONF_DRV_2500UA: 277 *drive_strength_ua = 2500; 278 break; 279 case PINCONF_DRV_3000UA: 280 *drive_strength_ua = 3000; 281 break; 282 case PINCONF_DRV_4000UA: 283 *drive_strength_ua = 4000; 284 break; 285 default: 286 return -EINVAL; 287 } 288 289 return 0; 290 } 291 292 static int aml_pinconf_get_gpio_bit(struct aml_pinctrl *info, 293 unsigned int pin, 294 unsigned int reg_type) 295 { 296 struct pinctrl_gpio_range *range = 297 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 298 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 299 unsigned int reg, bit, val; 300 int ret; 301 302 aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); 303 ret = regmap_read(bank->reg_gpio, reg, &val); 304 if (ret) 305 return ret; 306 307 return BIT(bit) & val ? 1 : 0; 308 } 309 310 static int aml_pinconf_get_output(struct aml_pinctrl *info, 311 unsigned int pin) 312 { 313 int ret = aml_pinconf_get_gpio_bit(info, pin, AML_REG_DIR); 314 315 if (ret < 0) 316 return ret; 317 318 return !ret; 319 } 320 321 static int aml_pinconf_get_drive(struct aml_pinctrl *info, 322 unsigned int pin) 323 { 324 return aml_pinconf_get_gpio_bit(info, pin, AML_REG_OUT); 325 } 326 327 static int aml_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, 328 unsigned long *config) 329 { 330 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); 331 enum pin_config_param param = pinconf_to_config_param(*config); 332 u16 arg; 333 int ret; 334 335 switch (param) { 336 case PIN_CONFIG_BIAS_DISABLE: 337 case PIN_CONFIG_BIAS_PULL_DOWN: 338 case PIN_CONFIG_BIAS_PULL_UP: 339 if (aml_pinconf_get_pull(info, pin) == param) 340 arg = 1; 341 else 342 return -EINVAL; 343 break; 344 case PIN_CONFIG_DRIVE_STRENGTH_UA: 345 ret = aml_pinconf_get_drive_strength(info, pin, &arg); 346 if (ret) 347 return ret; 348 break; 349 case PIN_CONFIG_OUTPUT_ENABLE: 350 ret = aml_pinconf_get_output(info, pin); 351 if (ret <= 0) 352 return -EINVAL; 353 arg = 1; 354 break; 355 case PIN_CONFIG_OUTPUT: 356 ret = aml_pinconf_get_output(info, pin); 357 if (ret <= 0) 358 return -EINVAL; 359 360 ret = aml_pinconf_get_drive(info, pin); 361 if (ret < 0) 362 return -EINVAL; 363 364 arg = ret; 365 break; 366 367 default: 368 return -ENOTSUPP; 369 } 370 371 *config = pinconf_to_config_packed(param, arg); 372 dev_dbg(info->dev, "pinconf for pin %u is %lu\n", pin, *config); 373 374 return 0; 375 } 376 377 static int aml_pinconf_disable_bias(struct aml_pinctrl *info, 378 unsigned int pin) 379 { 380 struct pinctrl_gpio_range *range = 381 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 382 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 383 unsigned int reg, bit = 0; 384 385 aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); 386 387 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); 388 } 389 390 static int aml_pinconf_enable_bias(struct aml_pinctrl *info, unsigned int pin, 391 bool pull_up) 392 { 393 struct pinctrl_gpio_range *range = 394 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 395 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 396 unsigned int reg, bit, val = 0; 397 int ret; 398 399 aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); 400 if (pull_up) 401 val = BIT(bit); 402 403 ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), val); 404 if (ret) 405 return ret; 406 407 aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); 408 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); 409 } 410 411 static int aml_pinconf_set_drive_strength(struct aml_pinctrl *info, 412 unsigned int pin, 413 u16 drive_strength_ua) 414 { 415 struct pinctrl_gpio_range *range = 416 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 417 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 418 unsigned int reg, bit, ds_val; 419 420 if (!bank->reg_ds) { 421 dev_err(info->dev, "drive-strength not supported\n"); 422 return -EOPNOTSUPP; 423 } 424 425 aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); 426 427 if (drive_strength_ua <= 500) { 428 ds_val = PINCONF_DRV_500UA; 429 } else if (drive_strength_ua <= 2500) { 430 ds_val = PINCONF_DRV_2500UA; 431 } else if (drive_strength_ua <= 3000) { 432 ds_val = PINCONF_DRV_3000UA; 433 } else if (drive_strength_ua <= 4000) { 434 ds_val = PINCONF_DRV_4000UA; 435 } else { 436 dev_warn_once(info->dev, 437 "pin %u: invalid drive-strength : %d , default to 4mA\n", 438 pin, drive_strength_ua); 439 ds_val = PINCONF_DRV_4000UA; 440 } 441 442 return regmap_update_bits(bank->reg_ds, reg, 0x3 << bit, ds_val << bit); 443 } 444 445 static int aml_pinconf_set_gpio_bit(struct aml_pinctrl *info, 446 unsigned int pin, 447 unsigned int reg_type, 448 bool arg) 449 { 450 struct pinctrl_gpio_range *range = 451 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 452 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 453 unsigned int reg, bit; 454 455 aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); 456 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 457 arg ? BIT(bit) : 0); 458 } 459 460 static int aml_pinconf_set_output(struct aml_pinctrl *info, 461 unsigned int pin, 462 bool out) 463 { 464 return aml_pinconf_set_gpio_bit(info, pin, AML_REG_DIR, !out); 465 } 466 467 static int aml_pinconf_set_drive(struct aml_pinctrl *info, 468 unsigned int pin, 469 bool high) 470 { 471 return aml_pinconf_set_gpio_bit(info, pin, AML_REG_OUT, high); 472 } 473 474 static int aml_pinconf_set_output_drive(struct aml_pinctrl *info, 475 unsigned int pin, 476 bool high) 477 { 478 int ret; 479 480 ret = aml_pinconf_set_output(info, pin, true); 481 if (ret) 482 return ret; 483 484 return aml_pinconf_set_drive(info, pin, high); 485 } 486 487 static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, 488 unsigned long *configs, unsigned int num_configs) 489 { 490 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); 491 enum pin_config_param param; 492 unsigned int arg = 0; 493 int i, ret; 494 495 for (i = 0; i < num_configs; i++) { 496 param = pinconf_to_config_param(configs[i]); 497 498 switch (param) { 499 case PIN_CONFIG_DRIVE_STRENGTH_UA: 500 case PIN_CONFIG_OUTPUT_ENABLE: 501 case PIN_CONFIG_OUTPUT: 502 arg = pinconf_to_config_argument(configs[i]); 503 break; 504 505 default: 506 break; 507 } 508 509 switch (param) { 510 case PIN_CONFIG_BIAS_DISABLE: 511 ret = aml_pinconf_disable_bias(info, pin); 512 break; 513 case PIN_CONFIG_BIAS_PULL_UP: 514 ret = aml_pinconf_enable_bias(info, pin, true); 515 break; 516 case PIN_CONFIG_BIAS_PULL_DOWN: 517 ret = aml_pinconf_enable_bias(info, pin, false); 518 break; 519 case PIN_CONFIG_DRIVE_STRENGTH_UA: 520 ret = aml_pinconf_set_drive_strength(info, pin, arg); 521 break; 522 case PIN_CONFIG_OUTPUT_ENABLE: 523 ret = aml_pinconf_set_output(info, pin, arg); 524 break; 525 case PIN_CONFIG_OUTPUT: 526 ret = aml_pinconf_set_output_drive(info, pin, arg); 527 break; 528 default: 529 ret = -ENOTSUPP; 530 } 531 532 if (ret) 533 return ret; 534 } 535 536 return 0; 537 } 538 539 static int aml_pinconf_group_set(struct pinctrl_dev *pcdev, 540 unsigned int num_group, 541 unsigned long *configs, 542 unsigned int num_configs) 543 { 544 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); 545 int i; 546 547 for (i = 0; i < info->groups[num_group].npins; i++) { 548 aml_pinconf_set(pcdev, info->groups[num_group].pins[i], configs, 549 num_configs); 550 } 551 552 return 0; 553 } 554 555 static int aml_pinconf_group_get(struct pinctrl_dev *pcdev, 556 unsigned int group, unsigned long *config) 557 { 558 return -EOPNOTSUPP; 559 } 560 561 static const struct pinconf_ops aml_pinconf_ops = { 562 .pin_config_get = aml_pinconf_get, 563 .pin_config_set = aml_pinconf_set, 564 .pin_config_group_get = aml_pinconf_group_get, 565 .pin_config_group_set = aml_pinconf_group_set, 566 .is_generic = true, 567 }; 568 569 static int aml_get_groups_count(struct pinctrl_dev *pctldev) 570 { 571 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 572 573 return info->ngroups; 574 } 575 576 static const char *aml_get_group_name(struct pinctrl_dev *pctldev, 577 unsigned int selector) 578 { 579 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 580 581 return info->groups[selector].name; 582 } 583 584 static int aml_get_group_pins(struct pinctrl_dev *pctldev, 585 unsigned int selector, const unsigned int **pins, 586 unsigned int *npins) 587 { 588 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 589 590 if (selector >= info->ngroups) 591 return -EINVAL; 592 593 *pins = info->groups[selector].pins; 594 *npins = info->groups[selector].npins; 595 596 return 0; 597 } 598 599 static void aml_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, 600 unsigned int offset) 601 { 602 seq_printf(s, " %s", dev_name(pcdev->dev)); 603 } 604 605 static const struct pinctrl_ops aml_pctrl_ops = { 606 .get_groups_count = aml_get_groups_count, 607 .get_group_name = aml_get_group_name, 608 .get_group_pins = aml_get_group_pins, 609 .dt_node_to_map = pinconf_generic_dt_node_to_map_pinmux, 610 .dt_free_map = pinconf_generic_dt_free_map, 611 .pin_dbg_show = aml_pin_dbg_show, 612 }; 613 614 static int aml_pctl_parse_functions(struct device_node *np, 615 struct aml_pinctrl *info, u32 index, 616 int *grp_index) 617 { 618 struct device *dev = info->dev; 619 struct aml_pmx_func *func; 620 struct aml_pctl_group *grp; 621 int ret, i; 622 623 func = &info->functions[index]; 624 func->name = np->name; 625 func->ngroups = of_get_child_count(np); 626 if (func->ngroups == 0) 627 return dev_err_probe(dev, -EINVAL, "No groups defined\n"); 628 629 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 630 if (!func->groups) 631 return -ENOMEM; 632 633 i = 0; 634 for_each_child_of_node_scoped(np, child) { 635 func->groups[i++] = child->name; 636 grp = &info->groups[*grp_index]; 637 grp->name = child->name; 638 *grp_index += 1; 639 ret = pinconf_generic_parse_dt_pinmux(child, dev, &grp->pins, 640 &grp->func, &grp->npins); 641 if (ret) { 642 dev_err(dev, "function :%s, groups:%s fail\n", func->name, child->name); 643 return ret; 644 } 645 } 646 dev_dbg(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); 647 648 return 0; 649 } 650 651 static u32 aml_bank_pins(struct device_node *np) 652 { 653 struct of_phandle_args of_args; 654 655 if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 656 0, &of_args)) 657 return 0; 658 else 659 return of_args.args[2]; 660 } 661 662 static int aml_bank_number(struct device_node *np) 663 { 664 struct of_phandle_args of_args; 665 666 if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 667 0, &of_args)) 668 return -EINVAL; 669 else 670 return of_args.args[1] >> 8; 671 } 672 673 static unsigned int aml_count_pins(struct device_node *np) 674 { 675 struct device_node *child; 676 unsigned int pins = 0; 677 678 for_each_child_of_node(np, child) { 679 if (of_property_read_bool(child, "gpio-controller")) 680 pins += aml_bank_pins(child); 681 } 682 683 return pins; 684 } 685 686 /* 687 * A pinctrl device contains two types of nodes. The one named GPIO 688 * bank which includes gpio-controller property. The other one named 689 * function which includes one or more pin groups. The pin group 690 * include pinmux property(global index in pinctrl dev, and mux vlaue 691 * in mux reg) and pin configuration properties. 692 */ 693 static void aml_pctl_dt_child_count(struct aml_pinctrl *info, 694 struct device_node *np) 695 { 696 struct device_node *child; 697 698 for_each_child_of_node(np, child) { 699 if (of_property_read_bool(child, "gpio-controller")) { 700 info->nbanks++; 701 } else { 702 info->nfunctions++; 703 info->ngroups += of_get_child_count(child); 704 } 705 } 706 } 707 708 static struct regmap *aml_map_resource(struct device *dev, unsigned int id, 709 struct device_node *node, char *name) 710 { 711 struct resource res; 712 void __iomem *base; 713 int i; 714 715 struct regmap_config aml_regmap_config = { 716 .reg_bits = 32, 717 .val_bits = 32, 718 .reg_stride = 4, 719 }; 720 721 i = of_property_match_string(node, "reg-names", name); 722 if (i < 0) 723 return NULL; 724 if (of_address_to_resource(node, i, &res)) 725 return NULL; 726 base = devm_ioremap_resource(dev, &res); 727 if (IS_ERR(base)) 728 return ERR_CAST(base); 729 730 aml_regmap_config.max_register = resource_size(&res) - 4; 731 aml_regmap_config.name = devm_kasprintf(dev, GFP_KERNEL, 732 "%s-%s", aml_bank_name[id], name); 733 if (!aml_regmap_config.name) 734 return ERR_PTR(-ENOMEM); 735 736 return devm_regmap_init_mmio(dev, base, &aml_regmap_config); 737 } 738 739 static inline int aml_gpio_calc_reg_and_bit(struct aml_gpio_bank *bank, 740 unsigned int reg_type, 741 unsigned int gpio, 742 unsigned int *reg, 743 unsigned int *bit) 744 { 745 *bit = gpio * aml_bit_strides[reg_type] + bank->pc.bit_offset[reg_type]; 746 *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; 747 *bit &= 0x1f; 748 749 return 0; 750 } 751 752 static int aml_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) 753 { 754 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 755 unsigned int bit, reg, val; 756 int ret; 757 758 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); 759 760 ret = regmap_read(bank->reg_gpio, reg, &val); 761 if (ret) 762 return ret; 763 764 return BIT(bit) & val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 765 } 766 767 static int aml_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) 768 { 769 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 770 unsigned int bit, reg; 771 772 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); 773 774 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); 775 } 776 777 static int aml_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, 778 int value) 779 { 780 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 781 unsigned int bit, reg; 782 int ret; 783 784 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); 785 ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); 786 if (ret < 0) 787 return ret; 788 789 aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); 790 791 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 792 value ? BIT(bit) : 0); 793 } 794 795 static int aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) 796 { 797 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 798 unsigned int bit, reg; 799 800 aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); 801 802 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 803 value ? BIT(bit) : 0); 804 } 805 806 static int aml_gpio_get(struct gpio_chip *chip, unsigned int gpio) 807 { 808 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 809 unsigned int reg, bit, val; 810 811 aml_gpio_calc_reg_and_bit(bank, AML_REG_IN, gpio, ®, &bit); 812 regmap_read(bank->reg_gpio, reg, &val); 813 814 return !!(val & BIT(bit)); 815 } 816 817 static const struct gpio_chip aml_gpio_template = { 818 .request = gpiochip_generic_request, 819 .free = gpiochip_generic_free, 820 .set_config = gpiochip_generic_config, 821 .set_rv = aml_gpio_set, 822 .get = aml_gpio_get, 823 .direction_input = aml_gpio_direction_input, 824 .direction_output = aml_gpio_direction_output, 825 .get_direction = aml_gpio_get_direction, 826 .can_sleep = false, 827 }; 828 829 static void init_bank_register_bit(struct aml_pinctrl *info, 830 struct aml_gpio_bank *bank) 831 { 832 const struct aml_pctl_data *data = info->data; 833 const struct aml_reg_bit *aml_rb; 834 bool def_offs = true; 835 int i; 836 837 if (data) { 838 for (i = 0; i < data->number; i++) { 839 aml_rb = &data->rb_offs[i]; 840 if (bank->bank_id == aml_rb->bank_id) { 841 def_offs = false; 842 break; 843 } 844 } 845 } 846 847 if (def_offs) { 848 for (i = 0; i < AML_NUM_REG; i++) { 849 bank->pc.reg_offset[i] = aml_def_regoffs[i]; 850 bank->pc.bit_offset[i] = 0; 851 } 852 } else { 853 for (i = 0; i < AML_NUM_REG; i++) { 854 bank->pc.reg_offset[i] = aml_rb->reg_offs[i]; 855 bank->pc.bit_offset[i] = aml_rb->bit_offs[i]; 856 } 857 } 858 } 859 860 static int aml_gpiolib_register_bank(struct aml_pinctrl *info, 861 int bank_nr, struct device_node *np) 862 { 863 struct aml_gpio_bank *bank = &info->banks[bank_nr]; 864 struct device *dev = info->dev; 865 int ret = 0; 866 867 ret = aml_bank_number(np); 868 if (ret < 0) { 869 dev_err(dev, "get num=%d bank identity fail\n", bank_nr); 870 return -EINVAL; 871 } 872 bank->bank_id = ret; 873 874 bank->reg_mux = aml_map_resource(dev, bank->bank_id, np, "mux"); 875 if (IS_ERR_OR_NULL(bank->reg_mux)) { 876 if (bank->bank_id == AMLOGIC_GPIO_TEST_N || 877 bank->bank_id == AMLOGIC_GPIO_ANALOG) 878 bank->reg_mux = NULL; 879 else 880 return dev_err_probe(dev, bank->reg_mux ? PTR_ERR(bank->reg_mux) : -ENOENT, 881 "mux registers not found\n"); 882 } 883 884 bank->reg_gpio = aml_map_resource(dev, bank->bank_id, np, "gpio"); 885 if (IS_ERR_OR_NULL(bank->reg_gpio)) 886 return dev_err_probe(dev, bank->reg_gpio ? PTR_ERR(bank->reg_gpio) : -ENOENT, 887 "gpio registers not found\n"); 888 889 bank->reg_ds = aml_map_resource(dev, bank->bank_id, np, "ds"); 890 if (IS_ERR_OR_NULL(bank->reg_ds)) { 891 dev_dbg(info->dev, "ds registers not found - skipping\n"); 892 bank->reg_ds = bank->reg_gpio; 893 } 894 895 bank->gpio_chip = aml_gpio_template; 896 bank->gpio_chip.base = -1; 897 bank->gpio_chip.ngpio = aml_bank_pins(np); 898 bank->gpio_chip.fwnode = of_fwnode_handle(np); 899 bank->gpio_chip.parent = dev; 900 901 init_bank_register_bit(info, bank); 902 bank->gpio_chip.label = aml_bank_name[bank->bank_id]; 903 904 bank->pin_base = bank->bank_id << 8; 905 906 return 0; 907 } 908 909 static int aml_pctl_probe_dt(struct platform_device *pdev, 910 struct pinctrl_desc *pctl_desc, 911 struct aml_pinctrl *info) 912 { 913 struct device *dev = &pdev->dev; 914 struct pinctrl_pin_desc *pdesc; 915 struct device_node *np = dev->of_node; 916 int grp_index = 0; 917 int i = 0, j = 0, k = 0, bank; 918 int ret = 0; 919 920 aml_pctl_dt_child_count(info, np); 921 if (!info->nbanks) 922 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); 923 924 dev_dbg(dev, "nbanks = %d\n", info->nbanks); 925 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); 926 dev_dbg(dev, "ngroups = %d\n", info->ngroups); 927 928 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 929 930 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 931 932 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); 933 934 if (!info->functions || !info->groups || !info->banks) 935 return -ENOMEM; 936 937 info->data = (struct aml_pctl_data *)of_device_get_match_data(dev); 938 939 pctl_desc->npins = aml_count_pins(np); 940 941 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); 942 if (!pdesc) 943 return -ENOMEM; 944 945 pctl_desc->pins = pdesc; 946 947 bank = 0; 948 for_each_child_of_node_scoped(np, child) { 949 if (of_property_read_bool(child, "gpio-controller")) { 950 const char *bank_name = NULL; 951 char **pin_names; 952 953 ret = aml_gpiolib_register_bank(info, bank, child); 954 if (ret) 955 return ret; 956 957 k = info->banks[bank].pin_base; 958 bank_name = info->banks[bank].gpio_chip.label; 959 960 pin_names = devm_kasprintf_strarray(dev, bank_name, 961 info->banks[bank].gpio_chip.ngpio); 962 if (IS_ERR(pin_names)) 963 return PTR_ERR(pin_names); 964 965 for (j = 0; j < info->banks[bank].gpio_chip.ngpio; j++, k++) { 966 pdesc->number = k; 967 pdesc->name = pin_names[j]; 968 pdesc++; 969 } 970 bank++; 971 } else { 972 ret = aml_pctl_parse_functions(child, info, 973 i++, &grp_index); 974 if (ret) 975 return ret; 976 } 977 } 978 979 return 0; 980 } 981 982 static int aml_pctl_probe(struct platform_device *pdev) 983 { 984 struct device *dev = &pdev->dev; 985 struct aml_pinctrl *info; 986 struct pinctrl_desc *pctl_desc; 987 int ret, i; 988 989 pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); 990 if (!pctl_desc) 991 return -ENOMEM; 992 993 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 994 if (!info) 995 return -ENOMEM; 996 997 info->dev = dev; 998 platform_set_drvdata(pdev, info); 999 ret = aml_pctl_probe_dt(pdev, pctl_desc, info); 1000 if (ret) 1001 return ret; 1002 1003 pctl_desc->owner = THIS_MODULE; 1004 pctl_desc->pctlops = &aml_pctrl_ops; 1005 pctl_desc->pmxops = &aml_pmx_ops; 1006 pctl_desc->confops = &aml_pinconf_ops; 1007 pctl_desc->name = dev_name(dev); 1008 1009 info->pctl = devm_pinctrl_register(dev, pctl_desc, info); 1010 if (IS_ERR(info->pctl)) 1011 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); 1012 1013 for (i = 0; i < info->nbanks; i++) { 1014 ret = gpiochip_add_data(&info->banks[i].gpio_chip, &info->banks[i]); 1015 if (ret) 1016 return dev_err_probe(dev, ret, "Failed to add gpiochip(%d)!\n", i); 1017 } 1018 1019 return 0; 1020 } 1021 1022 static const struct of_device_id aml_pctl_of_match[] = { 1023 { .compatible = "amlogic,pinctrl-a4", }, 1024 { /* sentinel */ } 1025 }; 1026 MODULE_DEVICE_TABLE(of, aml_pctl_dt_match); 1027 1028 static struct platform_driver aml_pctl_driver = { 1029 .driver = { 1030 .name = "amlogic-pinctrl", 1031 .of_match_table = aml_pctl_of_match, 1032 }, 1033 .probe = aml_pctl_probe, 1034 }; 1035 module_platform_driver(aml_pctl_driver); 1036 1037 MODULE_AUTHOR("Xianwei Zhao <xianwei.zhao@amlogic.com>"); 1038 MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic SoC"); 1039 MODULE_LICENSE("Dual BSD/GPL"); 1040