1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2024 Amlogic, Inc. All rights reserved. 4 * Author: Xianwei Zhao <xianwei.zhao@amlogic.com> 5 */ 6 7 #include <linux/err.h> 8 #include <linux/gpio/driver.h> 9 #include <linux/init.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/seq_file.h> 17 #include <linux/slab.h> 18 #include <linux/string_helpers.h> 19 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <dt-bindings/pinctrl/amlogic,pinctrl.h> 25 26 #include "../core.h" 27 #include "../pinconf.h" 28 29 #define gpio_chip_to_bank(chip) \ 30 container_of(chip, struct aml_gpio_bank, gpio_chip) 31 32 #define AML_REG_PULLEN 0 33 #define AML_REG_PULL 1 34 #define AML_REG_DIR 2 35 #define AML_REG_OUT 3 36 #define AML_REG_IN 4 37 #define AML_REG_DS 5 38 #define AML_NUM_REG 6 39 40 enum aml_pinconf_drv { 41 PINCONF_DRV_500UA, 42 PINCONF_DRV_2500UA, 43 PINCONF_DRV_3000UA, 44 PINCONF_DRV_4000UA, 45 }; 46 47 struct aml_pio_control { 48 u32 gpio_offset; 49 u32 reg_offset[AML_NUM_REG]; 50 u32 bit_offset[AML_NUM_REG]; 51 }; 52 53 /* 54 * partial bank(subordinate) pins mux config use other bank(main) mux registgers 55 * m_bank_id: the main bank which pin_id from 0, but register bit not from bit 0 56 * m_bit_offs: bit offset the main bank mux register 57 * sid: start pin_id of subordinate bank 58 * eid: end pin_id of subordinate bank 59 */ 60 struct multi_mux { 61 unsigned int m_bank_id; 62 unsigned int m_bit_offs; 63 unsigned int sid; 64 unsigned int eid; 65 }; 66 67 struct aml_pctl_data { 68 unsigned int number; 69 const struct multi_mux *p_mux; 70 }; 71 72 struct aml_pmx_func { 73 const char *name; 74 const char **groups; 75 unsigned int ngroups; 76 }; 77 78 struct aml_pctl_group { 79 const char *name; 80 unsigned int npins; 81 unsigned int *pins; 82 unsigned int *func; 83 }; 84 85 struct aml_gpio_bank { 86 struct gpio_chip gpio_chip; 87 struct aml_pio_control pc; 88 u32 bank_id; 89 u32 mux_bit_offs; 90 unsigned int pin_base; 91 struct regmap *reg_mux; 92 struct regmap *reg_gpio; 93 struct regmap *reg_ds; 94 const struct multi_mux *p_mux; 95 }; 96 97 struct aml_pinctrl { 98 struct device *dev; 99 struct pinctrl_dev *pctl; 100 struct aml_gpio_bank *banks; 101 int nbanks; 102 struct aml_pmx_func *functions; 103 int nfunctions; 104 struct aml_pctl_group *groups; 105 int ngroups; 106 107 const struct aml_pctl_data *data; 108 }; 109 110 static const unsigned int aml_bit_strides[AML_NUM_REG] = { 111 1, 1, 1, 1, 1, 2 112 }; 113 114 static const unsigned int aml_def_regoffs[AML_NUM_REG] = { 115 3, 4, 2, 1, 0, 7 116 }; 117 118 static const char *aml_bank_name[31] = { 119 "GPIOA", "GPIOB", "GPIOC", "GPIOD", "GPIOE", "GPIOF", "GPIOG", 120 "GPIOH", "GPIOI", "GPIOJ", "GPIOK", "GPIOL", "GPIOM", "GPION", 121 "GPIOO", "GPIOP", "GPIOQ", "GPIOR", "GPIOS", "GPIOT", "GPIOU", 122 "GPIOV", "GPIOW", "GPIOX", "GPIOY", "GPIOZ", "GPIODV", "GPIOAO", 123 "GPIOCC", "TEST_N", "ANALOG" 124 }; 125 126 static const struct multi_mux multi_mux_s7[] = { 127 { 128 .m_bank_id = AMLOGIC_GPIO_CC, 129 .m_bit_offs = 24, 130 .sid = (AMLOGIC_GPIO_X << 8) + 16, 131 .eid = (AMLOGIC_GPIO_X << 8) + 19, 132 }, 133 }; 134 135 static const struct aml_pctl_data s7_priv_data = { 136 .number = ARRAY_SIZE(multi_mux_s7), 137 .p_mux = multi_mux_s7, 138 }; 139 140 static const struct multi_mux multi_mux_s6[] = { 141 { 142 .m_bank_id = AMLOGIC_GPIO_CC, 143 .m_bit_offs = 24, 144 .sid = (AMLOGIC_GPIO_X << 8) + 16, 145 .eid = (AMLOGIC_GPIO_X << 8) + 19, 146 }, { 147 .m_bank_id = AMLOGIC_GPIO_F, 148 .m_bit_offs = 4, 149 .sid = (AMLOGIC_GPIO_D << 8) + 6, 150 .eid = (AMLOGIC_GPIO_D << 8) + 6, 151 }, 152 }; 153 154 static const struct aml_pctl_data s6_priv_data = { 155 .number = ARRAY_SIZE(multi_mux_s6), 156 .p_mux = multi_mux_s6, 157 }; 158 159 static int aml_pmx_calc_reg_and_offset(struct pinctrl_gpio_range *range, 160 unsigned int pin, unsigned int *reg, 161 unsigned int *offset) 162 { 163 unsigned int shift; 164 165 shift = ((pin - range->pin_base) << 2) + *offset; 166 *reg = (shift / 32) * 4; 167 *offset = shift % 32; 168 169 return 0; 170 } 171 172 static int aml_pctl_set_function(struct aml_pinctrl *info, 173 struct pinctrl_gpio_range *range, 174 int pin_id, int func) 175 { 176 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 177 unsigned int shift; 178 int reg; 179 int i; 180 unsigned int offset = bank->mux_bit_offs; 181 const struct multi_mux *p_mux; 182 183 /* peculiar mux reg set */ 184 if (bank->p_mux) { 185 p_mux = bank->p_mux; 186 if (pin_id >= p_mux->sid && pin_id <= p_mux->eid) { 187 bank = NULL; 188 for (i = 0; i < info->nbanks; i++) { 189 if (info->banks[i].bank_id == p_mux->m_bank_id) { 190 bank = &info->banks[i]; 191 break; 192 } 193 } 194 195 if (!bank || !bank->reg_mux) 196 return -EINVAL; 197 198 shift = (pin_id - p_mux->sid) << 2; 199 reg = (shift / 32) * 4; 200 offset = shift % 32; 201 return regmap_update_bits(bank->reg_mux, reg, 202 0xf << offset, (func & 0xf) << offset); 203 } 204 } 205 206 /* normal mux reg set */ 207 if (!bank->reg_mux) 208 return 0; 209 210 aml_pmx_calc_reg_and_offset(range, pin_id, ®, &offset); 211 return regmap_update_bits(bank->reg_mux, reg, 212 0xf << offset, (func & 0xf) << offset); 213 } 214 215 static int aml_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 216 { 217 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 218 219 return info->nfunctions; 220 } 221 222 static const char *aml_pmx_get_fname(struct pinctrl_dev *pctldev, 223 unsigned int selector) 224 { 225 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 226 227 return info->functions[selector].name; 228 } 229 230 static int aml_pmx_get_groups(struct pinctrl_dev *pctldev, 231 unsigned int selector, 232 const char * const **grps, 233 unsigned * const ngrps) 234 { 235 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 236 237 *grps = info->functions[selector].groups; 238 *ngrps = info->functions[selector].ngroups; 239 240 return 0; 241 } 242 243 static int aml_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned int fselector, 244 unsigned int group_id) 245 { 246 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 247 struct aml_pctl_group *group = &info->groups[group_id]; 248 struct pinctrl_gpio_range *range; 249 int i; 250 251 for (i = 0; i < group->npins; i++) { 252 range = pinctrl_find_gpio_range_from_pin(pctldev, group->pins[i]); 253 aml_pctl_set_function(info, range, group->pins[i], group->func[i]); 254 } 255 256 return 0; 257 } 258 259 static int aml_pmx_request_gpio(struct pinctrl_dev *pctldev, 260 struct pinctrl_gpio_range *range, 261 unsigned int pin) 262 { 263 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 264 265 return aml_pctl_set_function(info, range, pin, 0); 266 } 267 268 static const struct pinmux_ops aml_pmx_ops = { 269 .set_mux = aml_pmx_set_mux, 270 .get_functions_count = aml_pmx_get_funcs_count, 271 .get_function_name = aml_pmx_get_fname, 272 .get_function_groups = aml_pmx_get_groups, 273 .gpio_request_enable = aml_pmx_request_gpio, 274 }; 275 276 static int aml_calc_reg_and_bit(struct pinctrl_gpio_range *range, 277 unsigned int pin, 278 unsigned int reg_type, 279 unsigned int *reg, unsigned int *bit) 280 { 281 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 282 283 *bit = (pin - range->pin_base) * aml_bit_strides[reg_type] 284 + bank->pc.bit_offset[reg_type]; 285 *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; 286 *bit &= 0x1f; 287 288 return 0; 289 } 290 291 static int aml_pinconf_get_pull(struct aml_pinctrl *info, unsigned int pin) 292 { 293 struct pinctrl_gpio_range *range = 294 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 295 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 296 unsigned int reg, bit, val; 297 int ret, conf; 298 299 aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); 300 301 ret = regmap_read(bank->reg_gpio, reg, &val); 302 if (ret) 303 return ret; 304 305 if (!(val & BIT(bit))) { 306 conf = PIN_CONFIG_BIAS_DISABLE; 307 } else { 308 aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); 309 310 ret = regmap_read(bank->reg_gpio, reg, &val); 311 if (ret) 312 return ret; 313 314 if (val & BIT(bit)) 315 conf = PIN_CONFIG_BIAS_PULL_UP; 316 else 317 conf = PIN_CONFIG_BIAS_PULL_DOWN; 318 } 319 320 return conf; 321 } 322 323 static int aml_pinconf_get_drive_strength(struct aml_pinctrl *info, 324 unsigned int pin, 325 u16 *drive_strength_ua) 326 { 327 struct pinctrl_gpio_range *range = 328 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 329 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 330 unsigned int reg, bit; 331 unsigned int val; 332 int ret; 333 334 if (!bank->reg_ds) 335 return -EOPNOTSUPP; 336 337 aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); 338 ret = regmap_read(bank->reg_ds, reg, &val); 339 if (ret) 340 return ret; 341 342 switch ((val >> bit) & 0x3) { 343 case PINCONF_DRV_500UA: 344 *drive_strength_ua = 500; 345 break; 346 case PINCONF_DRV_2500UA: 347 *drive_strength_ua = 2500; 348 break; 349 case PINCONF_DRV_3000UA: 350 *drive_strength_ua = 3000; 351 break; 352 case PINCONF_DRV_4000UA: 353 *drive_strength_ua = 4000; 354 break; 355 default: 356 return -EINVAL; 357 } 358 359 return 0; 360 } 361 362 static int aml_pinconf_get_gpio_bit(struct aml_pinctrl *info, 363 unsigned int pin, 364 unsigned int reg_type) 365 { 366 struct pinctrl_gpio_range *range = 367 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 368 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 369 unsigned int reg, bit, val; 370 int ret; 371 372 aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); 373 ret = regmap_read(bank->reg_gpio, reg, &val); 374 if (ret) 375 return ret; 376 377 return BIT(bit) & val ? 1 : 0; 378 } 379 380 static int aml_pinconf_get_output(struct aml_pinctrl *info, 381 unsigned int pin) 382 { 383 int ret = aml_pinconf_get_gpio_bit(info, pin, AML_REG_DIR); 384 385 if (ret < 0) 386 return ret; 387 388 return !ret; 389 } 390 391 static int aml_pinconf_get_drive(struct aml_pinctrl *info, 392 unsigned int pin) 393 { 394 return aml_pinconf_get_gpio_bit(info, pin, AML_REG_OUT); 395 } 396 397 static int aml_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, 398 unsigned long *config) 399 { 400 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); 401 enum pin_config_param param = pinconf_to_config_param(*config); 402 u16 arg; 403 int ret; 404 405 switch (param) { 406 case PIN_CONFIG_BIAS_DISABLE: 407 case PIN_CONFIG_BIAS_PULL_DOWN: 408 case PIN_CONFIG_BIAS_PULL_UP: 409 if (aml_pinconf_get_pull(info, pin) == param) 410 arg = 1; 411 else 412 return -EINVAL; 413 break; 414 case PIN_CONFIG_DRIVE_STRENGTH_UA: 415 ret = aml_pinconf_get_drive_strength(info, pin, &arg); 416 if (ret) 417 return ret; 418 break; 419 case PIN_CONFIG_OUTPUT_ENABLE: 420 ret = aml_pinconf_get_output(info, pin); 421 if (ret <= 0) 422 return -EINVAL; 423 arg = 1; 424 break; 425 case PIN_CONFIG_OUTPUT: 426 ret = aml_pinconf_get_output(info, pin); 427 if (ret <= 0) 428 return -EINVAL; 429 430 ret = aml_pinconf_get_drive(info, pin); 431 if (ret < 0) 432 return -EINVAL; 433 434 arg = ret; 435 break; 436 437 default: 438 return -ENOTSUPP; 439 } 440 441 *config = pinconf_to_config_packed(param, arg); 442 dev_dbg(info->dev, "pinconf for pin %u is %lu\n", pin, *config); 443 444 return 0; 445 } 446 447 static int aml_pinconf_disable_bias(struct aml_pinctrl *info, 448 unsigned int pin) 449 { 450 struct pinctrl_gpio_range *range = 451 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 452 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 453 unsigned int reg, bit = 0; 454 455 aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); 456 457 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); 458 } 459 460 static int aml_pinconf_enable_bias(struct aml_pinctrl *info, unsigned int pin, 461 bool pull_up) 462 { 463 struct pinctrl_gpio_range *range = 464 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 465 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 466 unsigned int reg, bit, val = 0; 467 int ret; 468 469 aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); 470 if (pull_up) 471 val = BIT(bit); 472 473 ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), val); 474 if (ret) 475 return ret; 476 477 aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); 478 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); 479 } 480 481 static int aml_pinconf_set_drive_strength(struct aml_pinctrl *info, 482 unsigned int pin, 483 u16 drive_strength_ua) 484 { 485 struct pinctrl_gpio_range *range = 486 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 487 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 488 unsigned int reg, bit, ds_val; 489 490 if (!bank->reg_ds) { 491 dev_err(info->dev, "drive-strength not supported\n"); 492 return -EOPNOTSUPP; 493 } 494 495 aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); 496 497 if (drive_strength_ua <= 500) { 498 ds_val = PINCONF_DRV_500UA; 499 } else if (drive_strength_ua <= 2500) { 500 ds_val = PINCONF_DRV_2500UA; 501 } else if (drive_strength_ua <= 3000) { 502 ds_val = PINCONF_DRV_3000UA; 503 } else if (drive_strength_ua <= 4000) { 504 ds_val = PINCONF_DRV_4000UA; 505 } else { 506 dev_warn_once(info->dev, 507 "pin %u: invalid drive-strength : %d , default to 4mA\n", 508 pin, drive_strength_ua); 509 ds_val = PINCONF_DRV_4000UA; 510 } 511 512 return regmap_update_bits(bank->reg_ds, reg, 0x3 << bit, ds_val << bit); 513 } 514 515 static int aml_pinconf_set_gpio_bit(struct aml_pinctrl *info, 516 unsigned int pin, 517 unsigned int reg_type, 518 bool arg) 519 { 520 struct pinctrl_gpio_range *range = 521 pinctrl_find_gpio_range_from_pin(info->pctl, pin); 522 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); 523 unsigned int reg, bit; 524 525 aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); 526 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 527 arg ? BIT(bit) : 0); 528 } 529 530 static int aml_pinconf_set_output(struct aml_pinctrl *info, 531 unsigned int pin, 532 bool out) 533 { 534 return aml_pinconf_set_gpio_bit(info, pin, AML_REG_DIR, !out); 535 } 536 537 static int aml_pinconf_set_drive(struct aml_pinctrl *info, 538 unsigned int pin, 539 bool high) 540 { 541 return aml_pinconf_set_gpio_bit(info, pin, AML_REG_OUT, high); 542 } 543 544 static int aml_pinconf_set_output_drive(struct aml_pinctrl *info, 545 unsigned int pin, 546 bool high) 547 { 548 int ret; 549 550 ret = aml_pinconf_set_output(info, pin, true); 551 if (ret) 552 return ret; 553 554 return aml_pinconf_set_drive(info, pin, high); 555 } 556 557 static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, 558 unsigned long *configs, unsigned int num_configs) 559 { 560 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); 561 enum pin_config_param param; 562 unsigned int arg = 0; 563 int i, ret; 564 565 for (i = 0; i < num_configs; i++) { 566 param = pinconf_to_config_param(configs[i]); 567 568 switch (param) { 569 case PIN_CONFIG_DRIVE_STRENGTH_UA: 570 case PIN_CONFIG_OUTPUT_ENABLE: 571 case PIN_CONFIG_OUTPUT: 572 arg = pinconf_to_config_argument(configs[i]); 573 break; 574 575 default: 576 break; 577 } 578 579 switch (param) { 580 case PIN_CONFIG_BIAS_DISABLE: 581 ret = aml_pinconf_disable_bias(info, pin); 582 break; 583 case PIN_CONFIG_BIAS_PULL_UP: 584 ret = aml_pinconf_enable_bias(info, pin, true); 585 break; 586 case PIN_CONFIG_BIAS_PULL_DOWN: 587 ret = aml_pinconf_enable_bias(info, pin, false); 588 break; 589 case PIN_CONFIG_DRIVE_STRENGTH_UA: 590 ret = aml_pinconf_set_drive_strength(info, pin, arg); 591 break; 592 case PIN_CONFIG_OUTPUT_ENABLE: 593 ret = aml_pinconf_set_output(info, pin, arg); 594 break; 595 case PIN_CONFIG_OUTPUT: 596 ret = aml_pinconf_set_output_drive(info, pin, arg); 597 break; 598 default: 599 ret = -ENOTSUPP; 600 } 601 602 if (ret) 603 return ret; 604 } 605 606 return 0; 607 } 608 609 static int aml_pinconf_group_set(struct pinctrl_dev *pcdev, 610 unsigned int num_group, 611 unsigned long *configs, 612 unsigned int num_configs) 613 { 614 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); 615 int i; 616 617 for (i = 0; i < info->groups[num_group].npins; i++) { 618 aml_pinconf_set(pcdev, info->groups[num_group].pins[i], configs, 619 num_configs); 620 } 621 622 return 0; 623 } 624 625 static int aml_pinconf_group_get(struct pinctrl_dev *pcdev, 626 unsigned int group, unsigned long *config) 627 { 628 return -EOPNOTSUPP; 629 } 630 631 static const struct pinconf_ops aml_pinconf_ops = { 632 .pin_config_get = aml_pinconf_get, 633 .pin_config_set = aml_pinconf_set, 634 .pin_config_group_get = aml_pinconf_group_get, 635 .pin_config_group_set = aml_pinconf_group_set, 636 .is_generic = true, 637 }; 638 639 static int aml_get_groups_count(struct pinctrl_dev *pctldev) 640 { 641 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 642 643 return info->ngroups; 644 } 645 646 static const char *aml_get_group_name(struct pinctrl_dev *pctldev, 647 unsigned int selector) 648 { 649 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 650 651 return info->groups[selector].name; 652 } 653 654 static int aml_get_group_pins(struct pinctrl_dev *pctldev, 655 unsigned int selector, const unsigned int **pins, 656 unsigned int *npins) 657 { 658 struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 659 660 if (selector >= info->ngroups) 661 return -EINVAL; 662 663 *pins = info->groups[selector].pins; 664 *npins = info->groups[selector].npins; 665 666 return 0; 667 } 668 669 static void aml_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, 670 unsigned int offset) 671 { 672 seq_printf(s, " %s", dev_name(pcdev->dev)); 673 } 674 675 static const struct pinctrl_ops aml_pctrl_ops = { 676 .get_groups_count = aml_get_groups_count, 677 .get_group_name = aml_get_group_name, 678 .get_group_pins = aml_get_group_pins, 679 .dt_node_to_map = pinconf_generic_dt_node_to_map_pinmux, 680 .dt_free_map = pinconf_generic_dt_free_map, 681 .pin_dbg_show = aml_pin_dbg_show, 682 }; 683 684 static int aml_pctl_parse_functions(struct device_node *np, 685 struct aml_pinctrl *info, u32 index, 686 int *grp_index) 687 { 688 struct device *dev = info->dev; 689 struct aml_pmx_func *func; 690 struct aml_pctl_group *grp; 691 int ret, i; 692 693 func = &info->functions[index]; 694 func->name = np->name; 695 func->ngroups = of_get_child_count(np); 696 if (func->ngroups == 0) 697 return dev_err_probe(dev, -EINVAL, "No groups defined\n"); 698 699 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 700 if (!func->groups) 701 return -ENOMEM; 702 703 i = 0; 704 for_each_child_of_node_scoped(np, child) { 705 func->groups[i++] = child->name; 706 grp = &info->groups[*grp_index]; 707 grp->name = child->name; 708 *grp_index += 1; 709 ret = pinconf_generic_parse_dt_pinmux(child, dev, &grp->pins, 710 &grp->func, &grp->npins); 711 if (ret) { 712 dev_err(dev, "function :%s, groups:%s fail\n", func->name, child->name); 713 return ret; 714 } 715 } 716 dev_dbg(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); 717 718 return 0; 719 } 720 721 static u32 aml_bank_pins(struct device_node *np) 722 { 723 struct of_phandle_args of_args; 724 725 if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 726 0, &of_args)) 727 return 0; 728 else 729 return of_args.args[2]; 730 } 731 732 static int aml_bank_number(struct device_node *np) 733 { 734 struct of_phandle_args of_args; 735 736 if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 737 0, &of_args)) 738 return -EINVAL; 739 else 740 return of_args.args[1] >> 8; 741 } 742 743 static unsigned int aml_count_pins(struct device_node *np) 744 { 745 struct device_node *child; 746 unsigned int pins = 0; 747 748 for_each_child_of_node(np, child) { 749 if (of_property_read_bool(child, "gpio-controller")) 750 pins += aml_bank_pins(child); 751 } 752 753 return pins; 754 } 755 756 /* 757 * A pinctrl device contains two types of nodes. The one named GPIO 758 * bank which includes gpio-controller property. The other one named 759 * function which includes one or more pin groups. The pin group 760 * include pinmux property(global index in pinctrl dev, and mux vlaue 761 * in mux reg) and pin configuration properties. 762 */ 763 static void aml_pctl_dt_child_count(struct aml_pinctrl *info, 764 struct device_node *np) 765 { 766 struct device_node *child; 767 768 for_each_child_of_node(np, child) { 769 if (of_property_read_bool(child, "gpio-controller")) { 770 info->nbanks++; 771 } else { 772 info->nfunctions++; 773 info->ngroups += of_get_child_count(child); 774 } 775 } 776 } 777 778 static struct regmap *aml_map_resource(struct device *dev, unsigned int id, 779 struct device_node *node, char *name) 780 { 781 struct resource res; 782 void __iomem *base; 783 int i; 784 785 struct regmap_config aml_regmap_config = { 786 .reg_bits = 32, 787 .val_bits = 32, 788 .reg_stride = 4, 789 }; 790 791 i = of_property_match_string(node, "reg-names", name); 792 if (i < 0) 793 return NULL; 794 if (of_address_to_resource(node, i, &res)) 795 return NULL; 796 base = devm_ioremap_resource(dev, &res); 797 if (IS_ERR(base)) 798 return ERR_CAST(base); 799 800 aml_regmap_config.max_register = resource_size(&res) - 4; 801 aml_regmap_config.name = devm_kasprintf(dev, GFP_KERNEL, 802 "%s-%s", aml_bank_name[id], name); 803 if (!aml_regmap_config.name) 804 return ERR_PTR(-ENOMEM); 805 806 return devm_regmap_init_mmio(dev, base, &aml_regmap_config); 807 } 808 809 static inline int aml_gpio_calc_reg_and_bit(struct aml_gpio_bank *bank, 810 unsigned int reg_type, 811 unsigned int gpio, 812 unsigned int *reg, 813 unsigned int *bit) 814 { 815 *bit = gpio * aml_bit_strides[reg_type] + bank->pc.bit_offset[reg_type]; 816 *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; 817 *bit &= 0x1f; 818 819 return 0; 820 } 821 822 static int aml_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) 823 { 824 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 825 unsigned int bit, reg, val; 826 int ret; 827 828 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); 829 830 ret = regmap_read(bank->reg_gpio, reg, &val); 831 if (ret) 832 return ret; 833 834 return BIT(bit) & val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 835 } 836 837 static int aml_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) 838 { 839 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 840 unsigned int bit, reg; 841 842 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); 843 844 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); 845 } 846 847 static int aml_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, 848 int value) 849 { 850 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 851 unsigned int bit, reg; 852 int ret; 853 854 aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); 855 ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); 856 if (ret < 0) 857 return ret; 858 859 aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); 860 861 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 862 value ? BIT(bit) : 0); 863 } 864 865 static int aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) 866 { 867 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 868 unsigned int bit, reg; 869 870 aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); 871 872 return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 873 value ? BIT(bit) : 0); 874 } 875 876 static int aml_gpio_get(struct gpio_chip *chip, unsigned int gpio) 877 { 878 struct aml_gpio_bank *bank = gpiochip_get_data(chip); 879 unsigned int reg, bit, val; 880 881 aml_gpio_calc_reg_and_bit(bank, AML_REG_IN, gpio, ®, &bit); 882 regmap_read(bank->reg_gpio, reg, &val); 883 884 return !!(val & BIT(bit)); 885 } 886 887 static const struct gpio_chip aml_gpio_template = { 888 .request = gpiochip_generic_request, 889 .free = gpiochip_generic_free, 890 .set_config = gpiochip_generic_config, 891 .set = aml_gpio_set, 892 .get = aml_gpio_get, 893 .direction_input = aml_gpio_direction_input, 894 .direction_output = aml_gpio_direction_output, 895 .get_direction = aml_gpio_get_direction, 896 .can_sleep = false, 897 }; 898 899 static void init_bank_register_bit(struct aml_pinctrl *info, 900 struct aml_gpio_bank *bank) 901 { 902 const struct aml_pctl_data *data = info->data; 903 const struct multi_mux *p_mux; 904 int i; 905 906 for (i = 0; i < AML_NUM_REG; i++) { 907 bank->pc.reg_offset[i] = aml_def_regoffs[i]; 908 bank->pc.bit_offset[i] = 0; 909 } 910 911 bank->mux_bit_offs = 0; 912 913 if (data) { 914 for (i = 0; i < data->number; i++) { 915 p_mux = &data->p_mux[i]; 916 if (bank->bank_id == p_mux->m_bank_id) { 917 bank->mux_bit_offs = p_mux->m_bit_offs; 918 break; 919 } 920 if (p_mux->sid >> 8 == bank->bank_id) { 921 bank->p_mux = p_mux; 922 break; 923 } 924 } 925 } 926 } 927 928 static int aml_gpiolib_register_bank(struct aml_pinctrl *info, 929 int bank_nr, struct device_node *np) 930 { 931 struct aml_gpio_bank *bank = &info->banks[bank_nr]; 932 struct device *dev = info->dev; 933 int ret = 0; 934 935 ret = aml_bank_number(np); 936 if (ret < 0) { 937 dev_err(dev, "get num=%d bank identity fail\n", bank_nr); 938 return -EINVAL; 939 } 940 bank->bank_id = ret; 941 942 bank->reg_mux = aml_map_resource(dev, bank->bank_id, np, "mux"); 943 if (IS_ERR_OR_NULL(bank->reg_mux)) { 944 if (bank->bank_id == AMLOGIC_GPIO_TEST_N || 945 bank->bank_id == AMLOGIC_GPIO_ANALOG) 946 bank->reg_mux = NULL; 947 else 948 return dev_err_probe(dev, bank->reg_mux ? PTR_ERR(bank->reg_mux) : -ENOENT, 949 "mux registers not found\n"); 950 } 951 952 bank->reg_gpio = aml_map_resource(dev, bank->bank_id, np, "gpio"); 953 if (IS_ERR_OR_NULL(bank->reg_gpio)) 954 return dev_err_probe(dev, bank->reg_gpio ? PTR_ERR(bank->reg_gpio) : -ENOENT, 955 "gpio registers not found\n"); 956 957 bank->reg_ds = aml_map_resource(dev, bank->bank_id, np, "ds"); 958 if (IS_ERR_OR_NULL(bank->reg_ds)) { 959 dev_dbg(info->dev, "ds registers not found - skipping\n"); 960 bank->reg_ds = bank->reg_gpio; 961 } 962 963 bank->gpio_chip = aml_gpio_template; 964 bank->gpio_chip.base = -1; 965 bank->gpio_chip.ngpio = aml_bank_pins(np); 966 bank->gpio_chip.fwnode = of_fwnode_handle(np); 967 bank->gpio_chip.parent = dev; 968 969 init_bank_register_bit(info, bank); 970 bank->gpio_chip.label = aml_bank_name[bank->bank_id]; 971 972 bank->pin_base = bank->bank_id << 8; 973 974 return 0; 975 } 976 977 static int aml_pctl_probe_dt(struct platform_device *pdev, 978 struct pinctrl_desc *pctl_desc, 979 struct aml_pinctrl *info) 980 { 981 struct device *dev = &pdev->dev; 982 struct pinctrl_pin_desc *pdesc; 983 struct device_node *np = dev->of_node; 984 int grp_index = 0; 985 int i = 0, j = 0, k = 0, bank; 986 int ret = 0; 987 988 aml_pctl_dt_child_count(info, np); 989 if (!info->nbanks) 990 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); 991 992 dev_dbg(dev, "nbanks = %d\n", info->nbanks); 993 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); 994 dev_dbg(dev, "ngroups = %d\n", info->ngroups); 995 996 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 997 998 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 999 1000 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); 1001 1002 if (!info->functions || !info->groups || !info->banks) 1003 return -ENOMEM; 1004 1005 info->data = (struct aml_pctl_data *)of_device_get_match_data(dev); 1006 1007 pctl_desc->npins = aml_count_pins(np); 1008 1009 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); 1010 if (!pdesc) 1011 return -ENOMEM; 1012 1013 pctl_desc->pins = pdesc; 1014 1015 bank = 0; 1016 for_each_child_of_node_scoped(np, child) { 1017 if (of_property_read_bool(child, "gpio-controller")) { 1018 const char *bank_name = NULL; 1019 char **pin_names; 1020 1021 ret = aml_gpiolib_register_bank(info, bank, child); 1022 if (ret) 1023 return ret; 1024 1025 k = info->banks[bank].pin_base; 1026 bank_name = info->banks[bank].gpio_chip.label; 1027 1028 pin_names = devm_kasprintf_strarray(dev, bank_name, 1029 info->banks[bank].gpio_chip.ngpio); 1030 if (IS_ERR(pin_names)) 1031 return PTR_ERR(pin_names); 1032 1033 for (j = 0; j < info->banks[bank].gpio_chip.ngpio; j++, k++) { 1034 pdesc->number = k; 1035 pdesc->name = pin_names[j]; 1036 pdesc++; 1037 } 1038 bank++; 1039 } else { 1040 ret = aml_pctl_parse_functions(child, info, 1041 i++, &grp_index); 1042 if (ret) 1043 return ret; 1044 } 1045 } 1046 1047 return 0; 1048 } 1049 1050 static int aml_pctl_probe(struct platform_device *pdev) 1051 { 1052 struct device *dev = &pdev->dev; 1053 struct aml_pinctrl *info; 1054 struct pinctrl_desc *pctl_desc; 1055 int ret, i; 1056 1057 pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); 1058 if (!pctl_desc) 1059 return -ENOMEM; 1060 1061 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1062 if (!info) 1063 return -ENOMEM; 1064 1065 info->dev = dev; 1066 platform_set_drvdata(pdev, info); 1067 ret = aml_pctl_probe_dt(pdev, pctl_desc, info); 1068 if (ret) 1069 return ret; 1070 1071 pctl_desc->owner = THIS_MODULE; 1072 pctl_desc->pctlops = &aml_pctrl_ops; 1073 pctl_desc->pmxops = &aml_pmx_ops; 1074 pctl_desc->confops = &aml_pinconf_ops; 1075 pctl_desc->name = dev_name(dev); 1076 1077 info->pctl = devm_pinctrl_register(dev, pctl_desc, info); 1078 if (IS_ERR(info->pctl)) 1079 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); 1080 1081 for (i = 0; i < info->nbanks; i++) { 1082 ret = gpiochip_add_data(&info->banks[i].gpio_chip, &info->banks[i]); 1083 if (ret) 1084 return dev_err_probe(dev, ret, "Failed to add gpiochip(%d)!\n", i); 1085 } 1086 1087 return 0; 1088 } 1089 1090 static const struct of_device_id aml_pctl_of_match[] = { 1091 { .compatible = "amlogic,pinctrl-a4", }, 1092 { .compatible = "amlogic,pinctrl-s7", .data = &s7_priv_data, }, 1093 { .compatible = "amlogic,pinctrl-s6", .data = &s6_priv_data, }, 1094 { /* sentinel */ } 1095 }; 1096 MODULE_DEVICE_TABLE(of, aml_pctl_dt_match); 1097 1098 static struct platform_driver aml_pctl_driver = { 1099 .driver = { 1100 .name = "amlogic-pinctrl", 1101 .of_match_table = aml_pctl_of_match, 1102 }, 1103 .probe = aml_pctl_probe, 1104 }; 1105 module_platform_driver(aml_pctl_driver); 1106 1107 MODULE_AUTHOR("Xianwei Zhao <xianwei.zhao@amlogic.com>"); 1108 MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic SoC"); 1109 MODULE_LICENSE("Dual BSD/GPL"); 1110