1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver. 4 * Copyright (c) 2014 MediaTek Inc. 5 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> 6 */ 7 8 #include <linux/io.h> 9 #include <linux/gpio/driver.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_irq.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/pinctrl/machine.h> 15 #include <linux/pinctrl/pinconf.h> 16 #include <linux/pinctrl/pinconf-generic.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/bitops.h> 22 #include <linux/regmap.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/pm.h> 27 #include <dt-bindings/pinctrl/mt65xx.h> 28 29 #include "../core.h" 30 #include "../pinconf.h" 31 #include "../pinctrl-utils.h" 32 #include "mtk-eint.h" 33 #include "pinctrl-mtk-common.h" 34 35 #define GPIO_MODE_BITS 3 36 #define GPIO_MODE_PREFIX "GPIO" 37 38 static const char * const mtk_gpio_functions[] = { 39 "func0", "func1", "func2", "func3", 40 "func4", "func5", "func6", "func7", 41 "func8", "func9", "func10", "func11", 42 "func12", "func13", "func14", "func15", 43 }; 44 45 /* 46 * There are two base address for pull related configuration 47 * in mt8135, and different GPIO pins use different base address. 48 * When pin number greater than type1_start and less than type1_end, 49 * should use the second base address. 50 */ 51 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, 52 unsigned long pin) 53 { 54 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) 55 return pctl->regmap2; 56 return pctl->regmap1; 57 } 58 59 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin) 60 { 61 /* Different SoC has different mask and port shift. */ 62 return ((pin >> pctl->devdata->mode_shf) & pctl->devdata->port_mask) 63 << pctl->devdata->port_shf; 64 } 65 66 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 67 struct pinctrl_gpio_range *range, unsigned offset, 68 bool input) 69 { 70 unsigned int reg_addr; 71 unsigned int bit; 72 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 73 74 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; 75 bit = BIT(offset & pctl->devdata->mode_mask); 76 77 if (pctl->devdata->spec_dir_set) 78 pctl->devdata->spec_dir_set(®_addr, offset); 79 80 if (input) 81 /* Different SoC has different alignment offset. */ 82 reg_addr = CLR_ADDR(reg_addr, pctl); 83 else 84 reg_addr = SET_ADDR(reg_addr, pctl); 85 86 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); 87 return 0; 88 } 89 90 static int mtk_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 91 { 92 unsigned int reg_addr; 93 unsigned int bit; 94 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 95 96 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset; 97 bit = BIT(offset & pctl->devdata->mode_mask); 98 99 if (value) 100 reg_addr = SET_ADDR(reg_addr, pctl); 101 else 102 reg_addr = CLR_ADDR(reg_addr, pctl); 103 104 return regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); 105 } 106 107 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, 108 int value, enum pin_config_param arg) 109 { 110 unsigned int reg_addr, offset; 111 unsigned int bit; 112 113 /** 114 * Due to some soc are not support ies/smt config, add this special 115 * control to handle it. 116 */ 117 if (!pctl->devdata->spec_ies_smt_set && 118 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT && 119 arg == PIN_CONFIG_INPUT_ENABLE) 120 return -EINVAL; 121 122 if (!pctl->devdata->spec_ies_smt_set && 123 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT && 124 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) 125 return -EINVAL; 126 127 /* 128 * Due to some pins are irregular, their input enable and smt 129 * control register are discontinuous, so we need this special handle. 130 */ 131 if (pctl->devdata->spec_ies_smt_set) { 132 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), 133 pctl->devdata, pin, value, arg); 134 } 135 136 if (arg == PIN_CONFIG_INPUT_ENABLE) 137 offset = pctl->devdata->ies_offset; 138 else 139 offset = pctl->devdata->smt_offset; 140 141 bit = BIT(offset & pctl->devdata->mode_mask); 142 143 if (value) 144 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl); 145 else 146 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); 147 148 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); 149 return 0; 150 } 151 152 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, 153 const struct mtk_pinctrl_devdata *devdata, 154 unsigned int pin, int value, enum pin_config_param arg) 155 { 156 const struct mtk_pin_ies_smt_set *ies_smt_infos = NULL; 157 unsigned int i, info_num, reg_addr, bit; 158 159 switch (arg) { 160 case PIN_CONFIG_INPUT_ENABLE: 161 ies_smt_infos = devdata->spec_ies; 162 info_num = devdata->n_spec_ies; 163 break; 164 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 165 ies_smt_infos = devdata->spec_smt; 166 info_num = devdata->n_spec_smt; 167 break; 168 default: 169 break; 170 } 171 172 if (!ies_smt_infos) 173 return -EINVAL; 174 175 for (i = 0; i < info_num; i++) { 176 if (pin >= ies_smt_infos[i].start && 177 pin <= ies_smt_infos[i].end) { 178 break; 179 } 180 } 181 182 if (i == info_num) 183 return -EINVAL; 184 185 if (value) 186 reg_addr = ies_smt_infos[i].offset + devdata->port_align; 187 else 188 reg_addr = ies_smt_infos[i].offset + (devdata->port_align << 1); 189 190 bit = BIT(ies_smt_infos[i].bit); 191 regmap_write(regmap, reg_addr, bit); 192 return 0; 193 } 194 EXPORT_SYMBOL_NS_GPL(mtk_pconf_spec_set_ies_smt_range, "MTK_PINCTRL"); 195 196 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( 197 struct mtk_pinctrl *pctl, unsigned long pin) { 198 int i; 199 200 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) { 201 const struct mtk_pin_drv_grp *pin_drv = 202 pctl->devdata->pin_drv_grp + i; 203 if (pin == pin_drv->pin) 204 return pin_drv; 205 } 206 207 return NULL; 208 } 209 210 static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, 211 unsigned int pin, unsigned char driving) 212 { 213 const struct mtk_pin_drv_grp *pin_drv; 214 unsigned int val; 215 unsigned int bits, mask, shift; 216 const struct mtk_drv_group_desc *drv_grp; 217 218 if (pin >= pctl->devdata->npins) 219 return -EINVAL; 220 221 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin); 222 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls) 223 return -EINVAL; 224 225 drv_grp = pctl->devdata->grp_desc + pin_drv->grp; 226 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv 227 && !(driving % drv_grp->step)) { 228 val = driving / drv_grp->step - 1; 229 bits = drv_grp->high_bit - drv_grp->low_bit + 1; 230 mask = BIT(bits) - 1; 231 shift = pin_drv->bit + drv_grp->low_bit; 232 mask <<= shift; 233 val <<= shift; 234 return regmap_update_bits(mtk_get_regmap(pctl, pin), 235 pin_drv->offset, mask, val); 236 } 237 238 return -EINVAL; 239 } 240 241 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, 242 const struct mtk_pinctrl_devdata *devdata, 243 unsigned int pin, bool isup, unsigned int r1r0) 244 { 245 unsigned int i; 246 unsigned int reg_pupd, reg_set, reg_rst; 247 unsigned int bit_pupd, bit_r0, bit_r1; 248 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin; 249 bool find = false; 250 251 if (!devdata->spec_pupd) 252 return -EINVAL; 253 254 for (i = 0; i < devdata->n_spec_pupd; i++) { 255 if (pin == devdata->spec_pupd[i].pin) { 256 find = true; 257 break; 258 } 259 } 260 261 if (!find) 262 return -EINVAL; 263 264 spec_pupd_pin = devdata->spec_pupd + i; 265 reg_set = spec_pupd_pin->offset + devdata->port_align; 266 reg_rst = spec_pupd_pin->offset + (devdata->port_align << 1); 267 268 if (isup) 269 reg_pupd = reg_rst; 270 else 271 reg_pupd = reg_set; 272 273 bit_pupd = BIT(spec_pupd_pin->pupd_bit); 274 regmap_write(regmap, reg_pupd, bit_pupd); 275 276 bit_r0 = BIT(spec_pupd_pin->r0_bit); 277 bit_r1 = BIT(spec_pupd_pin->r1_bit); 278 279 switch (r1r0) { 280 case MTK_PUPD_SET_R1R0_00: 281 regmap_write(regmap, reg_rst, bit_r0); 282 regmap_write(regmap, reg_rst, bit_r1); 283 break; 284 case MTK_PUPD_SET_R1R0_01: 285 regmap_write(regmap, reg_set, bit_r0); 286 regmap_write(regmap, reg_rst, bit_r1); 287 break; 288 case MTK_PUPD_SET_R1R0_10: 289 regmap_write(regmap, reg_rst, bit_r0); 290 regmap_write(regmap, reg_set, bit_r1); 291 break; 292 case MTK_PUPD_SET_R1R0_11: 293 regmap_write(regmap, reg_set, bit_r0); 294 regmap_write(regmap, reg_set, bit_r1); 295 break; 296 default: 297 return -EINVAL; 298 } 299 300 return 0; 301 } 302 EXPORT_SYMBOL_NS_GPL(mtk_pctrl_spec_pull_set_samereg, "MTK_PINCTRL"); 303 304 static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, 305 unsigned int pin, bool enable, bool isup, unsigned int arg) 306 { 307 unsigned int bit; 308 unsigned int reg_pullen, reg_pullsel, r1r0; 309 int ret; 310 311 /* Some pins' pull setting are very different, 312 * they have separate pull up/down bit, R0 and R1 313 * resistor bit, so we need this special handle. 314 */ 315 if (pctl->devdata->spec_pull_set) { 316 /* For special pins, bias-disable is set by R1R0, 317 * the parameter should be "MTK_PUPD_SET_R1R0_00". 318 */ 319 r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00; 320 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), 321 pctl->devdata, pin, isup, 322 r1r0); 323 if (!ret) 324 return 0; 325 } 326 327 /* For generic pull config, default arg value should be 0 or 1. */ 328 if (arg != 0 && arg != 1) { 329 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", 330 arg, pin); 331 return -EINVAL; 332 } 333 334 if (pctl->devdata->mt8365_set_clr_mode) { 335 bit = pin & pctl->devdata->mode_mask; 336 reg_pullen = mtk_get_port(pctl, pin) + 337 pctl->devdata->pullen_offset; 338 reg_pullsel = mtk_get_port(pctl, pin) + 339 pctl->devdata->pullsel_offset; 340 ret = pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin), 341 bit, reg_pullen, reg_pullsel, 342 enable, isup); 343 if (ret) 344 return -EINVAL; 345 346 return 0; 347 } 348 349 bit = BIT(pin & pctl->devdata->mode_mask); 350 if (enable) 351 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + 352 pctl->devdata->pullen_offset, pctl); 353 else 354 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) + 355 pctl->devdata->pullen_offset, pctl); 356 357 if (isup) 358 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) + 359 pctl->devdata->pullsel_offset, pctl); 360 else 361 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + 362 pctl->devdata->pullsel_offset, pctl); 363 364 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); 365 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); 366 return 0; 367 } 368 369 static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, 370 unsigned int pin, enum pin_config_param param, 371 enum pin_config_param arg) 372 { 373 int ret = 0; 374 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 375 376 switch (param) { 377 case PIN_CONFIG_BIAS_DISABLE: 378 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg); 379 break; 380 case PIN_CONFIG_BIAS_PULL_UP: 381 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg); 382 break; 383 case PIN_CONFIG_BIAS_PULL_DOWN: 384 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg); 385 break; 386 case PIN_CONFIG_INPUT_ENABLE: 387 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true); 388 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); 389 break; 390 case PIN_CONFIG_LEVEL: 391 mtk_gpio_set(pctl->chip, pin, arg); 392 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); 393 break; 394 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 395 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true); 396 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); 397 break; 398 case PIN_CONFIG_DRIVE_STRENGTH: 399 ret = mtk_pconf_set_driving(pctl, pin, arg); 400 break; 401 default: 402 ret = -EINVAL; 403 } 404 405 return ret; 406 } 407 408 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, 409 unsigned group, 410 unsigned long *config) 411 { 412 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 413 414 *config = pctl->groups[group].config; 415 416 return 0; 417 } 418 419 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 420 unsigned long *configs, unsigned num_configs) 421 { 422 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 423 struct mtk_pinctrl_group *g = &pctl->groups[group]; 424 int i, ret; 425 426 for (i = 0; i < num_configs; i++) { 427 ret = mtk_pconf_parse_conf(pctldev, g->pin, 428 pinconf_to_config_param(configs[i]), 429 pinconf_to_config_argument(configs[i])); 430 if (ret < 0) 431 return ret; 432 433 g->config = configs[i]; 434 } 435 436 return 0; 437 } 438 439 static const struct pinconf_ops mtk_pconf_ops = { 440 .pin_config_group_get = mtk_pconf_group_get, 441 .pin_config_group_set = mtk_pconf_group_set, 442 }; 443 444 static struct mtk_pinctrl_group * 445 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin) 446 { 447 int i; 448 449 for (i = 0; i < pctl->ngroups; i++) { 450 struct mtk_pinctrl_group *grp = pctl->groups + i; 451 452 if (grp->pin == pin) 453 return grp; 454 } 455 456 return NULL; 457 } 458 459 static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin( 460 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum) 461 { 462 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num; 463 const struct mtk_desc_function *func = pin->functions; 464 465 while (func && func->name) { 466 if (func->muxval == fnum) 467 return func; 468 func++; 469 } 470 471 return NULL; 472 } 473 474 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl, 475 u32 pin_num, u32 fnum) 476 { 477 int i; 478 479 for (i = 0; i < pctl->devdata->npins; i++) { 480 const struct mtk_desc_pin *pin = pctl->devdata->pins + i; 481 482 if (pin->pin.number == pin_num) { 483 const struct mtk_desc_function *func = 484 pin->functions; 485 486 while (func && func->name) { 487 if (func->muxval == fnum) 488 return true; 489 func++; 490 } 491 492 break; 493 } 494 } 495 496 return false; 497 } 498 499 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, 500 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp, 501 struct pinctrl_map **map, unsigned *reserved_maps, 502 unsigned *num_maps) 503 { 504 bool ret; 505 506 if (*num_maps == *reserved_maps) 507 return -ENOSPC; 508 509 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 510 (*map)[*num_maps].data.mux.group = grp->name; 511 512 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum); 513 if (!ret) { 514 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 515 fnum, pin); 516 return -EINVAL; 517 } 518 519 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum]; 520 (*num_maps)++; 521 522 return 0; 523 } 524 525 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 526 struct device_node *node, 527 struct pinctrl_map **map, 528 unsigned *reserved_maps, 529 unsigned *num_maps) 530 { 531 struct property *pins; 532 u32 pinfunc, pin, func; 533 int num_pins, num_funcs, maps_per_pin; 534 unsigned long *configs; 535 unsigned int num_configs; 536 bool has_config = false; 537 int i, err; 538 unsigned reserve = 0; 539 struct mtk_pinctrl_group *grp; 540 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 541 542 pins = of_find_property(node, "pinmux", NULL); 543 if (!pins) { 544 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", 545 node); 546 return -EINVAL; 547 } 548 549 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 550 &num_configs); 551 if (err) 552 return err; 553 554 if (num_configs) 555 has_config = true; 556 557 num_pins = pins->length / sizeof(u32); 558 num_funcs = num_pins; 559 maps_per_pin = 0; 560 if (num_funcs) 561 maps_per_pin++; 562 if (has_config && num_pins >= 1) 563 maps_per_pin++; 564 565 if (!num_pins || !maps_per_pin) { 566 err = -EINVAL; 567 goto exit; 568 } 569 570 reserve = num_pins * maps_per_pin; 571 572 err = pinctrl_utils_reserve_map(pctldev, map, 573 reserved_maps, num_maps, reserve); 574 if (err < 0) 575 goto exit; 576 577 for (i = 0; i < num_pins; i++) { 578 err = of_property_read_u32_index(node, "pinmux", 579 i, &pinfunc); 580 if (err) 581 goto exit; 582 583 pin = MTK_GET_PIN_NO(pinfunc); 584 func = MTK_GET_PIN_FUNC(pinfunc); 585 586 if (pin >= pctl->devdata->npins || 587 func >= ARRAY_SIZE(mtk_gpio_functions)) { 588 dev_err(pctl->dev, "invalid pins value.\n"); 589 err = -EINVAL; 590 goto exit; 591 } 592 593 grp = mtk_pctrl_find_group_by_pin(pctl, pin); 594 if (!grp) { 595 dev_err(pctl->dev, "unable to match pin %d to group\n", 596 pin); 597 err = -EINVAL; 598 goto exit; 599 } 600 601 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 602 reserved_maps, num_maps); 603 if (err < 0) 604 goto exit; 605 606 if (has_config) { 607 err = pinctrl_utils_add_map_configs(pctldev, map, 608 reserved_maps, num_maps, grp->name, 609 configs, num_configs, 610 PIN_MAP_TYPE_CONFIGS_GROUP); 611 if (err < 0) 612 goto exit; 613 } 614 } 615 616 err = 0; 617 618 exit: 619 kfree(configs); 620 return err; 621 } 622 623 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 624 struct device_node *np_config, 625 struct pinctrl_map **map, unsigned *num_maps) 626 { 627 unsigned reserved_maps; 628 int ret; 629 630 *map = NULL; 631 *num_maps = 0; 632 reserved_maps = 0; 633 634 for_each_child_of_node_scoped(np_config, np) { 635 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map, 636 &reserved_maps, num_maps); 637 if (ret < 0) { 638 pinctrl_utils_free_map(pctldev, *map, *num_maps); 639 return ret; 640 } 641 } 642 643 return 0; 644 } 645 646 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 647 { 648 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 649 650 return pctl->ngroups; 651 } 652 653 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev, 654 unsigned group) 655 { 656 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 657 658 return pctl->groups[group].name; 659 } 660 661 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 662 unsigned group, 663 const unsigned **pins, 664 unsigned *num_pins) 665 { 666 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 667 668 *pins = (unsigned *)&pctl->groups[group].pin; 669 *num_pins = 1; 670 671 return 0; 672 } 673 674 static const struct pinctrl_ops mtk_pctrl_ops = { 675 .dt_node_to_map = mtk_pctrl_dt_node_to_map, 676 .dt_free_map = pinctrl_utils_free_map, 677 .get_groups_count = mtk_pctrl_get_groups_count, 678 .get_group_name = mtk_pctrl_get_group_name, 679 .get_group_pins = mtk_pctrl_get_group_pins, 680 }; 681 682 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 683 { 684 return ARRAY_SIZE(mtk_gpio_functions); 685 } 686 687 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev, 688 unsigned selector) 689 { 690 return mtk_gpio_functions[selector]; 691 } 692 693 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 694 unsigned function, 695 const char * const **groups, 696 unsigned * const num_groups) 697 { 698 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 699 700 *groups = pctl->grp_names; 701 *num_groups = pctl->ngroups; 702 703 return 0; 704 } 705 706 static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, 707 unsigned long pin, unsigned long mode) 708 { 709 unsigned int reg_addr; 710 unsigned char bit; 711 unsigned int val; 712 unsigned int mask = (1L << GPIO_MODE_BITS) - 1; 713 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 714 715 if (pctl->devdata->spec_pinmux_set) 716 pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin), 717 pin, mode); 718 719 reg_addr = ((pin / pctl->devdata->mode_per_reg) << pctl->devdata->port_shf) 720 + pctl->devdata->pinmux_offset; 721 722 mode &= mask; 723 bit = pin % pctl->devdata->mode_per_reg; 724 mask <<= (GPIO_MODE_BITS * bit); 725 val = (mode << (GPIO_MODE_BITS * bit)); 726 return regmap_update_bits(mtk_get_regmap(pctl, pin), 727 reg_addr, mask, val); 728 } 729 730 static const struct mtk_desc_pin * 731 mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num) 732 { 733 int i; 734 const struct mtk_desc_pin *pin; 735 736 for (i = 0; i < pctl->devdata->npins; i++) { 737 pin = pctl->devdata->pins + i; 738 if (pin->eint.eintnum == eint_num) 739 return pin; 740 } 741 742 return NULL; 743 } 744 745 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev, 746 unsigned function, 747 unsigned group) 748 { 749 bool ret; 750 const struct mtk_desc_function *desc; 751 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 752 struct mtk_pinctrl_group *g = pctl->groups + group; 753 754 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function); 755 if (!ret) { 756 dev_err(pctl->dev, "invalid function %d on group %d .\n", 757 function, group); 758 return -EINVAL; 759 } 760 761 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function); 762 if (!desc) 763 return -EINVAL; 764 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval); 765 return 0; 766 } 767 768 static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl, 769 unsigned offset) 770 { 771 const struct mtk_desc_pin *pin = pctl->devdata->pins + offset; 772 const struct mtk_desc_function *func = pin->functions; 773 774 while (func && func->name) { 775 if (!strncmp(func->name, GPIO_MODE_PREFIX, 776 sizeof(GPIO_MODE_PREFIX)-1)) 777 return func->muxval; 778 func++; 779 } 780 return -EINVAL; 781 } 782 783 static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, 784 struct pinctrl_gpio_range *range, 785 unsigned offset) 786 { 787 int muxval; 788 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 789 790 muxval = mtk_pmx_find_gpio_mode(pctl, offset); 791 792 if (muxval < 0) { 793 dev_err(pctl->dev, "invalid gpio pin %d.\n", offset); 794 return -EINVAL; 795 } 796 797 mtk_pmx_set_mode(pctldev, offset, muxval); 798 mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE); 799 800 return 0; 801 } 802 803 static const struct pinmux_ops mtk_pmx_ops = { 804 .get_functions_count = mtk_pmx_get_funcs_cnt, 805 .get_function_name = mtk_pmx_get_func_name, 806 .get_function_groups = mtk_pmx_get_func_groups, 807 .set_mux = mtk_pmx_set_mux, 808 .gpio_request_enable = mtk_pmx_gpio_request_enable, 809 }; 810 811 static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 812 { 813 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 814 815 return mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, offset, true); 816 } 817 818 static int mtk_gpio_direction_output(struct gpio_chip *chip, 819 unsigned offset, int value) 820 { 821 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 822 int ret; 823 824 ret = mtk_gpio_set(chip, offset, value); 825 if (ret) 826 return ret; 827 828 return mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, offset, false); 829 } 830 831 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 832 { 833 unsigned int reg_addr; 834 unsigned int bit; 835 unsigned int read_val = 0; 836 837 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 838 839 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; 840 bit = BIT(offset & pctl->devdata->mode_mask); 841 842 if (pctl->devdata->spec_dir_set) 843 pctl->devdata->spec_dir_set(®_addr, offset); 844 845 regmap_read(pctl->regmap1, reg_addr, &read_val); 846 if (read_val & bit) 847 return GPIO_LINE_DIRECTION_OUT; 848 849 return GPIO_LINE_DIRECTION_IN; 850 } 851 852 static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset) 853 { 854 unsigned int reg_addr; 855 unsigned int bit; 856 unsigned int read_val = 0; 857 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 858 859 reg_addr = mtk_get_port(pctl, offset) + 860 pctl->devdata->din_offset; 861 862 bit = BIT(offset & pctl->devdata->mode_mask); 863 regmap_read(pctl->regmap1, reg_addr, &read_val); 864 return !!(read_val & bit); 865 } 866 867 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 868 { 869 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 870 const struct mtk_desc_pin *pin; 871 unsigned long eint_n; 872 873 pin = pctl->devdata->pins + offset; 874 if (pin->eint.eintnum == NO_EINT_SUPPORT) 875 return -EINVAL; 876 877 eint_n = pin->eint.eintnum; 878 879 return mtk_eint_find_irq(pctl->eint, eint_n); 880 } 881 882 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned offset, 883 unsigned long config) 884 { 885 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 886 const struct mtk_desc_pin *pin; 887 unsigned long eint_n; 888 u32 debounce; 889 890 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 891 return -ENOTSUPP; 892 893 pin = pctl->devdata->pins + offset; 894 if (pin->eint.eintnum == NO_EINT_SUPPORT) 895 return -EINVAL; 896 897 debounce = pinconf_to_config_argument(config); 898 eint_n = pin->eint.eintnum; 899 900 return mtk_eint_set_debounce(pctl->eint, eint_n, debounce); 901 } 902 903 static const struct gpio_chip mtk_gpio_chip = { 904 .owner = THIS_MODULE, 905 .request = gpiochip_generic_request, 906 .free = gpiochip_generic_free, 907 .get_direction = mtk_gpio_get_direction, 908 .direction_input = mtk_gpio_direction_input, 909 .direction_output = mtk_gpio_direction_output, 910 .get = mtk_gpio_get, 911 .set = mtk_gpio_set, 912 .to_irq = mtk_gpio_to_irq, 913 .set_config = mtk_gpio_set_config, 914 }; 915 916 static int mtk_eint_suspend(struct device *device) 917 { 918 struct mtk_pinctrl *pctl = dev_get_drvdata(device); 919 920 return mtk_eint_do_suspend(pctl->eint); 921 } 922 923 static int mtk_eint_resume(struct device *device) 924 { 925 struct mtk_pinctrl *pctl = dev_get_drvdata(device); 926 927 return mtk_eint_do_resume(pctl->eint); 928 } 929 930 EXPORT_GPL_DEV_SLEEP_PM_OPS(mtk_eint_pm_ops) = { 931 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_eint_suspend, mtk_eint_resume) 932 }; 933 934 static int mtk_pctrl_build_state(struct platform_device *pdev) 935 { 936 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev); 937 int i; 938 939 pctl->ngroups = pctl->devdata->npins; 940 941 /* Allocate groups */ 942 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 943 sizeof(*pctl->groups), GFP_KERNEL); 944 if (!pctl->groups) 945 return -ENOMEM; 946 947 /* We assume that one pin is one group, use pin name as group name. */ 948 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 949 sizeof(*pctl->grp_names), GFP_KERNEL); 950 if (!pctl->grp_names) 951 return -ENOMEM; 952 953 for (i = 0; i < pctl->devdata->npins; i++) { 954 const struct mtk_desc_pin *pin = pctl->devdata->pins + i; 955 struct mtk_pinctrl_group *group = pctl->groups + i; 956 957 group->name = pin->pin.name; 958 group->pin = pin->pin.number; 959 960 pctl->grp_names[i] = pin->pin.name; 961 } 962 963 return 0; 964 } 965 966 static int 967 mtk_xt_get_gpio_n(void *data, unsigned long eint_n, unsigned int *gpio_n, 968 struct gpio_chip **gpio_chip) 969 { 970 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data; 971 const struct mtk_desc_pin *pin; 972 973 pin = mtk_find_pin_by_eint_num(pctl, eint_n); 974 if (!pin) 975 return -EINVAL; 976 977 *gpio_chip = pctl->chip; 978 *gpio_n = pin->pin.number; 979 980 return 0; 981 } 982 983 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n) 984 { 985 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data; 986 const struct mtk_desc_pin *pin; 987 988 pin = mtk_find_pin_by_eint_num(pctl, eint_n); 989 if (!pin) 990 return -EINVAL; 991 992 return mtk_gpio_get(pctl->chip, pin->pin.number); 993 } 994 995 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n) 996 { 997 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data; 998 const struct mtk_desc_pin *pin; 999 1000 pin = mtk_find_pin_by_eint_num(pctl, eint_n); 1001 if (!pin) 1002 return -EINVAL; 1003 1004 /* set mux to INT mode */ 1005 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux); 1006 /* set gpio direction to input */ 1007 mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number, 1008 true); 1009 /* set input-enable */ 1010 mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1, 1011 PIN_CONFIG_INPUT_ENABLE); 1012 1013 return 0; 1014 } 1015 1016 static const struct mtk_eint_xt mtk_eint_xt = { 1017 .get_gpio_n = mtk_xt_get_gpio_n, 1018 .get_gpio_state = mtk_xt_get_gpio_state, 1019 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint, 1020 }; 1021 1022 static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev) 1023 { 1024 struct device_node *np = pdev->dev.of_node; 1025 1026 if (!of_property_read_bool(np, "interrupt-controller")) 1027 return -ENODEV; 1028 1029 pctl->eint = devm_kzalloc(pctl->dev, sizeof(*pctl->eint), GFP_KERNEL); 1030 if (!pctl->eint) 1031 return -ENOMEM; 1032 1033 pctl->eint->nbase = 1; 1034 /* mtk-eint expects an array */ 1035 pctl->eint->base = devm_kzalloc(pctl->dev, sizeof(pctl->eint->base), GFP_KERNEL); 1036 if (!pctl->eint->base) 1037 return -ENOMEM; 1038 1039 pctl->eint->base[0] = devm_platform_ioremap_resource(pdev, 0); 1040 if (IS_ERR(pctl->eint->base[0])) 1041 return PTR_ERR(pctl->eint->base[0]); 1042 1043 pctl->eint->irq = irq_of_parse_and_map(np, 0); 1044 if (!pctl->eint->irq) 1045 return -EINVAL; 1046 1047 pctl->eint->dev = &pdev->dev; 1048 /* 1049 * If pctl->eint->regs == NULL, it would fall back into using a generic 1050 * register map in mtk_eint_do_init calls. 1051 */ 1052 pctl->eint->regs = pctl->devdata->eint_regs; 1053 pctl->eint->hw = &pctl->devdata->eint_hw; 1054 pctl->eint->pctl = pctl; 1055 pctl->eint->gpio_xlate = &mtk_eint_xt; 1056 1057 return mtk_eint_do_init(pctl->eint, NULL); 1058 } 1059 1060 /* This is used as a common probe function */ 1061 int mtk_pctrl_init(struct platform_device *pdev, 1062 const struct mtk_pinctrl_devdata *data, 1063 struct regmap *regmap) 1064 { 1065 struct device *dev = &pdev->dev; 1066 struct pinctrl_pin_desc *pins; 1067 struct mtk_pinctrl *pctl; 1068 struct device_node *np = pdev->dev.of_node, *node; 1069 int ret, i; 1070 1071 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1072 if (!pctl) 1073 return -ENOMEM; 1074 1075 platform_set_drvdata(pdev, pctl); 1076 1077 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0); 1078 if (node) { 1079 pctl->regmap1 = syscon_node_to_regmap(node); 1080 of_node_put(node); 1081 if (IS_ERR(pctl->regmap1)) 1082 return PTR_ERR(pctl->regmap1); 1083 } else if (regmap) { 1084 pctl->regmap1 = regmap; 1085 } else { 1086 return dev_err_probe(dev, -EINVAL, "Cannot find pinctrl regmap.\n"); 1087 } 1088 1089 /* Only 8135 has two base addr, other SoCs have only one. */ 1090 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1); 1091 if (node) { 1092 pctl->regmap2 = syscon_node_to_regmap(node); 1093 of_node_put(node); 1094 if (IS_ERR(pctl->regmap2)) 1095 return PTR_ERR(pctl->regmap2); 1096 } 1097 1098 pctl->devdata = data; 1099 ret = mtk_pctrl_build_state(pdev); 1100 if (ret) 1101 return dev_err_probe(dev, ret, "build state failed\n"); 1102 1103 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins), 1104 GFP_KERNEL); 1105 if (!pins) 1106 return -ENOMEM; 1107 1108 for (i = 0; i < pctl->devdata->npins; i++) 1109 pins[i] = pctl->devdata->pins[i].pin; 1110 1111 pctl->pctl_desc.name = dev_name(&pdev->dev); 1112 pctl->pctl_desc.owner = THIS_MODULE; 1113 pctl->pctl_desc.pins = pins; 1114 pctl->pctl_desc.npins = pctl->devdata->npins; 1115 pctl->pctl_desc.confops = &mtk_pconf_ops; 1116 pctl->pctl_desc.pctlops = &mtk_pctrl_ops; 1117 pctl->pctl_desc.pmxops = &mtk_pmx_ops; 1118 pctl->dev = &pdev->dev; 1119 1120 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1121 pctl); 1122 if (IS_ERR(pctl->pctl_dev)) 1123 return dev_err_probe(dev, PTR_ERR(pctl->pctl_dev), 1124 "Couldn't register pinctrl driver\n"); 1125 1126 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1127 if (!pctl->chip) 1128 return -ENOMEM; 1129 1130 *pctl->chip = mtk_gpio_chip; 1131 pctl->chip->ngpio = pctl->devdata->npins; 1132 pctl->chip->label = dev_name(&pdev->dev); 1133 pctl->chip->parent = &pdev->dev; 1134 pctl->chip->base = -1; 1135 1136 ret = devm_gpiochip_add_data(&pdev->dev, pctl->chip, pctl); 1137 if (ret) 1138 return -EINVAL; 1139 1140 /* Register the GPIO to pin mappings. */ 1141 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1142 0, 0, pctl->devdata->npins); 1143 if (ret) 1144 return -EINVAL; 1145 1146 /* Only initialize EINT if we have EINT pins */ 1147 if (data->eint_hw.ap_num > 0) { 1148 ret = mtk_eint_init(pctl, pdev); 1149 if (ret) 1150 return ret; 1151 } 1152 1153 return 0; 1154 } 1155 EXPORT_SYMBOL_NS_GPL(mtk_pctrl_init, "MTK_PINCTRL"); 1156 1157 int mtk_pctrl_common_probe(struct platform_device *pdev) 1158 { 1159 struct device *dev = &pdev->dev; 1160 const struct mtk_pinctrl_devdata *data = device_get_match_data(dev); 1161 1162 if (!data) 1163 return -ENODEV; 1164 1165 return mtk_pctrl_init(pdev, data, NULL); 1166 } 1167 EXPORT_SYMBOL_NS_GPL(mtk_pctrl_common_probe, "MTK_PINCTRL"); 1168 1169 MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver"); 1170 MODULE_LICENSE("GPL v2"); 1171