1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver. 4 * Copyright (c) 2014 MediaTek Inc. 5 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> 6 */ 7 8 #include <linux/io.h> 9 #include <linux/gpio/driver.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/of_irq.h> 14 #include <linux/pinctrl/consumer.h> 15 #include <linux/pinctrl/machine.h> 16 #include <linux/pinctrl/pinconf.h> 17 #include <linux/pinctrl/pinconf-generic.h> 18 #include <linux/pinctrl/pinctrl.h> 19 #include <linux/pinctrl/pinmux.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 #include <linux/bitops.h> 23 #include <linux/regmap.h> 24 #include <linux/mfd/syscon.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/pm.h> 28 #include <dt-bindings/pinctrl/mt65xx.h> 29 30 #include "../core.h" 31 #include "../pinconf.h" 32 #include "../pinctrl-utils.h" 33 #include "mtk-eint.h" 34 #include "pinctrl-mtk-common.h" 35 36 #define GPIO_MODE_BITS 3 37 #define GPIO_MODE_PREFIX "GPIO" 38 39 static const char * const mtk_gpio_functions[] = { 40 "func0", "func1", "func2", "func3", 41 "func4", "func5", "func6", "func7", 42 "func8", "func9", "func10", "func11", 43 "func12", "func13", "func14", "func15", 44 }; 45 46 /* 47 * There are two base address for pull related configuration 48 * in mt8135, and different GPIO pins use different base address. 49 * When pin number greater than type1_start and less than type1_end, 50 * should use the second base address. 51 */ 52 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, 53 unsigned long pin) 54 { 55 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) 56 return pctl->regmap2; 57 return pctl->regmap1; 58 } 59 60 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin) 61 { 62 /* Different SoC has different mask and port shift. */ 63 return ((pin >> pctl->devdata->mode_shf) & pctl->devdata->port_mask) 64 << pctl->devdata->port_shf; 65 } 66 67 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 68 struct pinctrl_gpio_range *range, unsigned offset, 69 bool input) 70 { 71 unsigned int reg_addr; 72 unsigned int bit; 73 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 74 75 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; 76 bit = BIT(offset & pctl->devdata->mode_mask); 77 78 if (pctl->devdata->spec_dir_set) 79 pctl->devdata->spec_dir_set(®_addr, offset); 80 81 if (input) 82 /* Different SoC has different alignment offset. */ 83 reg_addr = CLR_ADDR(reg_addr, pctl); 84 else 85 reg_addr = SET_ADDR(reg_addr, pctl); 86 87 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); 88 return 0; 89 } 90 91 static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 92 { 93 unsigned int reg_addr; 94 unsigned int bit; 95 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 96 97 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset; 98 bit = BIT(offset & pctl->devdata->mode_mask); 99 100 if (value) 101 reg_addr = SET_ADDR(reg_addr, pctl); 102 else 103 reg_addr = CLR_ADDR(reg_addr, pctl); 104 105 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); 106 } 107 108 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, 109 int value, enum pin_config_param arg) 110 { 111 unsigned int reg_addr, offset; 112 unsigned int bit; 113 114 /** 115 * Due to some soc are not support ies/smt config, add this special 116 * control to handle it. 117 */ 118 if (!pctl->devdata->spec_ies_smt_set && 119 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT && 120 arg == PIN_CONFIG_INPUT_ENABLE) 121 return -EINVAL; 122 123 if (!pctl->devdata->spec_ies_smt_set && 124 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT && 125 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) 126 return -EINVAL; 127 128 /* 129 * Due to some pins are irregular, their input enable and smt 130 * control register are discontinuous, so we need this special handle. 131 */ 132 if (pctl->devdata->spec_ies_smt_set) { 133 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), 134 pctl->devdata, pin, value, arg); 135 } 136 137 if (arg == PIN_CONFIG_INPUT_ENABLE) 138 offset = pctl->devdata->ies_offset; 139 else 140 offset = pctl->devdata->smt_offset; 141 142 bit = BIT(offset & pctl->devdata->mode_mask); 143 144 if (value) 145 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl); 146 else 147 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); 148 149 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); 150 return 0; 151 } 152 153 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, 154 const struct mtk_pinctrl_devdata *devdata, 155 unsigned int pin, int value, enum pin_config_param arg) 156 { 157 const struct mtk_pin_ies_smt_set *ies_smt_infos = NULL; 158 unsigned int i, info_num, reg_addr, bit; 159 160 switch (arg) { 161 case PIN_CONFIG_INPUT_ENABLE: 162 ies_smt_infos = devdata->spec_ies; 163 info_num = devdata->n_spec_ies; 164 break; 165 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 166 ies_smt_infos = devdata->spec_smt; 167 info_num = devdata->n_spec_smt; 168 break; 169 default: 170 break; 171 } 172 173 if (!ies_smt_infos) 174 return -EINVAL; 175 176 for (i = 0; i < info_num; i++) { 177 if (pin >= ies_smt_infos[i].start && 178 pin <= ies_smt_infos[i].end) { 179 break; 180 } 181 } 182 183 if (i == info_num) 184 return -EINVAL; 185 186 if (value) 187 reg_addr = ies_smt_infos[i].offset + devdata->port_align; 188 else 189 reg_addr = ies_smt_infos[i].offset + (devdata->port_align << 1); 190 191 bit = BIT(ies_smt_infos[i].bit); 192 regmap_write(regmap, reg_addr, bit); 193 return 0; 194 } 195 196 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( 197 struct mtk_pinctrl *pctl, unsigned long pin) { 198 int i; 199 200 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) { 201 const struct mtk_pin_drv_grp *pin_drv = 202 pctl->devdata->pin_drv_grp + i; 203 if (pin == pin_drv->pin) 204 return pin_drv; 205 } 206 207 return NULL; 208 } 209 210 static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, 211 unsigned int pin, unsigned char driving) 212 { 213 const struct mtk_pin_drv_grp *pin_drv; 214 unsigned int val; 215 unsigned int bits, mask, shift; 216 const struct mtk_drv_group_desc *drv_grp; 217 218 if (pin >= pctl->devdata->npins) 219 return -EINVAL; 220 221 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin); 222 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls) 223 return -EINVAL; 224 225 drv_grp = pctl->devdata->grp_desc + pin_drv->grp; 226 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv 227 && !(driving % drv_grp->step)) { 228 val = driving / drv_grp->step - 1; 229 bits = drv_grp->high_bit - drv_grp->low_bit + 1; 230 mask = BIT(bits) - 1; 231 shift = pin_drv->bit + drv_grp->low_bit; 232 mask <<= shift; 233 val <<= shift; 234 return regmap_update_bits(mtk_get_regmap(pctl, pin), 235 pin_drv->offset, mask, val); 236 } 237 238 return -EINVAL; 239 } 240 241 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, 242 const struct mtk_pinctrl_devdata *devdata, 243 unsigned int pin, bool isup, unsigned int r1r0) 244 { 245 unsigned int i; 246 unsigned int reg_pupd, reg_set, reg_rst; 247 unsigned int bit_pupd, bit_r0, bit_r1; 248 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin; 249 bool find = false; 250 251 if (!devdata->spec_pupd) 252 return -EINVAL; 253 254 for (i = 0; i < devdata->n_spec_pupd; i++) { 255 if (pin == devdata->spec_pupd[i].pin) { 256 find = true; 257 break; 258 } 259 } 260 261 if (!find) 262 return -EINVAL; 263 264 spec_pupd_pin = devdata->spec_pupd + i; 265 reg_set = spec_pupd_pin->offset + devdata->port_align; 266 reg_rst = spec_pupd_pin->offset + (devdata->port_align << 1); 267 268 if (isup) 269 reg_pupd = reg_rst; 270 else 271 reg_pupd = reg_set; 272 273 bit_pupd = BIT(spec_pupd_pin->pupd_bit); 274 regmap_write(regmap, reg_pupd, bit_pupd); 275 276 bit_r0 = BIT(spec_pupd_pin->r0_bit); 277 bit_r1 = BIT(spec_pupd_pin->r1_bit); 278 279 switch (r1r0) { 280 case MTK_PUPD_SET_R1R0_00: 281 regmap_write(regmap, reg_rst, bit_r0); 282 regmap_write(regmap, reg_rst, bit_r1); 283 break; 284 case MTK_PUPD_SET_R1R0_01: 285 regmap_write(regmap, reg_set, bit_r0); 286 regmap_write(regmap, reg_rst, bit_r1); 287 break; 288 case MTK_PUPD_SET_R1R0_10: 289 regmap_write(regmap, reg_rst, bit_r0); 290 regmap_write(regmap, reg_set, bit_r1); 291 break; 292 case MTK_PUPD_SET_R1R0_11: 293 regmap_write(regmap, reg_set, bit_r0); 294 regmap_write(regmap, reg_set, bit_r1); 295 break; 296 default: 297 return -EINVAL; 298 } 299 300 return 0; 301 } 302 303 static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, 304 unsigned int pin, bool enable, bool isup, unsigned int arg) 305 { 306 unsigned int bit; 307 unsigned int reg_pullen, reg_pullsel, r1r0; 308 int ret; 309 310 /* Some pins' pull setting are very different, 311 * they have separate pull up/down bit, R0 and R1 312 * resistor bit, so we need this special handle. 313 */ 314 if (pctl->devdata->spec_pull_set) { 315 /* For special pins, bias-disable is set by R1R0, 316 * the parameter should be "MTK_PUPD_SET_R1R0_00". 317 */ 318 r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00; 319 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), 320 pctl->devdata, pin, isup, 321 r1r0); 322 if (!ret) 323 return 0; 324 } 325 326 /* For generic pull config, default arg value should be 0 or 1. */ 327 if (arg != 0 && arg != 1) { 328 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", 329 arg, pin); 330 return -EINVAL; 331 } 332 333 bit = BIT(pin & pctl->devdata->mode_mask); 334 if (enable) 335 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + 336 pctl->devdata->pullen_offset, pctl); 337 else 338 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) + 339 pctl->devdata->pullen_offset, pctl); 340 341 if (isup) 342 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) + 343 pctl->devdata->pullsel_offset, pctl); 344 else 345 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + 346 pctl->devdata->pullsel_offset, pctl); 347 348 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); 349 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); 350 return 0; 351 } 352 353 static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, 354 unsigned int pin, enum pin_config_param param, 355 enum pin_config_param arg) 356 { 357 int ret = 0; 358 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 359 360 switch (param) { 361 case PIN_CONFIG_BIAS_DISABLE: 362 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg); 363 break; 364 case PIN_CONFIG_BIAS_PULL_UP: 365 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg); 366 break; 367 case PIN_CONFIG_BIAS_PULL_DOWN: 368 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg); 369 break; 370 case PIN_CONFIG_INPUT_ENABLE: 371 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true); 372 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); 373 break; 374 case PIN_CONFIG_OUTPUT: 375 mtk_gpio_set(pctl->chip, pin, arg); 376 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); 377 break; 378 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 379 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true); 380 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); 381 break; 382 case PIN_CONFIG_DRIVE_STRENGTH: 383 ret = mtk_pconf_set_driving(pctl, pin, arg); 384 break; 385 default: 386 ret = -EINVAL; 387 } 388 389 return ret; 390 } 391 392 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, 393 unsigned group, 394 unsigned long *config) 395 { 396 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 397 398 *config = pctl->groups[group].config; 399 400 return 0; 401 } 402 403 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 404 unsigned long *configs, unsigned num_configs) 405 { 406 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 407 struct mtk_pinctrl_group *g = &pctl->groups[group]; 408 int i, ret; 409 410 for (i = 0; i < num_configs; i++) { 411 ret = mtk_pconf_parse_conf(pctldev, g->pin, 412 pinconf_to_config_param(configs[i]), 413 pinconf_to_config_argument(configs[i])); 414 if (ret < 0) 415 return ret; 416 417 g->config = configs[i]; 418 } 419 420 return 0; 421 } 422 423 static const struct pinconf_ops mtk_pconf_ops = { 424 .pin_config_group_get = mtk_pconf_group_get, 425 .pin_config_group_set = mtk_pconf_group_set, 426 }; 427 428 static struct mtk_pinctrl_group * 429 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin) 430 { 431 int i; 432 433 for (i = 0; i < pctl->ngroups; i++) { 434 struct mtk_pinctrl_group *grp = pctl->groups + i; 435 436 if (grp->pin == pin) 437 return grp; 438 } 439 440 return NULL; 441 } 442 443 static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin( 444 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum) 445 { 446 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num; 447 const struct mtk_desc_function *func = pin->functions; 448 449 while (func && func->name) { 450 if (func->muxval == fnum) 451 return func; 452 func++; 453 } 454 455 return NULL; 456 } 457 458 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl, 459 u32 pin_num, u32 fnum) 460 { 461 int i; 462 463 for (i = 0; i < pctl->devdata->npins; i++) { 464 const struct mtk_desc_pin *pin = pctl->devdata->pins + i; 465 466 if (pin->pin.number == pin_num) { 467 const struct mtk_desc_function *func = 468 pin->functions; 469 470 while (func && func->name) { 471 if (func->muxval == fnum) 472 return true; 473 func++; 474 } 475 476 break; 477 } 478 } 479 480 return false; 481 } 482 483 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, 484 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp, 485 struct pinctrl_map **map, unsigned *reserved_maps, 486 unsigned *num_maps) 487 { 488 bool ret; 489 490 if (*num_maps == *reserved_maps) 491 return -ENOSPC; 492 493 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 494 (*map)[*num_maps].data.mux.group = grp->name; 495 496 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum); 497 if (!ret) { 498 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 499 fnum, pin); 500 return -EINVAL; 501 } 502 503 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum]; 504 (*num_maps)++; 505 506 return 0; 507 } 508 509 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 510 struct device_node *node, 511 struct pinctrl_map **map, 512 unsigned *reserved_maps, 513 unsigned *num_maps) 514 { 515 struct property *pins; 516 u32 pinfunc, pin, func; 517 int num_pins, num_funcs, maps_per_pin; 518 unsigned long *configs; 519 unsigned int num_configs; 520 bool has_config = false; 521 int i, err; 522 unsigned reserve = 0; 523 struct mtk_pinctrl_group *grp; 524 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 525 526 pins = of_find_property(node, "pinmux", NULL); 527 if (!pins) { 528 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", 529 node); 530 return -EINVAL; 531 } 532 533 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 534 &num_configs); 535 if (err) 536 return err; 537 538 if (num_configs) 539 has_config = true; 540 541 num_pins = pins->length / sizeof(u32); 542 num_funcs = num_pins; 543 maps_per_pin = 0; 544 if (num_funcs) 545 maps_per_pin++; 546 if (has_config && num_pins >= 1) 547 maps_per_pin++; 548 549 if (!num_pins || !maps_per_pin) { 550 err = -EINVAL; 551 goto exit; 552 } 553 554 reserve = num_pins * maps_per_pin; 555 556 err = pinctrl_utils_reserve_map(pctldev, map, 557 reserved_maps, num_maps, reserve); 558 if (err < 0) 559 goto exit; 560 561 for (i = 0; i < num_pins; i++) { 562 err = of_property_read_u32_index(node, "pinmux", 563 i, &pinfunc); 564 if (err) 565 goto exit; 566 567 pin = MTK_GET_PIN_NO(pinfunc); 568 func = MTK_GET_PIN_FUNC(pinfunc); 569 570 if (pin >= pctl->devdata->npins || 571 func >= ARRAY_SIZE(mtk_gpio_functions)) { 572 dev_err(pctl->dev, "invalid pins value.\n"); 573 err = -EINVAL; 574 goto exit; 575 } 576 577 grp = mtk_pctrl_find_group_by_pin(pctl, pin); 578 if (!grp) { 579 dev_err(pctl->dev, "unable to match pin %d to group\n", 580 pin); 581 err = -EINVAL; 582 goto exit; 583 } 584 585 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 586 reserved_maps, num_maps); 587 if (err < 0) 588 goto exit; 589 590 if (has_config) { 591 err = pinctrl_utils_add_map_configs(pctldev, map, 592 reserved_maps, num_maps, grp->name, 593 configs, num_configs, 594 PIN_MAP_TYPE_CONFIGS_GROUP); 595 if (err < 0) 596 goto exit; 597 } 598 } 599 600 err = 0; 601 602 exit: 603 kfree(configs); 604 return err; 605 } 606 607 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 608 struct device_node *np_config, 609 struct pinctrl_map **map, unsigned *num_maps) 610 { 611 struct device_node *np; 612 unsigned reserved_maps; 613 int ret; 614 615 *map = NULL; 616 *num_maps = 0; 617 reserved_maps = 0; 618 619 for_each_child_of_node(np_config, np) { 620 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map, 621 &reserved_maps, num_maps); 622 if (ret < 0) { 623 pinctrl_utils_free_map(pctldev, *map, *num_maps); 624 of_node_put(np); 625 return ret; 626 } 627 } 628 629 return 0; 630 } 631 632 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 633 { 634 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 635 636 return pctl->ngroups; 637 } 638 639 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev, 640 unsigned group) 641 { 642 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 643 644 return pctl->groups[group].name; 645 } 646 647 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 648 unsigned group, 649 const unsigned **pins, 650 unsigned *num_pins) 651 { 652 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 653 654 *pins = (unsigned *)&pctl->groups[group].pin; 655 *num_pins = 1; 656 657 return 0; 658 } 659 660 static const struct pinctrl_ops mtk_pctrl_ops = { 661 .dt_node_to_map = mtk_pctrl_dt_node_to_map, 662 .dt_free_map = pinctrl_utils_free_map, 663 .get_groups_count = mtk_pctrl_get_groups_count, 664 .get_group_name = mtk_pctrl_get_group_name, 665 .get_group_pins = mtk_pctrl_get_group_pins, 666 }; 667 668 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 669 { 670 return ARRAY_SIZE(mtk_gpio_functions); 671 } 672 673 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev, 674 unsigned selector) 675 { 676 return mtk_gpio_functions[selector]; 677 } 678 679 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 680 unsigned function, 681 const char * const **groups, 682 unsigned * const num_groups) 683 { 684 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 685 686 *groups = pctl->grp_names; 687 *num_groups = pctl->ngroups; 688 689 return 0; 690 } 691 692 static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, 693 unsigned long pin, unsigned long mode) 694 { 695 unsigned int reg_addr; 696 unsigned char bit; 697 unsigned int val; 698 unsigned int mask = (1L << GPIO_MODE_BITS) - 1; 699 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 700 701 if (pctl->devdata->spec_pinmux_set) 702 pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin), 703 pin, mode); 704 705 reg_addr = ((pin / pctl->devdata->mode_per_reg) << pctl->devdata->port_shf) 706 + pctl->devdata->pinmux_offset; 707 708 mode &= mask; 709 bit = pin % pctl->devdata->mode_per_reg; 710 mask <<= (GPIO_MODE_BITS * bit); 711 val = (mode << (GPIO_MODE_BITS * bit)); 712 return regmap_update_bits(mtk_get_regmap(pctl, pin), 713 reg_addr, mask, val); 714 } 715 716 static const struct mtk_desc_pin * 717 mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num) 718 { 719 int i; 720 const struct mtk_desc_pin *pin; 721 722 for (i = 0; i < pctl->devdata->npins; i++) { 723 pin = pctl->devdata->pins + i; 724 if (pin->eint.eintnum == eint_num) 725 return pin; 726 } 727 728 return NULL; 729 } 730 731 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev, 732 unsigned function, 733 unsigned group) 734 { 735 bool ret; 736 const struct mtk_desc_function *desc; 737 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 738 struct mtk_pinctrl_group *g = pctl->groups + group; 739 740 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function); 741 if (!ret) { 742 dev_err(pctl->dev, "invalid function %d on group %d .\n", 743 function, group); 744 return -EINVAL; 745 } 746 747 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function); 748 if (!desc) 749 return -EINVAL; 750 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval); 751 return 0; 752 } 753 754 static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl, 755 unsigned offset) 756 { 757 const struct mtk_desc_pin *pin = pctl->devdata->pins + offset; 758 const struct mtk_desc_function *func = pin->functions; 759 760 while (func && func->name) { 761 if (!strncmp(func->name, GPIO_MODE_PREFIX, 762 sizeof(GPIO_MODE_PREFIX)-1)) 763 return func->muxval; 764 func++; 765 } 766 return -EINVAL; 767 } 768 769 static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, 770 struct pinctrl_gpio_range *range, 771 unsigned offset) 772 { 773 int muxval; 774 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 775 776 muxval = mtk_pmx_find_gpio_mode(pctl, offset); 777 778 if (muxval < 0) { 779 dev_err(pctl->dev, "invalid gpio pin %d.\n", offset); 780 return -EINVAL; 781 } 782 783 mtk_pmx_set_mode(pctldev, offset, muxval); 784 mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE); 785 786 return 0; 787 } 788 789 static const struct pinmux_ops mtk_pmx_ops = { 790 .get_functions_count = mtk_pmx_get_funcs_cnt, 791 .get_function_name = mtk_pmx_get_func_name, 792 .get_function_groups = mtk_pmx_get_func_groups, 793 .set_mux = mtk_pmx_set_mux, 794 .gpio_set_direction = mtk_pmx_gpio_set_direction, 795 .gpio_request_enable = mtk_pmx_gpio_request_enable, 796 }; 797 798 static int mtk_gpio_direction_input(struct gpio_chip *chip, 799 unsigned offset) 800 { 801 return pinctrl_gpio_direction_input(chip->base + offset); 802 } 803 804 static int mtk_gpio_direction_output(struct gpio_chip *chip, 805 unsigned offset, int value) 806 { 807 mtk_gpio_set(chip, offset, value); 808 return pinctrl_gpio_direction_output(chip->base + offset); 809 } 810 811 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 812 { 813 unsigned int reg_addr; 814 unsigned int bit; 815 unsigned int read_val = 0; 816 817 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 818 819 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; 820 bit = BIT(offset & pctl->devdata->mode_mask); 821 822 if (pctl->devdata->spec_dir_set) 823 pctl->devdata->spec_dir_set(®_addr, offset); 824 825 regmap_read(pctl->regmap1, reg_addr, &read_val); 826 if (read_val & bit) 827 return GPIO_LINE_DIRECTION_OUT; 828 829 return GPIO_LINE_DIRECTION_IN; 830 } 831 832 static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset) 833 { 834 unsigned int reg_addr; 835 unsigned int bit; 836 unsigned int read_val = 0; 837 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 838 839 reg_addr = mtk_get_port(pctl, offset) + 840 pctl->devdata->din_offset; 841 842 bit = BIT(offset & pctl->devdata->mode_mask); 843 regmap_read(pctl->regmap1, reg_addr, &read_val); 844 return !!(read_val & bit); 845 } 846 847 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 848 { 849 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 850 const struct mtk_desc_pin *pin; 851 unsigned long eint_n; 852 853 pin = pctl->devdata->pins + offset; 854 if (pin->eint.eintnum == NO_EINT_SUPPORT) 855 return -EINVAL; 856 857 eint_n = pin->eint.eintnum; 858 859 return mtk_eint_find_irq(pctl->eint, eint_n); 860 } 861 862 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned offset, 863 unsigned long config) 864 { 865 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 866 const struct mtk_desc_pin *pin; 867 unsigned long eint_n; 868 u32 debounce; 869 870 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 871 return -ENOTSUPP; 872 873 pin = pctl->devdata->pins + offset; 874 if (pin->eint.eintnum == NO_EINT_SUPPORT) 875 return -EINVAL; 876 877 debounce = pinconf_to_config_argument(config); 878 eint_n = pin->eint.eintnum; 879 880 return mtk_eint_set_debounce(pctl->eint, eint_n, debounce); 881 } 882 883 static const struct gpio_chip mtk_gpio_chip = { 884 .owner = THIS_MODULE, 885 .request = gpiochip_generic_request, 886 .free = gpiochip_generic_free, 887 .get_direction = mtk_gpio_get_direction, 888 .direction_input = mtk_gpio_direction_input, 889 .direction_output = mtk_gpio_direction_output, 890 .get = mtk_gpio_get, 891 .set = mtk_gpio_set, 892 .to_irq = mtk_gpio_to_irq, 893 .set_config = mtk_gpio_set_config, 894 .of_gpio_n_cells = 2, 895 }; 896 897 static int mtk_eint_suspend(struct device *device) 898 { 899 struct mtk_pinctrl *pctl = dev_get_drvdata(device); 900 901 return mtk_eint_do_suspend(pctl->eint); 902 } 903 904 static int mtk_eint_resume(struct device *device) 905 { 906 struct mtk_pinctrl *pctl = dev_get_drvdata(device); 907 908 return mtk_eint_do_resume(pctl->eint); 909 } 910 911 const struct dev_pm_ops mtk_eint_pm_ops = { 912 .suspend_noirq = mtk_eint_suspend, 913 .resume_noirq = mtk_eint_resume, 914 }; 915 916 static int mtk_pctrl_build_state(struct platform_device *pdev) 917 { 918 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev); 919 int i; 920 921 pctl->ngroups = pctl->devdata->npins; 922 923 /* Allocate groups */ 924 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 925 sizeof(*pctl->groups), GFP_KERNEL); 926 if (!pctl->groups) 927 return -ENOMEM; 928 929 /* We assume that one pin is one group, use pin name as group name. */ 930 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 931 sizeof(*pctl->grp_names), GFP_KERNEL); 932 if (!pctl->grp_names) 933 return -ENOMEM; 934 935 for (i = 0; i < pctl->devdata->npins; i++) { 936 const struct mtk_desc_pin *pin = pctl->devdata->pins + i; 937 struct mtk_pinctrl_group *group = pctl->groups + i; 938 939 group->name = pin->pin.name; 940 group->pin = pin->pin.number; 941 942 pctl->grp_names[i] = pin->pin.name; 943 } 944 945 return 0; 946 } 947 948 static int 949 mtk_xt_get_gpio_n(void *data, unsigned long eint_n, unsigned int *gpio_n, 950 struct gpio_chip **gpio_chip) 951 { 952 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data; 953 const struct mtk_desc_pin *pin; 954 955 pin = mtk_find_pin_by_eint_num(pctl, eint_n); 956 if (!pin) 957 return -EINVAL; 958 959 *gpio_chip = pctl->chip; 960 *gpio_n = pin->pin.number; 961 962 return 0; 963 } 964 965 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n) 966 { 967 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data; 968 const struct mtk_desc_pin *pin; 969 970 pin = mtk_find_pin_by_eint_num(pctl, eint_n); 971 if (!pin) 972 return -EINVAL; 973 974 return mtk_gpio_get(pctl->chip, pin->pin.number); 975 } 976 977 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n) 978 { 979 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data; 980 const struct mtk_desc_pin *pin; 981 982 pin = mtk_find_pin_by_eint_num(pctl, eint_n); 983 if (!pin) 984 return -EINVAL; 985 986 /* set mux to INT mode */ 987 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux); 988 /* set gpio direction to input */ 989 mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number, 990 true); 991 /* set input-enable */ 992 mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1, 993 PIN_CONFIG_INPUT_ENABLE); 994 995 return 0; 996 } 997 998 static const struct mtk_eint_xt mtk_eint_xt = { 999 .get_gpio_n = mtk_xt_get_gpio_n, 1000 .get_gpio_state = mtk_xt_get_gpio_state, 1001 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint, 1002 }; 1003 1004 static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev) 1005 { 1006 struct device_node *np = pdev->dev.of_node; 1007 1008 if (!of_property_read_bool(np, "interrupt-controller")) 1009 return -ENODEV; 1010 1011 pctl->eint = devm_kzalloc(pctl->dev, sizeof(*pctl->eint), GFP_KERNEL); 1012 if (!pctl->eint) 1013 return -ENOMEM; 1014 1015 pctl->eint->base = devm_platform_ioremap_resource(pdev, 0); 1016 if (IS_ERR(pctl->eint->base)) 1017 return PTR_ERR(pctl->eint->base); 1018 1019 pctl->eint->irq = irq_of_parse_and_map(np, 0); 1020 if (!pctl->eint->irq) 1021 return -EINVAL; 1022 1023 pctl->eint->dev = &pdev->dev; 1024 /* 1025 * If pctl->eint->regs == NULL, it would fall back into using a generic 1026 * register map in mtk_eint_do_init calls. 1027 */ 1028 pctl->eint->regs = pctl->devdata->eint_regs; 1029 pctl->eint->hw = &pctl->devdata->eint_hw; 1030 pctl->eint->pctl = pctl; 1031 pctl->eint->gpio_xlate = &mtk_eint_xt; 1032 1033 return mtk_eint_do_init(pctl->eint); 1034 } 1035 1036 /* This is used as a common probe function */ 1037 int mtk_pctrl_init(struct platform_device *pdev, 1038 const struct mtk_pinctrl_devdata *data, 1039 struct regmap *regmap) 1040 { 1041 struct device *dev = &pdev->dev; 1042 struct pinctrl_pin_desc *pins; 1043 struct mtk_pinctrl *pctl; 1044 struct device_node *np = pdev->dev.of_node, *node; 1045 struct property *prop; 1046 int ret, i; 1047 1048 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1049 if (!pctl) 1050 return -ENOMEM; 1051 1052 platform_set_drvdata(pdev, pctl); 1053 1054 prop = of_find_property(np, "pins-are-numbered", NULL); 1055 if (!prop) 1056 return dev_err_probe(dev, -EINVAL, 1057 "only support pins-are-numbered format\n"); 1058 1059 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0); 1060 if (node) { 1061 pctl->regmap1 = syscon_node_to_regmap(node); 1062 of_node_put(node); 1063 if (IS_ERR(pctl->regmap1)) 1064 return PTR_ERR(pctl->regmap1); 1065 } else if (regmap) { 1066 pctl->regmap1 = regmap; 1067 } else { 1068 return dev_err_probe(dev, -EINVAL, "Cannot find pinctrl regmap.\n"); 1069 } 1070 1071 /* Only 8135 has two base addr, other SoCs have only one. */ 1072 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1); 1073 if (node) { 1074 pctl->regmap2 = syscon_node_to_regmap(node); 1075 of_node_put(node); 1076 if (IS_ERR(pctl->regmap2)) 1077 return PTR_ERR(pctl->regmap2); 1078 } 1079 1080 pctl->devdata = data; 1081 ret = mtk_pctrl_build_state(pdev); 1082 if (ret) 1083 return dev_err_probe(dev, ret, "build state failed\n"); 1084 1085 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins), 1086 GFP_KERNEL); 1087 if (!pins) 1088 return -ENOMEM; 1089 1090 for (i = 0; i < pctl->devdata->npins; i++) 1091 pins[i] = pctl->devdata->pins[i].pin; 1092 1093 pctl->pctl_desc.name = dev_name(&pdev->dev); 1094 pctl->pctl_desc.owner = THIS_MODULE; 1095 pctl->pctl_desc.pins = pins; 1096 pctl->pctl_desc.npins = pctl->devdata->npins; 1097 pctl->pctl_desc.confops = &mtk_pconf_ops; 1098 pctl->pctl_desc.pctlops = &mtk_pctrl_ops; 1099 pctl->pctl_desc.pmxops = &mtk_pmx_ops; 1100 pctl->dev = &pdev->dev; 1101 1102 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1103 pctl); 1104 if (IS_ERR(pctl->pctl_dev)) 1105 return dev_err_probe(dev, PTR_ERR(pctl->pctl_dev), 1106 "Couldn't register pinctrl driver\n"); 1107 1108 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1109 if (!pctl->chip) 1110 return -ENOMEM; 1111 1112 *pctl->chip = mtk_gpio_chip; 1113 pctl->chip->ngpio = pctl->devdata->npins; 1114 pctl->chip->label = dev_name(&pdev->dev); 1115 pctl->chip->parent = &pdev->dev; 1116 pctl->chip->base = -1; 1117 1118 ret = gpiochip_add_data(pctl->chip, pctl); 1119 if (ret) 1120 return -EINVAL; 1121 1122 /* Register the GPIO to pin mappings. */ 1123 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1124 0, 0, pctl->devdata->npins); 1125 if (ret) { 1126 ret = -EINVAL; 1127 goto chip_error; 1128 } 1129 1130 ret = mtk_eint_init(pctl, pdev); 1131 if (ret) 1132 goto chip_error; 1133 1134 return 0; 1135 1136 chip_error: 1137 gpiochip_remove(pctl->chip); 1138 return ret; 1139 } 1140 1141 int mtk_pctrl_common_probe(struct platform_device *pdev) 1142 { 1143 struct device *dev = &pdev->dev; 1144 const struct mtk_pinctrl_devdata *data = device_get_match_data(dev); 1145 1146 if (!data) 1147 return -ENODEV; 1148 1149 return mtk_pctrl_init(pdev, data, NULL); 1150 } 1151