1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 MediaTek Inc. 4 * 5 * Author: Sean Wang <sean.wang@mediatek.com> 6 * 7 */ 8 9 #include <dt-bindings/pinctrl/mt65xx.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/platform_device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 19 #include "mtk-eint.h" 20 #include "pinctrl-mtk-common-v2.h" 21 22 /** 23 * struct mtk_drive_desc - the structure that holds the information 24 * of the driving current 25 * @min: the minimum current of this group 26 * @max: the maximum current of this group 27 * @step: the step current of this group 28 * @scal: the weight factor 29 * 30 * formula: output = ((input) / step - 1) * scal 31 */ 32 struct mtk_drive_desc { 33 u8 min; 34 u8 max; 35 u8 step; 36 u8 scal; 37 }; 38 39 /* The groups of drive strength */ 40 static const struct mtk_drive_desc mtk_drive[] = { 41 [DRV_GRP0] = { 4, 16, 4, 1 }, 42 [DRV_GRP1] = { 4, 16, 4, 2 }, 43 [DRV_GRP2] = { 2, 8, 2, 1 }, 44 [DRV_GRP3] = { 2, 8, 2, 2 }, 45 [DRV_GRP4] = { 2, 16, 2, 1 }, 46 }; 47 48 static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val) 49 { 50 writel_relaxed(val, pctl->base[i] + reg); 51 } 52 53 static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg) 54 { 55 return readl_relaxed(pctl->base[i] + reg); 56 } 57 58 void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) 59 { 60 u32 val; 61 unsigned long flags; 62 63 spin_lock_irqsave(&pctl->lock, flags); 64 65 val = mtk_r32(pctl, i, reg); 66 val &= ~mask; 67 val |= set; 68 mtk_w32(pctl, i, reg, val); 69 70 spin_unlock_irqrestore(&pctl->lock, flags); 71 } 72 EXPORT_SYMBOL_NS_GPL(mtk_rmw, "MTK_PINCTRL"); 73 74 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, 75 const struct mtk_pin_desc *desc, 76 int field, struct mtk_pin_field *pfd) 77 { 78 const struct mtk_pin_field_calc *c; 79 const struct mtk_pin_reg_calc *rc; 80 int start = 0, end, check; 81 bool found = false; 82 u32 bits; 83 84 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) { 85 rc = &hw->soc->reg_cal[field]; 86 } else { 87 dev_dbg(hw->dev, 88 "Not support field %d for this soc\n", field); 89 return -ENOTSUPP; 90 } 91 92 end = rc->nranges - 1; 93 94 while (start <= end) { 95 check = (start + end) >> 1; 96 if (desc->number >= rc->range[check].s_pin 97 && desc->number <= rc->range[check].e_pin) { 98 found = true; 99 break; 100 } else if (start == end) 101 break; 102 else if (desc->number < rc->range[check].s_pin) 103 end = check - 1; 104 else 105 start = check + 1; 106 } 107 108 if (!found) { 109 dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n", 110 field, desc->number, desc->name); 111 return -ENOTSUPP; 112 } 113 114 c = rc->range + check; 115 116 if (c->i_base > hw->nbase - 1) { 117 dev_err(hw->dev, 118 "Invalid base for field %d for pin = %d (%s)\n", 119 field, desc->number, desc->name); 120 return -EINVAL; 121 } 122 123 /* Calculated bits as the overall offset the pin is located at, 124 * if c->fixed is held, that determines the all the pins in the 125 * range use the same field with the s_pin. 126 */ 127 bits = c->fixed ? c->s_bit : c->s_bit + 128 (desc->number - c->s_pin) * (c->x_bits); 129 130 /* Fill pfd from bits. For example 32-bit register applied is assumed 131 * when c->sz_reg is equal to 32. 132 */ 133 pfd->index = c->i_base; 134 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg); 135 pfd->bitpos = bits % c->sz_reg; 136 pfd->mask = (1 << c->x_bits) - 1; 137 138 /* pfd->next is used for indicating that bit wrapping-around happens 139 * which requires the manipulation for bit 0 starting in the next 140 * register to form the complete field read/write. 141 */ 142 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0; 143 144 return 0; 145 } 146 147 static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw, 148 const struct mtk_pin_desc *desc, 149 int field, struct mtk_pin_field *pfd) 150 { 151 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) { 152 dev_err(hw->dev, "Invalid Field %d\n", field); 153 return -EINVAL; 154 } 155 156 return mtk_hw_pin_field_lookup(hw, desc, field, pfd); 157 } 158 159 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l) 160 { 161 *l = 32 - pf->bitpos; 162 *h = get_count_order(pf->mask) - *l; 163 } 164 165 static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw, 166 struct mtk_pin_field *pf, int value) 167 { 168 int nbits_l, nbits_h; 169 170 mtk_hw_bits_part(pf, &nbits_h, &nbits_l); 171 172 mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos, 173 (value & pf->mask) << pf->bitpos); 174 175 mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1, 176 (value & pf->mask) >> nbits_l); 177 } 178 179 static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw, 180 struct mtk_pin_field *pf, int *value) 181 { 182 int nbits_l, nbits_h, h, l; 183 184 mtk_hw_bits_part(pf, &nbits_h, &nbits_l); 185 186 l = (mtk_r32(hw, pf->index, pf->offset) 187 >> pf->bitpos) & (BIT(nbits_l) - 1); 188 h = (mtk_r32(hw, pf->index, pf->offset + pf->next)) 189 & (BIT(nbits_h) - 1); 190 191 *value = (h << nbits_l) | l; 192 } 193 194 int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, 195 int field, int value) 196 { 197 struct mtk_pin_field pf; 198 int err; 199 200 err = mtk_hw_pin_field_get(hw, desc, field, &pf); 201 if (err) 202 return err; 203 204 if (value < 0 || value > pf.mask) 205 return -EINVAL; 206 207 if (!pf.next) 208 mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, 209 (value & pf.mask) << pf.bitpos); 210 else 211 mtk_hw_write_cross_field(hw, &pf, value); 212 213 return 0; 214 } 215 EXPORT_SYMBOL_GPL(mtk_hw_set_value); 216 217 int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, 218 int field, int *value) 219 { 220 struct mtk_pin_field pf; 221 int err; 222 223 err = mtk_hw_pin_field_get(hw, desc, field, &pf); 224 if (err) 225 return err; 226 227 if (!pf.next) 228 *value = (mtk_r32(hw, pf.index, pf.offset) 229 >> pf.bitpos) & pf.mask; 230 else 231 mtk_hw_read_cross_field(hw, &pf, value); 232 233 return 0; 234 } 235 EXPORT_SYMBOL_GPL(mtk_hw_get_value); 236 237 static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n) 238 { 239 const struct mtk_pin_desc *desc; 240 int i = 0; 241 242 desc = (const struct mtk_pin_desc *)hw->soc->pins; 243 244 while (i < hw->soc->npins) { 245 if (desc[i].eint.eint_n == eint_n) 246 return desc[i].number; 247 i++; 248 } 249 250 return EINT_NA; 251 } 252 253 /* 254 * Virtual GPIO only used inside SOC and not being exported to outside SOC. 255 * Some modules use virtual GPIO as eint (e.g. pmif or usb). 256 * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping 257 * and we can set GPIO as eint. 258 * But some modules use specific eint which doesn't have real GPIO pin. 259 * So we use virtual GPIO to map it. 260 */ 261 262 bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n) 263 { 264 const struct mtk_pin_desc *desc; 265 bool virt_gpio = false; 266 267 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; 268 269 /* if the GPIO is not supported for eint mode */ 270 if (desc->eint.eint_m == NO_EINT_SUPPORT) 271 return virt_gpio; 272 273 if (desc->funcs && !desc->funcs[desc->eint.eint_m].name) 274 virt_gpio = true; 275 276 return virt_gpio; 277 } 278 EXPORT_SYMBOL_GPL(mtk_is_virt_gpio); 279 280 static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n, 281 unsigned int *gpio_n, 282 struct gpio_chip **gpio_chip) 283 { 284 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; 285 const struct mtk_pin_desc *desc; 286 287 desc = (const struct mtk_pin_desc *)hw->soc->pins; 288 *gpio_chip = &hw->chip; 289 290 /* 291 * Be greedy to guess first gpio_n is equal to eint_n. 292 * Only eint virtual eint number is greater than gpio number. 293 */ 294 if (hw->soc->npins > eint_n && 295 desc[eint_n].eint.eint_n == eint_n) 296 *gpio_n = eint_n; 297 else 298 *gpio_n = mtk_xt_find_eint_num(hw, eint_n); 299 300 return *gpio_n == EINT_NA ? -EINVAL : 0; 301 } 302 303 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n) 304 { 305 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; 306 const struct mtk_pin_desc *desc; 307 struct gpio_chip *gpio_chip; 308 unsigned int gpio_n; 309 int value, err; 310 311 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip); 312 if (err) 313 return err; 314 315 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; 316 317 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); 318 if (err) 319 return err; 320 321 return !!value; 322 } 323 324 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n) 325 { 326 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; 327 const struct mtk_pin_desc *desc; 328 struct gpio_chip *gpio_chip; 329 unsigned int gpio_n; 330 int err; 331 332 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip); 333 if (err) 334 return err; 335 336 if (mtk_is_virt_gpio(hw, gpio_n)) 337 return 0; 338 339 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; 340 341 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, 342 desc->eint.eint_m); 343 if (err) 344 return err; 345 346 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT); 347 if (err) 348 return err; 349 350 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE); 351 /* SMT is supposed to be supported by every real GPIO and doesn't 352 * support virtual GPIOs, so the extra condition err != -ENOTSUPP 353 * is just for adding EINT support to these virtual GPIOs. It should 354 * add an extra flag in the pin descriptor when more pins with 355 * distinctive characteristic come out. 356 */ 357 if (err && err != -ENOTSUPP) 358 return err; 359 360 return 0; 361 } 362 363 static const struct mtk_eint_xt mtk_eint_xt = { 364 .get_gpio_n = mtk_xt_get_gpio_n, 365 .get_gpio_state = mtk_xt_get_gpio_state, 366 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint, 367 }; 368 369 int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) 370 { 371 struct device_node *np = pdev->dev.of_node; 372 int ret, i, j, count_reg_names; 373 374 if (!IS_ENABLED(CONFIG_EINT_MTK)) 375 return 0; 376 377 if (!of_property_read_bool(np, "interrupt-controller")) 378 return -ENODEV; 379 380 hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL); 381 if (!hw->eint) 382 return -ENOMEM; 383 384 count_reg_names = of_property_count_strings(np, "reg-names"); 385 if (count_reg_names < 0) 386 return -EINVAL; 387 388 hw->eint->nbase = count_reg_names - (int)hw->soc->nbase_names; 389 if (hw->eint->nbase <= 0) 390 return -EINVAL; 391 392 hw->eint->base = devm_kmalloc_array(&pdev->dev, hw->eint->nbase, 393 sizeof(*hw->eint->base), GFP_KERNEL | __GFP_ZERO); 394 if (!hw->eint->base) { 395 ret = -ENOMEM; 396 goto err_free_base; 397 } 398 399 for (i = hw->soc->nbase_names, j = 0; i < count_reg_names; i++, j++) { 400 hw->eint->base[j] = of_iomap(np, i); 401 if (IS_ERR(hw->eint->base[j])) { 402 ret = PTR_ERR(hw->eint->base[j]); 403 goto err_free_eint; 404 } 405 } 406 407 hw->eint->irq = irq_of_parse_and_map(np, 0); 408 if (!hw->eint->irq) { 409 ret = -EINVAL; 410 goto err_free_eint; 411 } 412 413 if (!hw->soc->eint_hw) { 414 ret = -ENODEV; 415 goto err_free_eint; 416 } 417 418 hw->eint->dev = &pdev->dev; 419 hw->eint->hw = hw->soc->eint_hw; 420 hw->eint->pctl = hw; 421 hw->eint->gpio_xlate = &mtk_eint_xt; 422 423 ret = mtk_eint_do_init(hw->eint, hw->soc->eint_pin); 424 if (ret) 425 goto err_free_eint; 426 427 return 0; 428 429 err_free_eint: 430 for (j = 0; j < hw->eint->nbase; j++) { 431 if (hw->eint->base[j]) 432 iounmap(hw->eint->base[j]); 433 } 434 devm_kfree(hw->dev, hw->eint->base); 435 err_free_base: 436 devm_kfree(hw->dev, hw->eint); 437 hw->eint = NULL; 438 return ret; 439 } 440 EXPORT_SYMBOL_GPL(mtk_build_eint); 441 442 /* Revision 0 */ 443 int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, 444 const struct mtk_pin_desc *desc) 445 { 446 int err; 447 448 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, 449 MTK_DISABLE); 450 if (err) 451 return err; 452 453 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, 454 MTK_DISABLE); 455 if (err) 456 return err; 457 458 return 0; 459 } 460 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set); 461 462 int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, 463 const struct mtk_pin_desc *desc, int *res) 464 { 465 int v, v2; 466 int err; 467 468 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v); 469 if (err) 470 return err; 471 472 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2); 473 if (err) 474 return err; 475 476 if (v == MTK_ENABLE || v2 == MTK_ENABLE) 477 return -EINVAL; 478 479 *res = 1; 480 481 return 0; 482 } 483 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get); 484 485 int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, 486 const struct mtk_pin_desc *desc, bool pullup) 487 { 488 int err, arg; 489 490 arg = pullup ? 1 : 2; 491 492 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1); 493 if (err) 494 return err; 495 496 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, 497 !!(arg & 2)); 498 if (err) 499 return err; 500 501 return 0; 502 } 503 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set); 504 505 int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, 506 const struct mtk_pin_desc *desc, bool pullup, int *res) 507 { 508 int reg, err, v; 509 510 reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD; 511 512 err = mtk_hw_get_value(hw, desc, reg, &v); 513 if (err) 514 return err; 515 516 if (!v) 517 return -EINVAL; 518 519 *res = 1; 520 521 return 0; 522 } 523 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get); 524 525 /* Revision 1 */ 526 int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, 527 const struct mtk_pin_desc *desc) 528 { 529 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, 530 MTK_DISABLE); 531 } 532 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1); 533 534 int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, 535 const struct mtk_pin_desc *desc, int *res) 536 { 537 int v, err; 538 539 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v); 540 if (err) 541 return err; 542 543 if (v == MTK_ENABLE) 544 return -EINVAL; 545 546 *res = 1; 547 548 return 0; 549 } 550 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get_rev1); 551 552 int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, 553 const struct mtk_pin_desc *desc, bool pullup) 554 { 555 int err, arg; 556 557 arg = pullup ? MTK_PULLUP : MTK_PULLDOWN; 558 559 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, 560 MTK_ENABLE); 561 if (err) 562 return err; 563 564 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg); 565 if (err) 566 return err; 567 568 return 0; 569 } 570 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_rev1); 571 572 int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, 573 const struct mtk_pin_desc *desc, bool pullup, 574 int *res) 575 { 576 int err, v; 577 578 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v); 579 if (err) 580 return err; 581 582 if (v == MTK_DISABLE) 583 return -EINVAL; 584 585 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v); 586 if (err) 587 return err; 588 589 if (pullup ^ (v == MTK_PULLUP)) 590 return -EINVAL; 591 592 *res = 1; 593 594 return 0; 595 } 596 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1); 597 598 /* Combo for the following pull register type: 599 * 1. PU + PD 600 * 2. PULLSEL + PULLEN 601 * 3. PUPD + R0 + R1 602 */ 603 static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw, 604 const struct mtk_pin_desc *desc, 605 u32 pullup, u32 arg, bool pd_only) 606 { 607 int err, pu, pd; 608 609 if (arg == MTK_DISABLE) { 610 pu = 0; 611 pd = 0; 612 } else if ((arg == MTK_ENABLE) && pullup) { 613 pu = 1; 614 pd = 0; 615 } else if ((arg == MTK_ENABLE) && !pullup) { 616 pu = 0; 617 pd = 1; 618 } else { 619 return -EINVAL; 620 } 621 622 if (!pd_only) { 623 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu); 624 if (err) 625 return err; 626 } 627 628 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); 629 } 630 631 static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, 632 const struct mtk_pin_desc *desc, 633 u32 pullup, u32 arg) 634 { 635 int err, enable; 636 637 if (arg == MTK_DISABLE) 638 enable = 0; 639 else if (arg == MTK_ENABLE) 640 enable = 1; 641 else { 642 err = -EINVAL; 643 goto out; 644 } 645 646 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable); 647 if (err) 648 goto out; 649 650 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup); 651 652 out: 653 return err; 654 } 655 656 static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw, 657 const struct mtk_pin_desc *desc, 658 u32 pullup, u32 arg) 659 { 660 int err, r0, r1; 661 662 if ((arg == MTK_DISABLE) || (arg == MTK_PUPD_SET_R1R0_00)) { 663 pullup = 0; 664 r0 = 0; 665 r1 = 0; 666 } else if (arg == MTK_PUPD_SET_R1R0_01) { 667 r0 = 1; 668 r1 = 0; 669 } else if (arg == MTK_PUPD_SET_R1R0_10) { 670 r0 = 0; 671 r1 = 1; 672 } else if (arg == MTK_PUPD_SET_R1R0_11) { 673 r0 = 1; 674 r1 = 1; 675 } else { 676 err = -EINVAL; 677 goto out; 678 } 679 680 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */ 681 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, !pullup); 682 if (err) 683 goto out; 684 685 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, r0); 686 if (err) 687 goto out; 688 689 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, r1); 690 691 out: 692 return err; 693 } 694 695 static int mtk_hw_pin_rsel_lookup(struct mtk_pinctrl *hw, 696 const struct mtk_pin_desc *desc, 697 u32 pullup, u32 arg, u32 *rsel_val) 698 { 699 const struct mtk_pin_rsel *rsel; 700 int check; 701 bool found = false; 702 703 rsel = hw->soc->pin_rsel; 704 705 for (check = 0; check <= hw->soc->npin_rsel - 1; check++) { 706 if (desc->number >= rsel[check].s_pin && 707 desc->number <= rsel[check].e_pin) { 708 if (pullup) { 709 if (rsel[check].up_rsel == arg) { 710 found = true; 711 *rsel_val = rsel[check].rsel_index; 712 break; 713 } 714 } else { 715 if (rsel[check].down_rsel == arg) { 716 found = true; 717 *rsel_val = rsel[check].rsel_index; 718 break; 719 } 720 } 721 } 722 } 723 724 if (!found) { 725 dev_err(hw->dev, "Not support rsel value %d Ohm for pin = %d (%s)\n", 726 arg, desc->number, desc->name); 727 return -ENOTSUPP; 728 } 729 730 return 0; 731 } 732 733 static int mtk_pinconf_bias_set_rsel(struct mtk_pinctrl *hw, 734 const struct mtk_pin_desc *desc, 735 u32 pullup, u32 arg) 736 { 737 int err, rsel_val; 738 739 if (hw->rsel_si_unit) { 740 /* find pin rsel_index from pin_rsel array*/ 741 err = mtk_hw_pin_rsel_lookup(hw, desc, pullup, arg, &rsel_val); 742 if (err) 743 return err; 744 } else { 745 if (arg < MTK_PULL_SET_RSEL_000 || arg > MTK_PULL_SET_RSEL_111) 746 return -EINVAL; 747 748 rsel_val = arg - MTK_PULL_SET_RSEL_000; 749 } 750 751 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_RSEL, rsel_val); 752 } 753 754 static int mtk_pinconf_bias_set_pu_pd_rsel(struct mtk_pinctrl *hw, 755 const struct mtk_pin_desc *desc, 756 u32 pullup, u32 arg) 757 { 758 u32 enable = arg == MTK_DISABLE ? MTK_DISABLE : MTK_ENABLE; 759 int err; 760 761 if (arg != MTK_DISABLE) { 762 err = mtk_pinconf_bias_set_rsel(hw, desc, pullup, arg); 763 if (err) 764 return err; 765 } 766 767 return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable, false); 768 } 769 770 int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, 771 const struct mtk_pin_desc *desc, 772 u32 pullup, u32 arg) 773 { 774 int err = -ENOTSUPP; 775 u32 try_all_type; 776 777 if (hw->soc->pull_type) 778 try_all_type = hw->soc->pull_type[desc->number]; 779 else 780 try_all_type = MTK_PULL_TYPE_MASK; 781 782 if (try_all_type & MTK_PULL_RSEL_TYPE) { 783 err = mtk_pinconf_bias_set_pu_pd_rsel(hw, desc, pullup, arg); 784 if (!err) 785 return 0; 786 } 787 788 if (try_all_type & MTK_PULL_PD_TYPE) { 789 err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, true); 790 if (!err) 791 return err; 792 } 793 794 if (try_all_type & MTK_PULL_PU_PD_TYPE) { 795 err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, false); 796 if (!err) 797 return 0; 798 } 799 800 if (try_all_type & MTK_PULL_PULLSEL_TYPE) { 801 err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, 802 pullup, arg); 803 if (!err) 804 return 0; 805 } 806 807 if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE) 808 err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg); 809 810 if (err) 811 dev_err(hw->dev, "Invalid pull argument\n"); 812 813 return err; 814 } 815 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo); 816 817 static int mtk_rsel_get_si_unit(struct mtk_pinctrl *hw, 818 const struct mtk_pin_desc *desc, 819 u32 pullup, u32 rsel_val, u32 *si_unit) 820 { 821 const struct mtk_pin_rsel *rsel; 822 int check; 823 824 rsel = hw->soc->pin_rsel; 825 826 for (check = 0; check <= hw->soc->npin_rsel - 1; check++) { 827 if (desc->number >= rsel[check].s_pin && 828 desc->number <= rsel[check].e_pin) { 829 if (rsel_val == rsel[check].rsel_index) { 830 if (pullup) 831 *si_unit = rsel[check].up_rsel; 832 else 833 *si_unit = rsel[check].down_rsel; 834 break; 835 } 836 } 837 } 838 839 return 0; 840 } 841 842 static int mtk_pinconf_bias_get_pu_pd_rsel(struct mtk_pinctrl *hw, 843 const struct mtk_pin_desc *desc, 844 u32 *pullup, u32 *enable) 845 { 846 int pu, pd, rsel, err; 847 848 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_RSEL, &rsel); 849 if (err) 850 goto out; 851 852 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu); 853 if (err) 854 goto out; 855 856 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); 857 if (err) 858 goto out; 859 860 if (pu == 0 && pd == 0) { 861 *pullup = 0; 862 *enable = MTK_DISABLE; 863 } else if (pu == 1 && pd == 0) { 864 *pullup = 1; 865 if (hw->rsel_si_unit) 866 mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable); 867 else 868 *enable = rsel + MTK_PULL_SET_RSEL_000; 869 } else if (pu == 0 && pd == 1) { 870 *pullup = 0; 871 if (hw->rsel_si_unit) 872 mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable); 873 else 874 *enable = rsel + MTK_PULL_SET_RSEL_000; 875 } else { 876 err = -EINVAL; 877 goto out; 878 } 879 880 out: 881 return err; 882 } 883 884 static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw, 885 const struct mtk_pin_desc *desc, 886 u32 *pullup, u32 *enable) 887 { 888 int err, pu, pd; 889 890 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu); 891 if (err) 892 goto out; 893 894 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); 895 if (err) 896 goto out; 897 898 if (pu == 0 && pd == 0) { 899 *pullup = 0; 900 *enable = MTK_DISABLE; 901 } else if (pu == 1 && pd == 0) { 902 *pullup = 1; 903 *enable = MTK_ENABLE; 904 } else if (pu == 0 && pd == 1) { 905 *pullup = 0; 906 *enable = MTK_ENABLE; 907 } else 908 err = -EINVAL; 909 910 out: 911 return err; 912 } 913 914 static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw, 915 const struct mtk_pin_desc *desc, 916 u32 *pullup, u32 *enable) 917 { 918 int err, pd; 919 920 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); 921 if (err) 922 goto out; 923 924 if (pd == 0) { 925 *pullup = 0; 926 *enable = MTK_DISABLE; 927 } else if (pd == 1) { 928 *pullup = 0; 929 *enable = MTK_ENABLE; 930 } else 931 err = -EINVAL; 932 933 out: 934 return err; 935 } 936 937 static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw, 938 const struct mtk_pin_desc *desc, 939 u32 *pullup, u32 *enable) 940 { 941 int err; 942 943 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup); 944 if (err) 945 goto out; 946 947 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable); 948 949 out: 950 return err; 951 } 952 953 static int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl *hw, 954 const struct mtk_pin_desc *desc, 955 u32 *pullup, u32 *enable) 956 { 957 int err, r0, r1; 958 959 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, pullup); 960 if (err) 961 goto out; 962 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */ 963 *pullup = !(*pullup); 964 965 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &r0); 966 if (err) 967 goto out; 968 969 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &r1); 970 if (err) 971 goto out; 972 973 if ((r1 == 0) && (r0 == 0)) 974 *enable = MTK_PUPD_SET_R1R0_00; 975 else if ((r1 == 0) && (r0 == 1)) 976 *enable = MTK_PUPD_SET_R1R0_01; 977 else if ((r1 == 1) && (r0 == 0)) 978 *enable = MTK_PUPD_SET_R1R0_10; 979 else if ((r1 == 1) && (r0 == 1)) 980 *enable = MTK_PUPD_SET_R1R0_11; 981 else 982 err = -EINVAL; 983 984 out: 985 return err; 986 } 987 988 int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, 989 const struct mtk_pin_desc *desc, 990 u32 *pullup, u32 *enable) 991 { 992 int err = -ENOTSUPP; 993 u32 try_all_type; 994 995 if (hw->soc->pull_type) 996 try_all_type = hw->soc->pull_type[desc->number]; 997 else 998 try_all_type = MTK_PULL_TYPE_MASK; 999 1000 if (try_all_type & MTK_PULL_RSEL_TYPE) { 1001 err = mtk_pinconf_bias_get_pu_pd_rsel(hw, desc, pullup, enable); 1002 if (!err) 1003 return 0; 1004 } 1005 1006 if (try_all_type & MTK_PULL_PD_TYPE) { 1007 err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable); 1008 if (!err) 1009 return err; 1010 } 1011 1012 if (try_all_type & MTK_PULL_PU_PD_TYPE) { 1013 err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); 1014 if (!err) 1015 return 0; 1016 } 1017 1018 if (try_all_type & MTK_PULL_PULLSEL_TYPE) { 1019 err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, 1020 pullup, enable); 1021 if (!err) 1022 return 0; 1023 } 1024 1025 if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE) 1026 err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable); 1027 1028 return err; 1029 } 1030 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo); 1031 1032 /* Revision 0 */ 1033 int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, 1034 const struct mtk_pin_desc *desc, u32 arg) 1035 { 1036 const struct mtk_drive_desc *tb; 1037 int err = -ENOTSUPP; 1038 1039 tb = &mtk_drive[desc->drv_n]; 1040 /* 4mA when (e8, e4) = (0, 0) 1041 * 8mA when (e8, e4) = (0, 1) 1042 * 12mA when (e8, e4) = (1, 0) 1043 * 16mA when (e8, e4) = (1, 1) 1044 */ 1045 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { 1046 arg = (arg / tb->step - 1) * tb->scal; 1047 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4, 1048 arg & 0x1); 1049 if (err) 1050 return err; 1051 1052 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8, 1053 (arg & 0x2) >> 1); 1054 if (err) 1055 return err; 1056 } 1057 1058 return err; 1059 } 1060 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set); 1061 1062 int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, 1063 const struct mtk_pin_desc *desc, int *val) 1064 { 1065 const struct mtk_drive_desc *tb; 1066 int err, val1, val2; 1067 1068 tb = &mtk_drive[desc->drv_n]; 1069 1070 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1); 1071 if (err) 1072 return err; 1073 1074 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2); 1075 if (err) 1076 return err; 1077 1078 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1) 1079 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1) 1080 */ 1081 *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step; 1082 1083 return 0; 1084 } 1085 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get); 1086 1087 /* Revision 1 */ 1088 int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, 1089 const struct mtk_pin_desc *desc, u32 arg) 1090 { 1091 const struct mtk_drive_desc *tb; 1092 int err = -ENOTSUPP; 1093 1094 tb = &mtk_drive[desc->drv_n]; 1095 1096 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { 1097 arg = (arg / tb->step - 1) * tb->scal; 1098 1099 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, 1100 arg); 1101 if (err) 1102 return err; 1103 } 1104 1105 return err; 1106 } 1107 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_rev1); 1108 1109 int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, 1110 const struct mtk_pin_desc *desc, int *val) 1111 { 1112 const struct mtk_drive_desc *tb; 1113 int err, val1; 1114 1115 tb = &mtk_drive[desc->drv_n]; 1116 1117 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1); 1118 if (err) 1119 return err; 1120 1121 *val = ((val1 & 0x7) / tb->scal + 1) * tb->step; 1122 1123 return 0; 1124 } 1125 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_rev1); 1126 1127 int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw, 1128 const struct mtk_pin_desc *desc, u32 arg) 1129 { 1130 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg); 1131 } 1132 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_raw); 1133 1134 int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw, 1135 const struct mtk_pin_desc *desc, int *val) 1136 { 1137 return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val); 1138 } 1139 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_raw); 1140 1141 int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, 1142 const struct mtk_pin_desc *desc, bool pullup, 1143 u32 arg) 1144 { 1145 int err; 1146 1147 /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0); 1148 * 10K off & 50K (75K) on, when (R0, R1) = (0, 1); 1149 * 10K on & 50K (75K) off, when (R0, R1) = (1, 0); 1150 * 10K on & 50K (75K) on, when (R0, R1) = (1, 1) 1151 */ 1152 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1); 1153 if (err) 1154 return 0; 1155 1156 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, 1157 !!(arg & 2)); 1158 if (err) 1159 return 0; 1160 1161 arg = pullup ? 0 : 1; 1162 1163 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg); 1164 1165 /* If PUPD register is not supported for that pin, let's fallback to 1166 * general bias control. 1167 */ 1168 if (err == -ENOTSUPP) { 1169 if (hw->soc->bias_set) { 1170 err = hw->soc->bias_set(hw, desc, pullup); 1171 if (err) 1172 return err; 1173 } else { 1174 err = mtk_pinconf_bias_set_rev1(hw, desc, pullup); 1175 if (err) 1176 err = mtk_pinconf_bias_set(hw, desc, pullup); 1177 } 1178 } 1179 1180 return err; 1181 } 1182 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_set); 1183 1184 int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, 1185 const struct mtk_pin_desc *desc, bool pullup, 1186 u32 *val) 1187 { 1188 u32 t, t2; 1189 int err; 1190 1191 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t); 1192 1193 /* If PUPD register is not supported for that pin, let's fallback to 1194 * general bias control. 1195 */ 1196 if (err == -ENOTSUPP) { 1197 if (hw->soc->bias_get) { 1198 err = hw->soc->bias_get(hw, desc, pullup, val); 1199 if (err) 1200 return err; 1201 } else { 1202 return -ENOTSUPP; 1203 } 1204 } else { 1205 /* t == 0 supposes PULLUP for the customized PULL setup */ 1206 if (err) 1207 return err; 1208 1209 if (pullup ^ !t) 1210 return -EINVAL; 1211 } 1212 1213 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t); 1214 if (err) 1215 return err; 1216 1217 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2); 1218 if (err) 1219 return err; 1220 1221 *val = (t | t2 << 1) & 0x7; 1222 1223 return 0; 1224 } 1225 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_get); 1226 1227 int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, 1228 const struct mtk_pin_desc *desc, u32 arg) 1229 { 1230 int err; 1231 int en = arg & 1; 1232 int e0 = !!(arg & 2); 1233 int e1 = !!(arg & 4); 1234 1235 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en); 1236 if (err) 1237 return err; 1238 1239 if (!en) 1240 return err; 1241 1242 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0); 1243 if (err) 1244 return err; 1245 1246 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1); 1247 } 1248 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set); 1249 1250 int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, 1251 const struct mtk_pin_desc *desc, u32 *val) 1252 { 1253 u32 en, e0, e1; 1254 int err; 1255 1256 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en); 1257 if (err) 1258 return err; 1259 1260 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0); 1261 if (err) 1262 return err; 1263 1264 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1); 1265 if (err) 1266 return err; 1267 1268 *val = (en | e0 << 1 | e1 << 2) & 0x7; 1269 1270 return 0; 1271 } 1272 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get); 1273 1274 int mtk_pinconf_adv_drive_set_raw(struct mtk_pinctrl *hw, 1275 const struct mtk_pin_desc *desc, u32 arg) 1276 { 1277 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_ADV, arg); 1278 } 1279 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set_raw); 1280 1281 int mtk_pinconf_adv_drive_get_raw(struct mtk_pinctrl *hw, 1282 const struct mtk_pin_desc *desc, u32 *val) 1283 { 1284 return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_ADV, val); 1285 } 1286 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get_raw); 1287 1288 MODULE_LICENSE("GPL v2"); 1289 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 1290 MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs"); 1291