1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/pinctrl/pinctrl.h> 13 #include <linux/regmap.h> 14 #include <linux/pinctrl/pinconf-generic.h> 15 #include <dt-bindings/pinctrl/mt65xx.h> 16 17 #include "pinctrl-mtk-common.h" 18 #include "pinctrl-mtk-mt2712.h" 19 20 static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = { 21 MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0), 22 MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10), 23 MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3), 24 MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13), 25 MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6), 26 MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0), 27 28 MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0), 29 MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4), 30 MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8), 31 MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12), 32 MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0), 33 MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4), 34 MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8), 35 MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0), 36 MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0), 37 MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0), 38 MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0), 39 MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0), 40 MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0), 41 MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0), 42 MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0), 43 MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0), 44 MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0), 45 MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0), 46 MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0), 47 MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12), 48 MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8), 49 MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4), 50 MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0), 51 MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0), 52 MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0), 53 MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0), 54 MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0), 55 56 MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0), 57 MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12), 58 MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4), 59 MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8), 60 MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0), 61 MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0), 62 MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0), 63 MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0), 64 65 MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0), 66 MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12), 67 MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8), 68 MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4), 69 MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0), 70 MTK_PIN_PUPD_SPEC_SR(94, 0xd20, 2, 1, 0), 71 MTK_PIN_PUPD_SPEC_SR(95, 0xcf0, 2, 1, 0), 72 MTK_PIN_PUPD_SPEC_SR(96, 0xd30, 2, 1, 0), 73 74 MTK_PIN_PUPD_SPEC_SR(135, 0xe50, 11, 10, 9), 75 MTK_PIN_PUPD_SPEC_SR(136, 0xe50, 14, 13, 12), 76 MTK_PIN_PUPD_SPEC_SR(137, 0xe70, 5, 4, 3), 77 MTK_PIN_PUPD_SPEC_SR(138, 0xe70, 8, 7, 6), 78 MTK_PIN_PUPD_SPEC_SR(139, 0xe70, 11, 10, 9), 79 MTK_PIN_PUPD_SPEC_SR(140, 0xe70, 14, 13, 12), 80 MTK_PIN_PUPD_SPEC_SR(141, 0xe60, 2, 1, 0), 81 MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3) 82 }; 83 84 static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = { 85 MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2), 86 MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0), 87 MTK_PIN_IES_SMT_SPEC(8, 11, 0x900, 1), 88 MTK_PIN_IES_SMT_SPEC(12, 12, 0x8d0, 6), 89 MTK_PIN_IES_SMT_SPEC(13, 13, 0x8d0, 7), 90 MTK_PIN_IES_SMT_SPEC(14, 14, 0x8d0, 6), 91 MTK_PIN_IES_SMT_SPEC(15, 15, 0x8d0, 7), 92 MTK_PIN_IES_SMT_SPEC(18, 23, 0x8d0, 1), 93 MTK_PIN_IES_SMT_SPEC(24, 25, 0x8d0, 2), 94 MTK_PIN_IES_SMT_SPEC(26, 26, 0x8d0, 3), 95 MTK_PIN_IES_SMT_SPEC(27, 27, 0x8d0, 4), 96 MTK_PIN_IES_SMT_SPEC(28, 29, 0x8d0, 3), 97 MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 13), 98 MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 13), 99 MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 13), 100 MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 13), 101 MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 13), 102 MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 13), 103 MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 13), 104 MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 13), 105 MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 13), 106 MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 13), 107 MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 13), 108 MTK_PIN_IES_SMT_SPEC(57, 62, 0x900, 3), 109 MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 13), 110 MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 13), 111 MTK_PIN_IES_SMT_SPEC(67, 67, 0xc80, 13), 112 MTK_PIN_IES_SMT_SPEC(68, 68, 0xca0, 13), 113 MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 13), 114 MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 13), 115 MTK_PIN_IES_SMT_SPEC(71, 74, 0x8d0, 8), 116 MTK_PIN_IES_SMT_SPEC(75, 77, 0x8d0, 9), 117 MTK_PIN_IES_SMT_SPEC(78, 81, 0x8d0, 10), 118 MTK_PIN_IES_SMT_SPEC(82, 88, 0x8d0, 9), 119 MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 13), 120 MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 13), 121 MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 13), 122 MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 13), 123 MTK_PIN_IES_SMT_SPEC(97, 100, 0x8d0, 11), 124 MTK_PIN_IES_SMT_SPEC(101, 104, 0x8d0, 12), 125 MTK_PIN_IES_SMT_SPEC(105, 105, 0x8d0, 13), 126 MTK_PIN_IES_SMT_SPEC(106, 106, 0x8d0, 14), 127 MTK_PIN_IES_SMT_SPEC(107, 107, 0x8d0, 15), 128 MTK_PIN_IES_SMT_SPEC(108, 108, 0x8e0, 0), 129 MTK_PIN_IES_SMT_SPEC(109, 109, 0x8e0, 1), 130 MTK_PIN_IES_SMT_SPEC(110, 110, 0x8e0, 2), 131 MTK_PIN_IES_SMT_SPEC(111, 111, 0x8d0, 13), 132 MTK_PIN_IES_SMT_SPEC(112, 112, 0x8d0, 14), 133 MTK_PIN_IES_SMT_SPEC(113, 113, 0x8d0, 15), 134 MTK_PIN_IES_SMT_SPEC(114, 114, 0x8e0, 0), 135 MTK_PIN_IES_SMT_SPEC(115, 115, 0x8e0, 1), 136 MTK_PIN_IES_SMT_SPEC(116, 116, 0x8e0, 2), 137 MTK_PIN_IES_SMT_SPEC(117, 117, 0x8e0, 3), 138 MTK_PIN_IES_SMT_SPEC(118, 118, 0x8e0, 4), 139 MTK_PIN_IES_SMT_SPEC(119, 119, 0x8e0, 5), 140 MTK_PIN_IES_SMT_SPEC(120, 120, 0x8e0, 3), 141 MTK_PIN_IES_SMT_SPEC(121, 121, 0x8e0, 4), 142 MTK_PIN_IES_SMT_SPEC(122, 122, 0x8e0, 5), 143 MTK_PIN_IES_SMT_SPEC(123, 126, 0x8e0, 6), 144 MTK_PIN_IES_SMT_SPEC(127, 130, 0x8e0, 7), 145 MTK_PIN_IES_SMT_SPEC(131, 134, 0x8e0, 8), 146 MTK_PIN_IES_SMT_SPEC(135, 142, 0x8d0, 1), 147 MTK_PIN_IES_SMT_SPEC(143, 147, 0x8e0, 9), 148 MTK_PIN_IES_SMT_SPEC(148, 152, 0x8e0, 10), 149 MTK_PIN_IES_SMT_SPEC(153, 156, 0x8e0, 11), 150 MTK_PIN_IES_SMT_SPEC(157, 160, 0x8e0, 12), 151 MTK_PIN_IES_SMT_SPEC(161, 164, 0x8e0, 13), 152 MTK_PIN_IES_SMT_SPEC(165, 168, 0x8e0, 14), 153 MTK_PIN_IES_SMT_SPEC(169, 170, 0x8e0, 15), 154 MTK_PIN_IES_SMT_SPEC(171, 172, 0x8f0, 0), 155 MTK_PIN_IES_SMT_SPEC(173, 173, 0x8f0, 1), 156 MTK_PIN_IES_SMT_SPEC(174, 175, 0x8f0, 2), 157 MTK_PIN_IES_SMT_SPEC(176, 176, 0x8f0, 1), 158 MTK_PIN_IES_SMT_SPEC(177, 177, 0x8f0, 3), 159 MTK_PIN_IES_SMT_SPEC(178, 178, 0x8f0, 4), 160 MTK_PIN_IES_SMT_SPEC(179, 179, 0x8f0, 3), 161 MTK_PIN_IES_SMT_SPEC(180, 180, 0x8f0, 4), 162 MTK_PIN_IES_SMT_SPEC(181, 181, 0x8f0, 5), 163 MTK_PIN_IES_SMT_SPEC(182, 182, 0x8f0, 6), 164 MTK_PIN_IES_SMT_SPEC(183, 183, 0x8f0, 5), 165 MTK_PIN_IES_SMT_SPEC(184, 184, 0x8f0, 6), 166 MTK_PIN_IES_SMT_SPEC(185, 186, 0x8f0, 7), 167 MTK_PIN_IES_SMT_SPEC(187, 187, 0x8f0, 8), 168 MTK_PIN_IES_SMT_SPEC(188, 188, 0x8f0, 9), 169 MTK_PIN_IES_SMT_SPEC(189, 189, 0x8f0, 8), 170 MTK_PIN_IES_SMT_SPEC(190, 190, 0x8f0, 9), 171 MTK_PIN_IES_SMT_SPEC(191, 191, 0x8f0, 10), 172 MTK_PIN_IES_SMT_SPEC(192, 192, 0x8f0, 11), 173 MTK_PIN_IES_SMT_SPEC(193, 194, 0x8f0, 10), 174 MTK_PIN_IES_SMT_SPEC(195, 195, 0x8f0, 11), 175 MTK_PIN_IES_SMT_SPEC(196, 199, 0x8f0, 12), 176 MTK_PIN_IES_SMT_SPEC(200, 203, 0x8f0, 13), 177 MTK_PIN_IES_SMT_SPEC(204, 206, 0x8f0, 14), 178 MTK_PIN_IES_SMT_SPEC(207, 209, 0x8f0, 15) 179 }; 180 181 static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = { 182 MTK_PIN_IES_SMT_SPEC(0, 3, 0x8c0, 2), 183 MTK_PIN_IES_SMT_SPEC(4, 7, 0x8c0, 0), 184 MTK_PIN_IES_SMT_SPEC(8, 9, 0x8c0, 1), 185 MTK_PIN_IES_SMT_SPEC(10, 11, 0x8c0, 4), 186 MTK_PIN_IES_SMT_SPEC(12, 12, 0x890, 6), 187 MTK_PIN_IES_SMT_SPEC(13, 13, 0x890, 7), 188 MTK_PIN_IES_SMT_SPEC(14, 14, 0x890, 6), 189 MTK_PIN_IES_SMT_SPEC(15, 15, 0x890, 7), 190 MTK_PIN_IES_SMT_SPEC(18, 23, 0x890, 1), 191 MTK_PIN_IES_SMT_SPEC(24, 25, 0x890, 2), 192 MTK_PIN_IES_SMT_SPEC(26, 26, 0x890, 3), 193 MTK_PIN_IES_SMT_SPEC(27, 27, 0x890, 4), 194 MTK_PIN_IES_SMT_SPEC(28, 29, 0x890, 3), 195 MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 14), 196 MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 14), 197 MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 14), 198 MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 14), 199 MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 14), 200 MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 14), 201 MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 14), 202 MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 14), 203 MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 14), 204 MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 14), 205 MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 14), 206 MTK_PIN_IES_SMT_SPEC(57, 62, 0x8c0, 3), 207 MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 14), 208 MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 14), 209 MTK_PIN_IES_SMT_SPEC(67, 68, 0xc80, 14), 210 MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 14), 211 MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 14), 212 MTK_PIN_IES_SMT_SPEC(71, 74, 0x890, 8), 213 MTK_PIN_IES_SMT_SPEC(75, 77, 0x890, 9), 214 MTK_PIN_IES_SMT_SPEC(78, 81, 0x890, 10), 215 MTK_PIN_IES_SMT_SPEC(82, 88, 0x890, 9), 216 MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 14), 217 MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 14), 218 MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 14), 219 MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 14), 220 MTK_PIN_IES_SMT_SPEC(97, 100, 0x890, 11), 221 MTK_PIN_IES_SMT_SPEC(101, 104, 0x890, 12), 222 MTK_PIN_IES_SMT_SPEC(105, 105, 0x890, 13), 223 MTK_PIN_IES_SMT_SPEC(106, 106, 0x890, 14), 224 MTK_PIN_IES_SMT_SPEC(107, 107, 0x890, 15), 225 MTK_PIN_IES_SMT_SPEC(108, 108, 0x8a0, 0), 226 MTK_PIN_IES_SMT_SPEC(109, 109, 0x8a0, 1), 227 MTK_PIN_IES_SMT_SPEC(110, 110, 0x8a0, 2), 228 MTK_PIN_IES_SMT_SPEC(111, 111, 0x890, 13), 229 MTK_PIN_IES_SMT_SPEC(112, 112, 0x890, 14), 230 MTK_PIN_IES_SMT_SPEC(113, 113, 0x890, 15), 231 MTK_PIN_IES_SMT_SPEC(114, 114, 0x8a0, 0), 232 MTK_PIN_IES_SMT_SPEC(115, 115, 0x8a0, 1), 233 MTK_PIN_IES_SMT_SPEC(116, 116, 0x8a0, 2), 234 MTK_PIN_IES_SMT_SPEC(117, 117, 0x8a0, 3), 235 MTK_PIN_IES_SMT_SPEC(118, 118, 0x8a0, 4), 236 MTK_PIN_IES_SMT_SPEC(119, 119, 0x8a0, 5), 237 MTK_PIN_IES_SMT_SPEC(120, 120, 0x8a0, 3), 238 MTK_PIN_IES_SMT_SPEC(121, 121, 0x8a0, 4), 239 MTK_PIN_IES_SMT_SPEC(122, 122, 0x8a0, 5), 240 MTK_PIN_IES_SMT_SPEC(123, 126, 0x8a0, 6), 241 MTK_PIN_IES_SMT_SPEC(127, 130, 0x8a0, 7), 242 MTK_PIN_IES_SMT_SPEC(131, 135, 0x8a0, 8), 243 MTK_PIN_IES_SMT_SPEC(136, 142, 0x890, 1), 244 MTK_PIN_IES_SMT_SPEC(143, 147, 0x8a0, 9), 245 MTK_PIN_IES_SMT_SPEC(148, 152, 0x8a0, 10), 246 MTK_PIN_IES_SMT_SPEC(153, 156, 0x8a0, 11), 247 MTK_PIN_IES_SMT_SPEC(157, 160, 0x8a0, 12), 248 MTK_PIN_IES_SMT_SPEC(161, 164, 0x8a0, 13), 249 MTK_PIN_IES_SMT_SPEC(165, 168, 0x8a0, 14), 250 MTK_PIN_IES_SMT_SPEC(169, 170, 0x8a0, 15), 251 MTK_PIN_IES_SMT_SPEC(171, 172, 0x8b0, 0), 252 MTK_PIN_IES_SMT_SPEC(173, 173, 0x8b0, 1), 253 MTK_PIN_IES_SMT_SPEC(174, 175, 0x8b0, 2), 254 MTK_PIN_IES_SMT_SPEC(176, 176, 0x8b0, 1), 255 MTK_PIN_IES_SMT_SPEC(177, 177, 0x8b0, 3), 256 MTK_PIN_IES_SMT_SPEC(178, 178, 0x8b0, 4), 257 MTK_PIN_IES_SMT_SPEC(179, 179, 0x8b0, 3), 258 MTK_PIN_IES_SMT_SPEC(180, 180, 0x8b0, 4), 259 MTK_PIN_IES_SMT_SPEC(181, 181, 0x8b0, 5), 260 MTK_PIN_IES_SMT_SPEC(182, 182, 0x8b0, 6), 261 MTK_PIN_IES_SMT_SPEC(183, 183, 0x8b0, 5), 262 MTK_PIN_IES_SMT_SPEC(184, 184, 0x8b0, 6), 263 MTK_PIN_IES_SMT_SPEC(185, 186, 0x8b0, 7), 264 MTK_PIN_IES_SMT_SPEC(187, 187, 0x8b0, 8), 265 MTK_PIN_IES_SMT_SPEC(188, 188, 0x8b0, 9), 266 MTK_PIN_IES_SMT_SPEC(189, 189, 0x8b0, 8), 267 MTK_PIN_IES_SMT_SPEC(190, 190, 0x8b0, 9), 268 MTK_PIN_IES_SMT_SPEC(191, 191, 0x8b0, 10), 269 MTK_PIN_IES_SMT_SPEC(192, 192, 0x8b0, 11), 270 MTK_PIN_IES_SMT_SPEC(193, 194, 0x8b0, 10), 271 MTK_PIN_IES_SMT_SPEC(195, 195, 0x8b0, 11), 272 MTK_PIN_IES_SMT_SPEC(196, 199, 0x8b0, 12), 273 MTK_PIN_IES_SMT_SPEC(200, 203, 0x8b0, 13), 274 MTK_PIN_IES_SMT_SPEC(204, 206, 0x8b0, 14), 275 MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15) 276 }; 277 278 static const struct mtk_drv_group_desc mt2712_drv_grp[] = { 279 /* 0E4E8SR 4/8/12/16 */ 280 MTK_DRV_GRP(4, 16, 1, 2, 4), 281 /* 0E2E4SR 2/4/6/8 */ 282 MTK_DRV_GRP(2, 8, 1, 2, 2), 283 /* E8E4E2 2/4/6/8/10/12/14/16 */ 284 MTK_DRV_GRP(2, 16, 0, 2, 2) 285 }; 286 287 static const struct mtk_pin_drv_grp mt2712_pin_drv[] = { 288 MTK_PIN_DRV_GRP(0, 0xc10, 4, 0), 289 MTK_PIN_DRV_GRP(1, 0xc10, 4, 0), 290 MTK_PIN_DRV_GRP(2, 0xc10, 4, 0), 291 MTK_PIN_DRV_GRP(3, 0xc10, 4, 0), 292 293 MTK_PIN_DRV_GRP(4, 0xc00, 12, 0), 294 MTK_PIN_DRV_GRP(5, 0xc00, 12, 0), 295 MTK_PIN_DRV_GRP(6, 0xc00, 12, 0), 296 MTK_PIN_DRV_GRP(7, 0xc00, 12, 0), 297 298 MTK_PIN_DRV_GRP(8, 0xc10, 0, 0), 299 MTK_PIN_DRV_GRP(9, 0xc10, 0, 0), 300 MTK_PIN_DRV_GRP(10, 0xc10, 0, 0), 301 MTK_PIN_DRV_GRP(11, 0xc10, 0, 0), 302 303 MTK_PIN_DRV_GRP(12, 0xb60, 0, 0), 304 305 MTK_PIN_DRV_GRP(13, 0xb60, 4, 0), 306 307 MTK_PIN_DRV_GRP(14, 0xb60, 0, 0), 308 309 MTK_PIN_DRV_GRP(15, 0xb60, 4, 0), 310 311 MTK_PIN_DRV_GRP(18, 0xb40, 0, 1), 312 MTK_PIN_DRV_GRP(19, 0xb40, 0, 1), 313 MTK_PIN_DRV_GRP(20, 0xb40, 0, 1), 314 MTK_PIN_DRV_GRP(21, 0xb40, 0, 1), 315 MTK_PIN_DRV_GRP(22, 0xb40, 0, 1), 316 MTK_PIN_DRV_GRP(23, 0xb40, 0, 1), 317 318 MTK_PIN_DRV_GRP(24, 0xb40, 4, 0), 319 320 MTK_PIN_DRV_GRP(25, 0xb40, 8, 0), 321 322 MTK_PIN_DRV_GRP(26, 0xb40, 12, 0), 323 324 MTK_PIN_DRV_GRP(27, 0xb50, 0, 0), 325 326 MTK_PIN_DRV_GRP(28, 0xb40, 12, 0), 327 MTK_PIN_DRV_GRP(29, 0xb40, 12, 0), 328 329 MTK_PIN_DRV_GRP(30, 0xf50, 8, 2), 330 MTK_PIN_DRV_GRP(31, 0xf50, 8, 2), 331 MTK_PIN_DRV_GRP(32, 0xf50, 8, 2), 332 MTK_PIN_DRV_GRP(33, 0xf50, 8, 2), 333 MTK_PIN_DRV_GRP(34, 0xf50, 8, 2), 334 MTK_PIN_DRV_GRP(35, 0xf50, 8, 2), 335 MTK_PIN_DRV_GRP(36, 0xf50, 8, 2), 336 337 MTK_PIN_DRV_GRP(37, 0xc40, 8, 2), 338 339 MTK_PIN_DRV_GRP(38, 0xc60, 8, 2), 340 MTK_PIN_DRV_GRP(39, 0xc60, 8, 2), 341 MTK_PIN_DRV_GRP(40, 0xc60, 8, 2), 342 MTK_PIN_DRV_GRP(41, 0xc60, 8, 2), 343 MTK_PIN_DRV_GRP(42, 0xc60, 8, 2), 344 MTK_PIN_DRV_GRP(43, 0xc60, 8, 2), 345 MTK_PIN_DRV_GRP(44, 0xc60, 8, 2), 346 MTK_PIN_DRV_GRP(45, 0xc60, 8, 2), 347 348 MTK_PIN_DRV_GRP(46, 0xc50, 8, 2), 349 350 MTK_PIN_DRV_GRP(47, 0xda0, 8, 2), 351 352 MTK_PIN_DRV_GRP(48, 0xd90, 8, 2), 353 354 MTK_PIN_DRV_GRP(49, 0xd60, 8, 2), 355 MTK_PIN_DRV_GRP(50, 0xd60, 8, 2), 356 MTK_PIN_DRV_GRP(51, 0xd60, 8, 2), 357 MTK_PIN_DRV_GRP(52, 0xd60, 8, 2), 358 359 MTK_PIN_DRV_GRP(53, 0xd50, 8, 2), 360 361 MTK_PIN_DRV_GRP(54, 0xd80, 8, 2), 362 363 MTK_PIN_DRV_GRP(55, 0xe00, 8, 2), 364 365 MTK_PIN_DRV_GRP(56, 0xd40, 8, 2), 366 367 MTK_PIN_DRV_GRP(63, 0xc80, 8, 2), 368 369 MTK_PIN_DRV_GRP(64, 0xca0, 8, 2), 370 MTK_PIN_DRV_GRP(65, 0xca0, 8, 2), 371 MTK_PIN_DRV_GRP(66, 0xca0, 8, 2), 372 373 MTK_PIN_DRV_GRP(67, 0xcd0, 8, 2), 374 375 MTK_PIN_DRV_GRP(68, 0xca0, 8, 2), 376 377 MTK_PIN_DRV_GRP(69, 0xc90, 8, 2), 378 379 MTK_PIN_DRV_GRP(70, 0xcc0, 8, 2), 380 381 MTK_PIN_DRV_GRP(71, 0xb60, 8, 1), 382 MTK_PIN_DRV_GRP(72, 0xb60, 8, 1), 383 MTK_PIN_DRV_GRP(73, 0xb60, 8, 1), 384 MTK_PIN_DRV_GRP(74, 0xb60, 8, 1), 385 386 MTK_PIN_DRV_GRP(75, 0xb60, 12, 1), 387 MTK_PIN_DRV_GRP(76, 0xb60, 12, 1), 388 MTK_PIN_DRV_GRP(77, 0xb60, 12, 1), 389 390 MTK_PIN_DRV_GRP(78, 0xb70, 0, 1), 391 MTK_PIN_DRV_GRP(79, 0xb70, 0, 1), 392 MTK_PIN_DRV_GRP(80, 0xb70, 0, 1), 393 MTK_PIN_DRV_GRP(81, 0xb70, 0, 1), 394 395 MTK_PIN_DRV_GRP(82, 0xb60, 12, 1), 396 MTK_PIN_DRV_GRP(83, 0xb60, 12, 1), 397 MTK_PIN_DRV_GRP(84, 0xb60, 12, 1), 398 MTK_PIN_DRV_GRP(85, 0xb60, 12, 1), 399 MTK_PIN_DRV_GRP(86, 0xb60, 12, 1), 400 MTK_PIN_DRV_GRP(87, 0xb60, 12, 1), 401 MTK_PIN_DRV_GRP(88, 0xb60, 12, 1), 402 403 MTK_PIN_DRV_GRP(89, 0xce0, 8, 2), 404 405 MTK_PIN_DRV_GRP(90, 0xd00, 8, 2), 406 MTK_PIN_DRV_GRP(91, 0xd00, 8, 2), 407 MTK_PIN_DRV_GRP(92, 0xd00, 8, 2), 408 MTK_PIN_DRV_GRP(93, 0xd00, 8, 2), 409 410 MTK_PIN_DRV_GRP(94, 0xd20, 8, 2), 411 412 MTK_PIN_DRV_GRP(95, 0xcf0, 8, 2), 413 414 MTK_PIN_DRV_GRP(96, 0xd30, 8, 2), 415 416 MTK_PIN_DRV_GRP(97, 0xb70, 4, 0), 417 MTK_PIN_DRV_GRP(98, 0xb70, 4, 0), 418 MTK_PIN_DRV_GRP(99, 0xb70, 4, 0), 419 MTK_PIN_DRV_GRP(100, 0xb70, 4, 0), 420 421 MTK_PIN_DRV_GRP(101, 0xb70, 8, 0), 422 MTK_PIN_DRV_GRP(102, 0xb70, 8, 0), 423 MTK_PIN_DRV_GRP(103, 0xb70, 8, 0), 424 MTK_PIN_DRV_GRP(104, 0xb70, 8, 0), 425 426 MTK_PIN_DRV_GRP(135, 0xb40, 0, 1), 427 MTK_PIN_DRV_GRP(136, 0xb40, 0, 1), 428 MTK_PIN_DRV_GRP(137, 0xb40, 0, 1), 429 MTK_PIN_DRV_GRP(138, 0xb40, 0, 1), 430 MTK_PIN_DRV_GRP(139, 0xb40, 0, 1), 431 MTK_PIN_DRV_GRP(140, 0xb40, 0, 1), 432 MTK_PIN_DRV_GRP(141, 0xb40, 0, 1), 433 MTK_PIN_DRV_GRP(142, 0xb40, 0, 1), 434 435 MTK_PIN_DRV_GRP(143, 0xba0, 12, 0), 436 MTK_PIN_DRV_GRP(144, 0xba0, 12, 0), 437 MTK_PIN_DRV_GRP(145, 0xba0, 12, 0), 438 MTK_PIN_DRV_GRP(146, 0xba0, 12, 0), 439 MTK_PIN_DRV_GRP(147, 0xba0, 12, 0), 440 441 MTK_PIN_DRV_GRP(148, 0xbb0, 0, 0), 442 MTK_PIN_DRV_GRP(149, 0xbb0, 0, 0), 443 MTK_PIN_DRV_GRP(150, 0xbb0, 0, 0), 444 MTK_PIN_DRV_GRP(151, 0xbb0, 0, 0), 445 MTK_PIN_DRV_GRP(152, 0xbb0, 0, 0), 446 447 MTK_PIN_DRV_GRP(153, 0xbb0, 4, 0), 448 MTK_PIN_DRV_GRP(154, 0xbb0, 4, 0), 449 MTK_PIN_DRV_GRP(155, 0xbb0, 4, 0), 450 MTK_PIN_DRV_GRP(156, 0xbb0, 4, 0), 451 452 MTK_PIN_DRV_GRP(157, 0xbb0, 8, 0), 453 MTK_PIN_DRV_GRP(158, 0xbb0, 8, 0), 454 MTK_PIN_DRV_GRP(159, 0xbb0, 8, 0), 455 MTK_PIN_DRV_GRP(160, 0xbb0, 8, 0), 456 457 MTK_PIN_DRV_GRP(161, 0xbb0, 12, 0), 458 MTK_PIN_DRV_GRP(162, 0xbb0, 12, 0), 459 MTK_PIN_DRV_GRP(163, 0xbb0, 12, 0), 460 MTK_PIN_DRV_GRP(164, 0xbb0, 12, 0), 461 462 MTK_PIN_DRV_GRP(165, 0xbc0, 0, 0), 463 MTK_PIN_DRV_GRP(166, 0xbc0, 0, 0), 464 MTK_PIN_DRV_GRP(167, 0xbc0, 0, 0), 465 MTK_PIN_DRV_GRP(168, 0xbc0, 0, 0), 466 467 MTK_PIN_DRV_GRP(169, 0xbc0, 4, 0), 468 MTK_PIN_DRV_GRP(170, 0xbc0, 4, 0), 469 470 MTK_PIN_DRV_GRP(171, 0xbc0, 8, 0), 471 MTK_PIN_DRV_GRP(172, 0xbc0, 8, 0), 472 473 MTK_PIN_DRV_GRP(173, 0xbc0, 12, 0), 474 475 MTK_PIN_DRV_GRP(174, 0xbd0, 0, 0), 476 MTK_PIN_DRV_GRP(175, 0xbd0, 0, 0), 477 478 MTK_PIN_DRV_GRP(176, 0xbc0, 12, 0), 479 480 MTK_PIN_DRV_GRP(177, 0xbd0, 4, 0), 481 482 MTK_PIN_DRV_GRP(178, 0xbd0, 8, 0), 483 484 MTK_PIN_DRV_GRP(179, 0xbd0, 4, 0), 485 486 MTK_PIN_DRV_GRP(180, 0xbd0, 8, 0), 487 488 MTK_PIN_DRV_GRP(181, 0xbd0, 12, 0), 489 490 MTK_PIN_DRV_GRP(182, 0xbe0, 0, 0), 491 492 MTK_PIN_DRV_GRP(183, 0xbd0, 12, 0), 493 494 MTK_PIN_DRV_GRP(184, 0xbe0, 0, 0), 495 496 MTK_PIN_DRV_GRP(185, 0xbe0, 4, 0), 497 498 MTK_PIN_DRV_GRP(186, 0xbe0, 8, 0), 499 500 MTK_PIN_DRV_GRP(187, 0xbe0, 12, 0), 501 502 MTK_PIN_DRV_GRP(188, 0xbf0, 0, 0), 503 504 MTK_PIN_DRV_GRP(189, 0xbe0, 12, 0), 505 506 MTK_PIN_DRV_GRP(190, 0xbf0, 0, 0), 507 508 MTK_PIN_DRV_GRP(191, 0xbf0, 4, 0), 509 510 MTK_PIN_DRV_GRP(192, 0xbf0, 8, 0), 511 512 MTK_PIN_DRV_GRP(193, 0xbf0, 4, 0), 513 MTK_PIN_DRV_GRP(194, 0xbf0, 4, 0), 514 515 MTK_PIN_DRV_GRP(195, 0xbf0, 8, 0), 516 517 MTK_PIN_DRV_GRP(196, 0xbf0, 12, 0), 518 MTK_PIN_DRV_GRP(197, 0xbf0, 12, 0), 519 MTK_PIN_DRV_GRP(198, 0xbf0, 12, 0), 520 MTK_PIN_DRV_GRP(199, 0xbf0, 12, 0), 521 522 MTK_PIN_DRV_GRP(200, 0xc00, 0, 0), 523 MTK_PIN_DRV_GRP(201, 0xc00, 0, 0), 524 MTK_PIN_DRV_GRP(202, 0xc00, 0, 0), 525 MTK_PIN_DRV_GRP(203, 0xc00, 0, 0), 526 527 MTK_PIN_DRV_GRP(204, 0xc00, 4, 0), 528 MTK_PIN_DRV_GRP(205, 0xc00, 4, 0), 529 MTK_PIN_DRV_GRP(206, 0xc00, 4, 0), 530 531 MTK_PIN_DRV_GRP(207, 0xc00, 8, 0), 532 MTK_PIN_DRV_GRP(208, 0xc00, 8, 0), 533 MTK_PIN_DRV_GRP(209, 0xc00, 8, 0), 534 }; 535 536 static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = { 537 .pins = mtk_pins_mt2712, 538 .npins = ARRAY_SIZE(mtk_pins_mt2712), 539 .grp_desc = mt2712_drv_grp, 540 .n_grp_cls = ARRAY_SIZE(mt2712_drv_grp), 541 .pin_drv_grp = mt2712_pin_drv, 542 .n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv), 543 .spec_ies = mt2712_ies_set, 544 .n_spec_ies = ARRAY_SIZE(mt2712_ies_set), 545 .spec_pupd = mt2712_spec_pupd, 546 .n_spec_pupd = ARRAY_SIZE(mt2712_spec_pupd), 547 .spec_smt = mt2712_smt_set, 548 .n_spec_smt = ARRAY_SIZE(mt2712_smt_set), 549 .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, 550 .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, 551 .dir_offset = 0x0000, 552 .pullen_offset = 0x0100, 553 .pullsel_offset = 0x0200, 554 .dout_offset = 0x0300, 555 .din_offset = 0x0400, 556 .pinmux_offset = 0x0500, 557 .type1_start = 210, 558 .type1_end = 210, 559 .port_shf = 4, 560 .port_mask = 0xf, 561 .port_align = 4, 562 .mode_mask = 0xf, 563 .mode_per_reg = 5, 564 .mode_shf = 4, 565 .eint_hw = { 566 .port_mask = 0xf, 567 .ports = 8, 568 .ap_num = 229, 569 .db_cnt = 40, 570 }, 571 }; 572 573 static const struct of_device_id mt2712_pctrl_match[] = { 574 { .compatible = "mediatek,mt2712-pinctrl", .data = &mt2712_pinctrl_data }, 575 { } 576 }; 577 MODULE_DEVICE_TABLE(of, mt2712_pctrl_match); 578 579 static struct platform_driver mtk_pinctrl_driver = { 580 .probe = mtk_pctrl_common_probe, 581 .driver = { 582 .name = "mediatek-mt2712-pinctrl", 583 .of_match_table = mt2712_pctrl_match, 584 .pm = &mtk_eint_pm_ops, 585 }, 586 }; 587 588 static int __init mtk_pinctrl_init(void) 589 { 590 return platform_driver_register(&mtk_pinctrl_driver); 591 } 592 593 arch_initcall(mtk_pinctrl_init); 594