1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Sunrisepoint PCH pinctrl/GPIO driver 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 14 #include <linux/pinctrl/pinctrl.h> 15 16 #include "pinctrl-intel.h" 17 18 #define SPT_PAD_OWN 0x020 19 #define SPT_PADCFGLOCK 0x0a0 20 #define SPT_HOSTSW_OWN 0x0d0 21 #define SPT_GPI_IS 0x100 22 #define SPT_GPI_IE 0x120 23 24 #define SPT_COMMUNITY(b, s, e) \ 25 { \ 26 .barno = (b), \ 27 .padown_offset = SPT_PAD_OWN, \ 28 .padcfglock_offset = SPT_PADCFGLOCK, \ 29 .hostown_offset = SPT_HOSTSW_OWN, \ 30 .is_offset = SPT_GPI_IS, \ 31 .ie_offset = SPT_GPI_IE, \ 32 .gpp_size = 24, \ 33 .gpp_num_padown_regs = 4, \ 34 .pin_base = (s), \ 35 .npins = ((e) - (s) + 1), \ 36 } 37 38 #define SPTH_GPP(r, s, e, g) \ 39 { \ 40 .reg_num = (r), \ 41 .base = (s), \ 42 .size = ((e) - (s) + 1), \ 43 .gpio_base = (g), \ 44 } 45 46 #define SPTH_COMMUNITY(b, s, e, g) \ 47 { \ 48 .barno = (b), \ 49 .padown_offset = SPT_PAD_OWN, \ 50 .padcfglock_offset = SPT_PADCFGLOCK, \ 51 .hostown_offset = SPT_HOSTSW_OWN, \ 52 .ie_offset = SPT_GPI_IE, \ 53 .pin_base = (s), \ 54 .npins = ((e) - (s) + 1), \ 55 .gpps = (g), \ 56 .ngpps = ARRAY_SIZE(g), \ 57 } 58 59 /* Sunrisepoint-LP */ 60 static const struct pinctrl_pin_desc sptlp_pins[] = { 61 /* GPP_A */ 62 PINCTRL_PIN(0, "RCINB"), 63 PINCTRL_PIN(1, "LAD_0"), 64 PINCTRL_PIN(2, "LAD_1"), 65 PINCTRL_PIN(3, "LAD_2"), 66 PINCTRL_PIN(4, "LAD_3"), 67 PINCTRL_PIN(5, "LFRAMEB"), 68 PINCTRL_PIN(6, "SERIQ"), 69 PINCTRL_PIN(7, "PIRQAB"), 70 PINCTRL_PIN(8, "CLKRUNB"), 71 PINCTRL_PIN(9, "CLKOUT_LPC_0"), 72 PINCTRL_PIN(10, "CLKOUT_LPC_1"), 73 PINCTRL_PIN(11, "PMEB"), 74 PINCTRL_PIN(12, "BM_BUSYB"), 75 PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"), 76 PINCTRL_PIN(14, "SUS_STATB"), 77 PINCTRL_PIN(15, "SUSACKB"), 78 PINCTRL_PIN(16, "SD_1P8_SEL"), 79 PINCTRL_PIN(17, "SD_PWR_EN_B"), 80 PINCTRL_PIN(18, "ISH_GP_0"), 81 PINCTRL_PIN(19, "ISH_GP_1"), 82 PINCTRL_PIN(20, "ISH_GP_2"), 83 PINCTRL_PIN(21, "ISH_GP_3"), 84 PINCTRL_PIN(22, "ISH_GP_4"), 85 PINCTRL_PIN(23, "ISH_GP_5"), 86 /* GPP_B */ 87 PINCTRL_PIN(24, "CORE_VID_0"), 88 PINCTRL_PIN(25, "CORE_VID_1"), 89 PINCTRL_PIN(26, "VRALERTB"), 90 PINCTRL_PIN(27, "CPU_GP_2"), 91 PINCTRL_PIN(28, "CPU_GP_3"), 92 PINCTRL_PIN(29, "SRCCLKREQB_0"), 93 PINCTRL_PIN(30, "SRCCLKREQB_1"), 94 PINCTRL_PIN(31, "SRCCLKREQB_2"), 95 PINCTRL_PIN(32, "SRCCLKREQB_3"), 96 PINCTRL_PIN(33, "SRCCLKREQB_4"), 97 PINCTRL_PIN(34, "SRCCLKREQB_5"), 98 PINCTRL_PIN(35, "EXT_PWR_GATEB"), 99 PINCTRL_PIN(36, "SLP_S0B"), 100 PINCTRL_PIN(37, "PLTRSTB"), 101 PINCTRL_PIN(38, "SPKR"), 102 PINCTRL_PIN(39, "GSPI0_CSB"), 103 PINCTRL_PIN(40, "GSPI0_CLK"), 104 PINCTRL_PIN(41, "GSPI0_MISO"), 105 PINCTRL_PIN(42, "GSPI0_MOSI"), 106 PINCTRL_PIN(43, "GSPI1_CSB"), 107 PINCTRL_PIN(44, "GSPI1_CLK"), 108 PINCTRL_PIN(45, "GSPI1_MISO"), 109 PINCTRL_PIN(46, "GSPI1_MOSI"), 110 PINCTRL_PIN(47, "SML1ALERTB"), 111 /* GPP_C */ 112 PINCTRL_PIN(48, "SMBCLK"), 113 PINCTRL_PIN(49, "SMBDATA"), 114 PINCTRL_PIN(50, "SMBALERTB"), 115 PINCTRL_PIN(51, "SML0CLK"), 116 PINCTRL_PIN(52, "SML0DATA"), 117 PINCTRL_PIN(53, "SML0ALERTB"), 118 PINCTRL_PIN(54, "SML1CLK"), 119 PINCTRL_PIN(55, "SML1DATA"), 120 PINCTRL_PIN(56, "UART0_RXD"), 121 PINCTRL_PIN(57, "UART0_TXD"), 122 PINCTRL_PIN(58, "UART0_RTSB"), 123 PINCTRL_PIN(59, "UART0_CTSB"), 124 PINCTRL_PIN(60, "UART1_RXD"), 125 PINCTRL_PIN(61, "UART1_TXD"), 126 PINCTRL_PIN(62, "UART1_RTSB"), 127 PINCTRL_PIN(63, "UART1_CTSB"), 128 PINCTRL_PIN(64, "I2C0_SDA"), 129 PINCTRL_PIN(65, "I2C0_SCL"), 130 PINCTRL_PIN(66, "I2C1_SDA"), 131 PINCTRL_PIN(67, "I2C1_SCL"), 132 PINCTRL_PIN(68, "UART2_RXD"), 133 PINCTRL_PIN(69, "UART2_TXD"), 134 PINCTRL_PIN(70, "UART2_RTSB"), 135 PINCTRL_PIN(71, "UART2_CTSB"), 136 /* GPP_D */ 137 PINCTRL_PIN(72, "SPI1_CSB"), 138 PINCTRL_PIN(73, "SPI1_CLK"), 139 PINCTRL_PIN(74, "SPI1_MISO_IO_1"), 140 PINCTRL_PIN(75, "SPI1_MOSI_IO_0"), 141 PINCTRL_PIN(76, "FLASHTRIG"), 142 PINCTRL_PIN(77, "ISH_I2C0_SDA"), 143 PINCTRL_PIN(78, "ISH_I2C0_SCL"), 144 PINCTRL_PIN(79, "ISH_I2C1_SDA"), 145 PINCTRL_PIN(80, "ISH_I2C1_SCL"), 146 PINCTRL_PIN(81, "ISH_SPI_CSB"), 147 PINCTRL_PIN(82, "ISH_SPI_CLK"), 148 PINCTRL_PIN(83, "ISH_SPI_MISO"), 149 PINCTRL_PIN(84, "ISH_SPI_MOSI"), 150 PINCTRL_PIN(85, "ISH_UART0_RXD"), 151 PINCTRL_PIN(86, "ISH_UART0_TXD"), 152 PINCTRL_PIN(87, "ISH_UART0_RTSB"), 153 PINCTRL_PIN(88, "ISH_UART0_CTSB"), 154 PINCTRL_PIN(89, "DMIC_CLK_1"), 155 PINCTRL_PIN(90, "DMIC_DATA_1"), 156 PINCTRL_PIN(91, "DMIC_CLK_0"), 157 PINCTRL_PIN(92, "DMIC_DATA_0"), 158 PINCTRL_PIN(93, "SPI1_IO_2"), 159 PINCTRL_PIN(94, "SPI1_IO_3"), 160 PINCTRL_PIN(95, "SSP_MCLK"), 161 /* GPP_E */ 162 PINCTRL_PIN(96, "SATAXPCIE_0"), 163 PINCTRL_PIN(97, "SATAXPCIE_1"), 164 PINCTRL_PIN(98, "SATAXPCIE_2"), 165 PINCTRL_PIN(99, "CPU_GP_0"), 166 PINCTRL_PIN(100, "SATA_DEVSLP_0"), 167 PINCTRL_PIN(101, "SATA_DEVSLP_1"), 168 PINCTRL_PIN(102, "SATA_DEVSLP_2"), 169 PINCTRL_PIN(103, "CPU_GP_1"), 170 PINCTRL_PIN(104, "SATA_LEDB"), 171 PINCTRL_PIN(105, "USB2_OCB_0"), 172 PINCTRL_PIN(106, "USB2_OCB_1"), 173 PINCTRL_PIN(107, "USB2_OCB_2"), 174 PINCTRL_PIN(108, "USB2_OCB_3"), 175 PINCTRL_PIN(109, "DDSP_HPD_0"), 176 PINCTRL_PIN(110, "DDSP_HPD_1"), 177 PINCTRL_PIN(111, "DDSP_HPD_2"), 178 PINCTRL_PIN(112, "DDSP_HPD_3"), 179 PINCTRL_PIN(113, "EDP_HPD"), 180 PINCTRL_PIN(114, "DDPB_CTRLCLK"), 181 PINCTRL_PIN(115, "DDPB_CTRLDATA"), 182 PINCTRL_PIN(116, "DDPC_CTRLCLK"), 183 PINCTRL_PIN(117, "DDPC_CTRLDATA"), 184 PINCTRL_PIN(118, "DDPD_CTRLCLK"), 185 PINCTRL_PIN(119, "DDPD_CTRLDATA"), 186 /* GPP_F */ 187 PINCTRL_PIN(120, "SSP2_SCLK"), 188 PINCTRL_PIN(121, "SSP2_SFRM"), 189 PINCTRL_PIN(122, "SSP2_TXD"), 190 PINCTRL_PIN(123, "SSP2_RXD"), 191 PINCTRL_PIN(124, "I2C2_SDA"), 192 PINCTRL_PIN(125, "I2C2_SCL"), 193 PINCTRL_PIN(126, "I2C3_SDA"), 194 PINCTRL_PIN(127, "I2C3_SCL"), 195 PINCTRL_PIN(128, "I2C4_SDA"), 196 PINCTRL_PIN(129, "I2C4_SCL"), 197 PINCTRL_PIN(130, "I2C5_SDA"), 198 PINCTRL_PIN(131, "I2C5_SCL"), 199 PINCTRL_PIN(132, "EMMC_CMD"), 200 PINCTRL_PIN(133, "EMMC_DATA_0"), 201 PINCTRL_PIN(134, "EMMC_DATA_1"), 202 PINCTRL_PIN(135, "EMMC_DATA_2"), 203 PINCTRL_PIN(136, "EMMC_DATA_3"), 204 PINCTRL_PIN(137, "EMMC_DATA_4"), 205 PINCTRL_PIN(138, "EMMC_DATA_5"), 206 PINCTRL_PIN(139, "EMMC_DATA_6"), 207 PINCTRL_PIN(140, "EMMC_DATA_7"), 208 PINCTRL_PIN(141, "EMMC_RCLK"), 209 PINCTRL_PIN(142, "EMMC_CLK"), 210 PINCTRL_PIN(143, "GPP_F_23"), 211 /* GPP_G */ 212 PINCTRL_PIN(144, "SD_CMD"), 213 PINCTRL_PIN(145, "SD_DATA_0"), 214 PINCTRL_PIN(146, "SD_DATA_1"), 215 PINCTRL_PIN(147, "SD_DATA_2"), 216 PINCTRL_PIN(148, "SD_DATA_3"), 217 PINCTRL_PIN(149, "SD_CDB"), 218 PINCTRL_PIN(150, "SD_CLK"), 219 PINCTRL_PIN(151, "SD_WP"), 220 }; 221 222 static const unsigned sptlp_spi0_pins[] = { 39, 40, 41, 42 }; 223 static const unsigned sptlp_spi1_pins[] = { 43, 44, 45, 46 }; 224 static const unsigned sptlp_uart0_pins[] = { 56, 57, 58, 59 }; 225 static const unsigned sptlp_uart1_pins[] = { 60, 61, 62, 63 }; 226 static const unsigned sptlp_uart2_pins[] = { 68, 69, 71, 71 }; 227 static const unsigned sptlp_i2c0_pins[] = { 64, 65 }; 228 static const unsigned sptlp_i2c1_pins[] = { 66, 67 }; 229 static const unsigned sptlp_i2c2_pins[] = { 124, 125 }; 230 static const unsigned sptlp_i2c3_pins[] = { 126, 127 }; 231 static const unsigned sptlp_i2c4_pins[] = { 128, 129 }; 232 static const unsigned sptlp_i2c4b_pins[] = { 85, 86 }; 233 static const unsigned sptlp_i2c5_pins[] = { 130, 131 }; 234 static const unsigned sptlp_ssp2_pins[] = { 120, 121, 122, 123 }; 235 static const unsigned sptlp_emmc_pins[] = { 236 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 237 }; 238 static const unsigned sptlp_sd_pins[] = { 239 144, 145, 146, 147, 148, 149, 150, 151, 240 }; 241 242 static const struct intel_pingroup sptlp_groups[] = { 243 PIN_GROUP("spi0_grp", sptlp_spi0_pins, 1), 244 PIN_GROUP("spi1_grp", sptlp_spi1_pins, 1), 245 PIN_GROUP("uart0_grp", sptlp_uart0_pins, 1), 246 PIN_GROUP("uart1_grp", sptlp_uart1_pins, 1), 247 PIN_GROUP("uart2_grp", sptlp_uart2_pins, 1), 248 PIN_GROUP("i2c0_grp", sptlp_i2c0_pins, 1), 249 PIN_GROUP("i2c1_grp", sptlp_i2c1_pins, 1), 250 PIN_GROUP("i2c2_grp", sptlp_i2c2_pins, 1), 251 PIN_GROUP("i2c3_grp", sptlp_i2c3_pins, 1), 252 PIN_GROUP("i2c4_grp", sptlp_i2c4_pins, 1), 253 PIN_GROUP("i2c4b_grp", sptlp_i2c4b_pins, 3), 254 PIN_GROUP("i2c5_grp", sptlp_i2c5_pins, 1), 255 PIN_GROUP("ssp2_grp", sptlp_ssp2_pins, 1), 256 PIN_GROUP("emmc_grp", sptlp_emmc_pins, 1), 257 PIN_GROUP("sd_grp", sptlp_sd_pins, 1), 258 }; 259 260 static const char * const sptlp_spi0_groups[] = { "spi0_grp" }; 261 static const char * const sptlp_spi1_groups[] = { "spi0_grp" }; 262 static const char * const sptlp_uart0_groups[] = { "uart0_grp" }; 263 static const char * const sptlp_uart1_groups[] = { "uart1_grp" }; 264 static const char * const sptlp_uart2_groups[] = { "uart2_grp" }; 265 static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" }; 266 static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" }; 267 static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" }; 268 static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" }; 269 static const char * const sptlp_i2c4_groups[] = { "i2c4_grp", "i2c4b_grp" }; 270 static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" }; 271 static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" }; 272 static const char * const sptlp_emmc_groups[] = { "emmc_grp" }; 273 static const char * const sptlp_sd_groups[] = { "sd_grp" }; 274 275 static const struct intel_function sptlp_functions[] = { 276 FUNCTION("spi0", sptlp_spi0_groups), 277 FUNCTION("spi1", sptlp_spi1_groups), 278 FUNCTION("uart0", sptlp_uart0_groups), 279 FUNCTION("uart1", sptlp_uart1_groups), 280 FUNCTION("uart2", sptlp_uart2_groups), 281 FUNCTION("i2c0", sptlp_i2c0_groups), 282 FUNCTION("i2c1", sptlp_i2c1_groups), 283 FUNCTION("i2c2", sptlp_i2c2_groups), 284 FUNCTION("i2c3", sptlp_i2c3_groups), 285 FUNCTION("i2c4", sptlp_i2c4_groups), 286 FUNCTION("i2c5", sptlp_i2c5_groups), 287 FUNCTION("ssp2", sptlp_ssp2_groups), 288 FUNCTION("emmc", sptlp_emmc_groups), 289 FUNCTION("sd", sptlp_sd_groups), 290 }; 291 292 static const struct intel_community sptlp_communities[] = { 293 SPT_COMMUNITY(0, 0, 47), 294 SPT_COMMUNITY(1, 48, 119), 295 SPT_COMMUNITY(2, 120, 151), 296 }; 297 298 static const struct intel_pinctrl_soc_data sptlp_soc_data = { 299 .pins = sptlp_pins, 300 .npins = ARRAY_SIZE(sptlp_pins), 301 .groups = sptlp_groups, 302 .ngroups = ARRAY_SIZE(sptlp_groups), 303 .functions = sptlp_functions, 304 .nfunctions = ARRAY_SIZE(sptlp_functions), 305 .communities = sptlp_communities, 306 .ncommunities = ARRAY_SIZE(sptlp_communities), 307 }; 308 309 /* Sunrisepoint-H */ 310 static const struct pinctrl_pin_desc spth_pins[] = { 311 /* GPP_A */ 312 PINCTRL_PIN(0, "RCINB"), 313 PINCTRL_PIN(1, "LAD_0"), 314 PINCTRL_PIN(2, "LAD_1"), 315 PINCTRL_PIN(3, "LAD_2"), 316 PINCTRL_PIN(4, "LAD_3"), 317 PINCTRL_PIN(5, "LFRAMEB"), 318 PINCTRL_PIN(6, "SERIQ"), 319 PINCTRL_PIN(7, "PIRQAB"), 320 PINCTRL_PIN(8, "CLKRUNB"), 321 PINCTRL_PIN(9, "CLKOUT_LPC_0"), 322 PINCTRL_PIN(10, "CLKOUT_LPC_1"), 323 PINCTRL_PIN(11, "PMEB"), 324 PINCTRL_PIN(12, "BM_BUSYB"), 325 PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"), 326 PINCTRL_PIN(14, "SUS_STATB"), 327 PINCTRL_PIN(15, "SUSACKB"), 328 PINCTRL_PIN(16, "CLKOUT_48"), 329 PINCTRL_PIN(17, "ISH_GP_7"), 330 PINCTRL_PIN(18, "ISH_GP_0"), 331 PINCTRL_PIN(19, "ISH_GP_1"), 332 PINCTRL_PIN(20, "ISH_GP_2"), 333 PINCTRL_PIN(21, "ISH_GP_3"), 334 PINCTRL_PIN(22, "ISH_GP_4"), 335 PINCTRL_PIN(23, "ISH_GP_5"), 336 /* GPP_B */ 337 PINCTRL_PIN(24, "CORE_VID_0"), 338 PINCTRL_PIN(25, "CORE_VID_1"), 339 PINCTRL_PIN(26, "VRALERTB"), 340 PINCTRL_PIN(27, "CPU_GP_2"), 341 PINCTRL_PIN(28, "CPU_GP_3"), 342 PINCTRL_PIN(29, "SRCCLKREQB_0"), 343 PINCTRL_PIN(30, "SRCCLKREQB_1"), 344 PINCTRL_PIN(31, "SRCCLKREQB_2"), 345 PINCTRL_PIN(32, "SRCCLKREQB_3"), 346 PINCTRL_PIN(33, "SRCCLKREQB_4"), 347 PINCTRL_PIN(34, "SRCCLKREQB_5"), 348 PINCTRL_PIN(35, "EXT_PWR_GATEB"), 349 PINCTRL_PIN(36, "SLP_S0B"), 350 PINCTRL_PIN(37, "PLTRSTB"), 351 PINCTRL_PIN(38, "SPKR"), 352 PINCTRL_PIN(39, "GSPI0_CSB"), 353 PINCTRL_PIN(40, "GSPI0_CLK"), 354 PINCTRL_PIN(41, "GSPI0_MISO"), 355 PINCTRL_PIN(42, "GSPI0_MOSI"), 356 PINCTRL_PIN(43, "GSPI1_CSB"), 357 PINCTRL_PIN(44, "GSPI1_CLK"), 358 PINCTRL_PIN(45, "GSPI1_MISO"), 359 PINCTRL_PIN(46, "GSPI1_MOSI"), 360 PINCTRL_PIN(47, "SML1ALERTB"), 361 /* GPP_C */ 362 PINCTRL_PIN(48, "SMBCLK"), 363 PINCTRL_PIN(49, "SMBDATA"), 364 PINCTRL_PIN(50, "SMBALERTB"), 365 PINCTRL_PIN(51, "SML0CLK"), 366 PINCTRL_PIN(52, "SML0DATA"), 367 PINCTRL_PIN(53, "SML0ALERTB"), 368 PINCTRL_PIN(54, "SML1CLK"), 369 PINCTRL_PIN(55, "SML1DATA"), 370 PINCTRL_PIN(56, "UART0_RXD"), 371 PINCTRL_PIN(57, "UART0_TXD"), 372 PINCTRL_PIN(58, "UART0_RTSB"), 373 PINCTRL_PIN(59, "UART0_CTSB"), 374 PINCTRL_PIN(60, "UART1_RXD"), 375 PINCTRL_PIN(61, "UART1_TXD"), 376 PINCTRL_PIN(62, "UART1_RTSB"), 377 PINCTRL_PIN(63, "UART1_CTSB"), 378 PINCTRL_PIN(64, "I2C0_SDA"), 379 PINCTRL_PIN(65, "I2C0_SCL"), 380 PINCTRL_PIN(66, "I2C1_SDA"), 381 PINCTRL_PIN(67, "I2C1_SCL"), 382 PINCTRL_PIN(68, "UART2_RXD"), 383 PINCTRL_PIN(69, "UART2_TXD"), 384 PINCTRL_PIN(70, "UART2_RTSB"), 385 PINCTRL_PIN(71, "UART2_CTSB"), 386 /* GPP_D */ 387 PINCTRL_PIN(72, "SPI1_CSB"), 388 PINCTRL_PIN(73, "SPI1_CLK"), 389 PINCTRL_PIN(74, "SPI1_MISO_IO_1"), 390 PINCTRL_PIN(75, "SPI1_MOSI_IO_0"), 391 PINCTRL_PIN(76, "ISH_I2C2_SDA"), 392 PINCTRL_PIN(77, "SSP0_SFRM"), 393 PINCTRL_PIN(78, "SSP0_TXD"), 394 PINCTRL_PIN(79, "SSP0_RXD"), 395 PINCTRL_PIN(80, "SSP0_SCLK"), 396 PINCTRL_PIN(81, "ISH_SPI_CSB"), 397 PINCTRL_PIN(82, "ISH_SPI_CLK"), 398 PINCTRL_PIN(83, "ISH_SPI_MISO"), 399 PINCTRL_PIN(84, "ISH_SPI_MOSI"), 400 PINCTRL_PIN(85, "ISH_UART0_RXD"), 401 PINCTRL_PIN(86, "ISH_UART0_TXD"), 402 PINCTRL_PIN(87, "ISH_UART0_RTSB"), 403 PINCTRL_PIN(88, "ISH_UART0_CTSB"), 404 PINCTRL_PIN(89, "DMIC_CLK_1"), 405 PINCTRL_PIN(90, "DMIC_DATA_1"), 406 PINCTRL_PIN(91, "DMIC_CLK_0"), 407 PINCTRL_PIN(92, "DMIC_DATA_0"), 408 PINCTRL_PIN(93, "SPI1_IO_2"), 409 PINCTRL_PIN(94, "SPI1_IO_3"), 410 PINCTRL_PIN(95, "ISH_I2C2_SCL"), 411 /* GPP_E */ 412 PINCTRL_PIN(96, "SATAXPCIE_0"), 413 PINCTRL_PIN(97, "SATAXPCIE_1"), 414 PINCTRL_PIN(98, "SATAXPCIE_2"), 415 PINCTRL_PIN(99, "CPU_GP_0"), 416 PINCTRL_PIN(100, "SATA_DEVSLP_0"), 417 PINCTRL_PIN(101, "SATA_DEVSLP_1"), 418 PINCTRL_PIN(102, "SATA_DEVSLP_2"), 419 PINCTRL_PIN(103, "CPU_GP_1"), 420 PINCTRL_PIN(104, "SATA_LEDB"), 421 PINCTRL_PIN(105, "USB2_OCB_0"), 422 PINCTRL_PIN(106, "USB2_OCB_1"), 423 PINCTRL_PIN(107, "USB2_OCB_2"), 424 PINCTRL_PIN(108, "USB2_OCB_3"), 425 /* GPP_F */ 426 PINCTRL_PIN(109, "SATAXPCIE_3"), 427 PINCTRL_PIN(110, "SATAXPCIE_4"), 428 PINCTRL_PIN(111, "SATAXPCIE_5"), 429 PINCTRL_PIN(112, "SATAXPCIE_6"), 430 PINCTRL_PIN(113, "SATAXPCIE_7"), 431 PINCTRL_PIN(114, "SATA_DEVSLP_3"), 432 PINCTRL_PIN(115, "SATA_DEVSLP_4"), 433 PINCTRL_PIN(116, "SATA_DEVSLP_5"), 434 PINCTRL_PIN(117, "SATA_DEVSLP_6"), 435 PINCTRL_PIN(118, "SATA_DEVSLP_7"), 436 PINCTRL_PIN(119, "SATA_SCLOCK"), 437 PINCTRL_PIN(120, "SATA_SLOAD"), 438 PINCTRL_PIN(121, "SATA_SDATAOUT1"), 439 PINCTRL_PIN(122, "SATA_SDATAOUT0"), 440 PINCTRL_PIN(123, "GPP_F_14"), 441 PINCTRL_PIN(124, "USB_OCB_4"), 442 PINCTRL_PIN(125, "USB_OCB_5"), 443 PINCTRL_PIN(126, "USB_OCB_6"), 444 PINCTRL_PIN(127, "USB_OCB_7"), 445 PINCTRL_PIN(128, "L_VDDEN"), 446 PINCTRL_PIN(129, "L_BKLTEN"), 447 PINCTRL_PIN(130, "L_BKLTCTL"), 448 PINCTRL_PIN(131, "GPP_F_22"), 449 PINCTRL_PIN(132, "GPP_F_23"), 450 /* GPP_G */ 451 PINCTRL_PIN(133, "FAN_TACH_0"), 452 PINCTRL_PIN(134, "FAN_TACH_1"), 453 PINCTRL_PIN(135, "FAN_TACH_2"), 454 PINCTRL_PIN(136, "FAN_TACH_3"), 455 PINCTRL_PIN(137, "FAN_TACH_4"), 456 PINCTRL_PIN(138, "FAN_TACH_5"), 457 PINCTRL_PIN(139, "FAN_TACH_6"), 458 PINCTRL_PIN(140, "FAN_TACH_7"), 459 PINCTRL_PIN(141, "FAN_PWM_0"), 460 PINCTRL_PIN(142, "FAN_PWM_1"), 461 PINCTRL_PIN(143, "FAN_PWM_2"), 462 PINCTRL_PIN(144, "FAN_PWM_3"), 463 PINCTRL_PIN(145, "GSXDOUT"), 464 PINCTRL_PIN(146, "GSXSLOAD"), 465 PINCTRL_PIN(147, "GSXDIN"), 466 PINCTRL_PIN(148, "GSXRESETB"), 467 PINCTRL_PIN(149, "GSXCLK"), 468 PINCTRL_PIN(150, "ADR_COMPLETE"), 469 PINCTRL_PIN(151, "NMIB"), 470 PINCTRL_PIN(152, "SMIB"), 471 PINCTRL_PIN(153, "GPP_G_20"), 472 PINCTRL_PIN(154, "GPP_G_21"), 473 PINCTRL_PIN(155, "GPP_G_22"), 474 PINCTRL_PIN(156, "GPP_G_23"), 475 /* GPP_H */ 476 PINCTRL_PIN(157, "SRCCLKREQB_6"), 477 PINCTRL_PIN(158, "SRCCLKREQB_7"), 478 PINCTRL_PIN(159, "SRCCLKREQB_8"), 479 PINCTRL_PIN(160, "SRCCLKREQB_9"), 480 PINCTRL_PIN(161, "SRCCLKREQB_10"), 481 PINCTRL_PIN(162, "SRCCLKREQB_11"), 482 PINCTRL_PIN(163, "SRCCLKREQB_12"), 483 PINCTRL_PIN(164, "SRCCLKREQB_13"), 484 PINCTRL_PIN(165, "SRCCLKREQB_14"), 485 PINCTRL_PIN(166, "SRCCLKREQB_15"), 486 PINCTRL_PIN(167, "SML2CLK"), 487 PINCTRL_PIN(168, "SML2DATA"), 488 PINCTRL_PIN(169, "SML2ALERTB"), 489 PINCTRL_PIN(170, "SML3CLK"), 490 PINCTRL_PIN(171, "SML3DATA"), 491 PINCTRL_PIN(172, "SML3ALERTB"), 492 PINCTRL_PIN(173, "SML4CLK"), 493 PINCTRL_PIN(174, "SML4DATA"), 494 PINCTRL_PIN(175, "SML4ALERTB"), 495 PINCTRL_PIN(176, "ISH_I2C0_SDA"), 496 PINCTRL_PIN(177, "ISH_I2C0_SCL"), 497 PINCTRL_PIN(178, "ISH_I2C1_SDA"), 498 PINCTRL_PIN(179, "ISH_I2C1_SCL"), 499 PINCTRL_PIN(180, "GPP_H_23"), 500 /* GPP_I */ 501 PINCTRL_PIN(181, "DDSP_HDP_0"), 502 PINCTRL_PIN(182, "DDSP_HDP_1"), 503 PINCTRL_PIN(183, "DDSP_HDP_2"), 504 PINCTRL_PIN(184, "DDSP_HDP_3"), 505 PINCTRL_PIN(185, "EDP_HPD"), 506 PINCTRL_PIN(186, "DDPB_CTRLCLK"), 507 PINCTRL_PIN(187, "DDPB_CTRLDATA"), 508 PINCTRL_PIN(188, "DDPC_CTRLCLK"), 509 PINCTRL_PIN(189, "DDPC_CTRLDATA"), 510 PINCTRL_PIN(190, "DDPD_CTRLCLK"), 511 PINCTRL_PIN(191, "DDPD_CTRLDATA"), 512 }; 513 514 static const unsigned spth_spi0_pins[] = { 39, 40, 41, 42 }; 515 static const unsigned spth_spi1_pins[] = { 43, 44, 45, 46 }; 516 static const unsigned spth_uart0_pins[] = { 56, 57, 58, 59 }; 517 static const unsigned spth_uart1_pins[] = { 60, 61, 62, 63 }; 518 static const unsigned spth_uart2_pins[] = { 68, 69, 71, 71 }; 519 static const unsigned spth_i2c0_pins[] = { 64, 65 }; 520 static const unsigned spth_i2c1_pins[] = { 66, 67 }; 521 static const unsigned spth_i2c2_pins[] = { 76, 95 }; 522 523 static const struct intel_pingroup spth_groups[] = { 524 PIN_GROUP("spi0_grp", spth_spi0_pins, 1), 525 PIN_GROUP("spi1_grp", spth_spi1_pins, 1), 526 PIN_GROUP("uart0_grp", spth_uart0_pins, 1), 527 PIN_GROUP("uart1_grp", spth_uart1_pins, 1), 528 PIN_GROUP("uart2_grp", spth_uart2_pins, 1), 529 PIN_GROUP("i2c0_grp", spth_i2c0_pins, 1), 530 PIN_GROUP("i2c1_grp", spth_i2c1_pins, 1), 531 PIN_GROUP("i2c2_grp", spth_i2c2_pins, 2), 532 }; 533 534 static const char * const spth_spi0_groups[] = { "spi0_grp" }; 535 static const char * const spth_spi1_groups[] = { "spi0_grp" }; 536 static const char * const spth_uart0_groups[] = { "uart0_grp" }; 537 static const char * const spth_uart1_groups[] = { "uart1_grp" }; 538 static const char * const spth_uart2_groups[] = { "uart2_grp" }; 539 static const char * const spth_i2c0_groups[] = { "i2c0_grp" }; 540 static const char * const spth_i2c1_groups[] = { "i2c1_grp" }; 541 static const char * const spth_i2c2_groups[] = { "i2c2_grp" }; 542 543 static const struct intel_function spth_functions[] = { 544 FUNCTION("spi0", spth_spi0_groups), 545 FUNCTION("spi1", spth_spi1_groups), 546 FUNCTION("uart0", spth_uart0_groups), 547 FUNCTION("uart1", spth_uart1_groups), 548 FUNCTION("uart2", spth_uart2_groups), 549 FUNCTION("i2c0", spth_i2c0_groups), 550 FUNCTION("i2c1", spth_i2c1_groups), 551 FUNCTION("i2c2", spth_i2c2_groups), 552 }; 553 554 static const struct intel_padgroup spth_community0_gpps[] = { 555 SPTH_GPP(0, 0, 23, 0), /* GPP_A */ 556 SPTH_GPP(1, 24, 47, 24), /* GPP_B */ 557 }; 558 559 static const struct intel_padgroup spth_community1_gpps[] = { 560 SPTH_GPP(0, 48, 71, 48), /* GPP_C */ 561 SPTH_GPP(1, 72, 95, 72), /* GPP_D */ 562 SPTH_GPP(2, 96, 108, 96), /* GPP_E */ 563 SPTH_GPP(3, 109, 132, 120), /* GPP_F */ 564 SPTH_GPP(4, 133, 156, 144), /* GPP_G */ 565 SPTH_GPP(5, 157, 180, 168), /* GPP_H */ 566 }; 567 568 static const struct intel_padgroup spth_community3_gpps[] = { 569 SPTH_GPP(0, 181, 191, 192), /* GPP_I */ 570 }; 571 572 static const struct intel_community spth_communities[] = { 573 SPTH_COMMUNITY(0, 0, 47, spth_community0_gpps), 574 SPTH_COMMUNITY(1, 48, 180, spth_community1_gpps), 575 SPTH_COMMUNITY(2, 181, 191, spth_community3_gpps), 576 }; 577 578 static const struct intel_pinctrl_soc_data spth_soc_data = { 579 .pins = spth_pins, 580 .npins = ARRAY_SIZE(spth_pins), 581 .groups = spth_groups, 582 .ngroups = ARRAY_SIZE(spth_groups), 583 .functions = spth_functions, 584 .nfunctions = ARRAY_SIZE(spth_functions), 585 .communities = spth_communities, 586 .ncommunities = ARRAY_SIZE(spth_communities), 587 }; 588 589 static const struct acpi_device_id spt_pinctrl_acpi_match[] = { 590 { "INT344B", (kernel_ulong_t)&sptlp_soc_data }, 591 { "INT345D", (kernel_ulong_t)&spth_soc_data }, 592 { } 593 }; 594 MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match); 595 596 static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops); 597 598 static struct platform_driver spt_pinctrl_driver = { 599 .probe = intel_pinctrl_probe_by_hid, 600 .driver = { 601 .name = "sunrisepoint-pinctrl", 602 .acpi_match_table = spt_pinctrl_acpi_match, 603 .pm = &spt_pinctrl_pm_ops, 604 }, 605 }; 606 607 static int __init spt_pinctrl_init(void) 608 { 609 return platform_driver_register(&spt_pinctrl_driver); 610 } 611 subsys_initcall(spt_pinctrl_init); 612 613 static void __exit spt_pinctrl_exit(void) 614 { 615 platform_driver_unregister(&spt_pinctrl_driver); 616 } 617 module_exit(spt_pinctrl_exit); 618 619 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 620 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 621 MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver"); 622 MODULE_LICENSE("GPL v2"); 623