1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Merrifield SoC pinctrl driver 4 * 5 * Copyright (C) 2016, Intel Corporation 6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7 */ 8 9 #include <linux/bits.h> 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/mod_devicetable.h> 14 #include <linux/platform_device.h> 15 #include <linux/pinctrl/pinconf.h> 16 #include <linux/pinctrl/pinconf-generic.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 20 #include "pinctrl-intel.h" 21 22 #define MRFLD_FAMILY_NR 64 23 #define MRFLD_FAMILY_LEN 0x400 24 25 #define SLEW_OFFSET 0x000 26 #define BUFCFG_OFFSET 0x100 27 #define MISC_OFFSET 0x300 28 29 #define BUFCFG_PINMODE_SHIFT 0 30 #define BUFCFG_PINMODE_MASK GENMASK(2, 0) 31 #define BUFCFG_PINMODE_GPIO 0 32 #define BUFCFG_PUPD_VAL_SHIFT 4 33 #define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4) 34 #define BUFCFG_PUPD_VAL_2K 0 35 #define BUFCFG_PUPD_VAL_20K 1 36 #define BUFCFG_PUPD_VAL_50K 2 37 #define BUFCFG_PUPD_VAL_910 3 38 #define BUFCFG_PU_EN BIT(8) 39 #define BUFCFG_PD_EN BIT(9) 40 #define BUFCFG_Px_EN_MASK GENMASK(9, 8) 41 #define BUFCFG_SLEWSEL BIT(10) 42 #define BUFCFG_OVINEN BIT(12) 43 #define BUFCFG_OVINEN_EN BIT(13) 44 #define BUFCFG_OVINEN_MASK GENMASK(13, 12) 45 #define BUFCFG_OVOUTEN BIT(14) 46 #define BUFCFG_OVOUTEN_EN BIT(15) 47 #define BUFCFG_OVOUTEN_MASK GENMASK(15, 14) 48 #define BUFCFG_INDATAOV_VAL BIT(16) 49 #define BUFCFG_INDATAOV_EN BIT(17) 50 #define BUFCFG_INDATAOV_MASK GENMASK(17, 16) 51 #define BUFCFG_OUTDATAOV_VAL BIT(18) 52 #define BUFCFG_OUTDATAOV_EN BIT(19) 53 #define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18) 54 #define BUFCFG_OD_EN BIT(21) 55 56 /** 57 * struct mrfld_family - Intel pin family description 58 * @barno: MMIO BAR number where registers for this family reside 59 * @pin_base: Starting pin of pins in this family 60 * @npins: Number of pins in this family 61 * @protected: True if family is protected by access 62 * @regs: family specific common registers 63 */ 64 struct mrfld_family { 65 unsigned int barno; 66 unsigned int pin_base; 67 size_t npins; 68 bool protected; 69 void __iomem *regs; 70 }; 71 72 #define MRFLD_FAMILY(b, s, e) \ 73 { \ 74 .barno = (b), \ 75 .pin_base = (s), \ 76 .npins = (e) - (s) + 1, \ 77 } 78 79 #define MRFLD_FAMILY_PROTECTED(b, s, e) \ 80 { \ 81 .barno = (b), \ 82 .pin_base = (s), \ 83 .npins = (e) - (s) + 1, \ 84 .protected = true, \ 85 } 86 87 static const struct pinctrl_pin_desc mrfld_pins[] = { 88 /* Family 0: OCP2SSC (0 pins) */ 89 /* Family 1: ULPI (13 pins) */ 90 PINCTRL_PIN(0, "ULPI_CLK"), 91 PINCTRL_PIN(1, "ULPI_D0"), 92 PINCTRL_PIN(2, "ULPI_D1"), 93 PINCTRL_PIN(3, "ULPI_D2"), 94 PINCTRL_PIN(4, "ULPI_D3"), 95 PINCTRL_PIN(5, "ULPI_D4"), 96 PINCTRL_PIN(6, "ULPI_D5"), 97 PINCTRL_PIN(7, "ULPI_D6"), 98 PINCTRL_PIN(8, "ULPI_D7"), 99 PINCTRL_PIN(9, "ULPI_DIR"), 100 PINCTRL_PIN(10, "ULPI_NXT"), 101 PINCTRL_PIN(11, "ULPI_REFCLK"), 102 PINCTRL_PIN(12, "ULPI_STP"), 103 /* Family 2: eMMC (24 pins) */ 104 PINCTRL_PIN(13, "EMMC_CLK"), 105 PINCTRL_PIN(14, "EMMC_CMD"), 106 PINCTRL_PIN(15, "EMMC_D0"), 107 PINCTRL_PIN(16, "EMMC_D1"), 108 PINCTRL_PIN(17, "EMMC_D2"), 109 PINCTRL_PIN(18, "EMMC_D3"), 110 PINCTRL_PIN(19, "EMMC_D4"), 111 PINCTRL_PIN(20, "EMMC_D5"), 112 PINCTRL_PIN(21, "EMMC_D6"), 113 PINCTRL_PIN(22, "EMMC_D7"), 114 PINCTRL_PIN(23, "EMMC_RST_N"), 115 PINCTRL_PIN(24, "GP154"), 116 PINCTRL_PIN(25, "GP155"), 117 PINCTRL_PIN(26, "GP156"), 118 PINCTRL_PIN(27, "GP157"), 119 PINCTRL_PIN(28, "GP158"), 120 PINCTRL_PIN(29, "GP159"), 121 PINCTRL_PIN(30, "GP160"), 122 PINCTRL_PIN(31, "GP161"), 123 PINCTRL_PIN(32, "GP162"), 124 PINCTRL_PIN(33, "GP163"), 125 PINCTRL_PIN(34, "GP97"), 126 PINCTRL_PIN(35, "GP14"), 127 PINCTRL_PIN(36, "GP15"), 128 /* Family 3: SDIO (20 pins) */ 129 PINCTRL_PIN(37, "GP77_SD_CD"), 130 PINCTRL_PIN(38, "GP78_SD_CLK"), 131 PINCTRL_PIN(39, "GP79_SD_CMD"), 132 PINCTRL_PIN(40, "GP80_SD_D0"), 133 PINCTRL_PIN(41, "GP81_SD_D1"), 134 PINCTRL_PIN(42, "GP82_SD_D2"), 135 PINCTRL_PIN(43, "GP83_SD_D3"), 136 PINCTRL_PIN(44, "GP84_SD_LS_CLK_FB"), 137 PINCTRL_PIN(45, "GP85_SD_LS_CMD_DIR"), 138 PINCTRL_PIN(46, "GP86_SD_LS_D_DIR"), 139 PINCTRL_PIN(47, "GP88_SD_LS_SEL"), 140 PINCTRL_PIN(48, "GP87_SD_PD"), 141 PINCTRL_PIN(49, "GP89_SD_WP"), 142 PINCTRL_PIN(50, "GP90_SDIO_CLK"), 143 PINCTRL_PIN(51, "GP91_SDIO_CMD"), 144 PINCTRL_PIN(52, "GP92_SDIO_D0"), 145 PINCTRL_PIN(53, "GP93_SDIO_D1"), 146 PINCTRL_PIN(54, "GP94_SDIO_D2"), 147 PINCTRL_PIN(55, "GP95_SDIO_D3"), 148 PINCTRL_PIN(56, "GP96_SDIO_PD"), 149 /* Family 4: HSI (8 pins) */ 150 PINCTRL_PIN(57, "HSI_ACDATA"), 151 PINCTRL_PIN(58, "HSI_ACFLAG"), 152 PINCTRL_PIN(59, "HSI_ACREADY"), 153 PINCTRL_PIN(60, "HSI_ACWAKE"), 154 PINCTRL_PIN(61, "HSI_CADATA"), 155 PINCTRL_PIN(62, "HSI_CAFLAG"), 156 PINCTRL_PIN(63, "HSI_CAREADY"), 157 PINCTRL_PIN(64, "HSI_CAWAKE"), 158 /* Family 5: SSP Audio (14 pins) */ 159 PINCTRL_PIN(65, "GP70"), 160 PINCTRL_PIN(66, "GP71"), 161 PINCTRL_PIN(67, "GP32_I2S_0_CLK"), 162 PINCTRL_PIN(68, "GP33_I2S_0_FS"), 163 PINCTRL_PIN(69, "GP34_I2S_0_RXD"), 164 PINCTRL_PIN(70, "GP35_I2S_0_TXD"), 165 PINCTRL_PIN(71, "GP36_I2S_1_CLK"), 166 PINCTRL_PIN(72, "GP37_I2S_1_FS"), 167 PINCTRL_PIN(73, "GP38_I2S_1_RXD"), 168 PINCTRL_PIN(74, "GP39_I2S_1_TXD"), 169 PINCTRL_PIN(75, "GP40_I2S_2_CLK"), 170 PINCTRL_PIN(76, "GP41_I2S_2_FS"), 171 PINCTRL_PIN(77, "GP42_I2S_2_RXD"), 172 PINCTRL_PIN(78, "GP43_I2S_2_TXD"), 173 /* Family 6: GP SSP (22 pins) */ 174 PINCTRL_PIN(79, "GP120_SPI_0_CLK"), 175 PINCTRL_PIN(80, "GP121_SPI_0_SS"), 176 PINCTRL_PIN(81, "GP122_SPI_0_RXD"), 177 PINCTRL_PIN(82, "GP123_SPI_0_TXD"), 178 PINCTRL_PIN(83, "GP102_SPI_1_CLK"), 179 PINCTRL_PIN(84, "GP103_SPI_1_SS0"), 180 PINCTRL_PIN(85, "GP104_SPI_1_SS1"), 181 PINCTRL_PIN(86, "GP105_SPI_1_SS2"), 182 PINCTRL_PIN(87, "GP106_SPI_1_SS3"), 183 PINCTRL_PIN(88, "GP107_SPI_1_RXD"), 184 PINCTRL_PIN(89, "GP108_SPI_1_TXD"), 185 PINCTRL_PIN(90, "GP109_SPI_2_CLK"), 186 PINCTRL_PIN(91, "GP110_SPI_2_SS0"), 187 PINCTRL_PIN(92, "GP111_SPI_2_SS1"), 188 PINCTRL_PIN(93, "GP112_SPI_2_SS2"), 189 PINCTRL_PIN(94, "GP113_SPI_2_SS3"), 190 PINCTRL_PIN(95, "GP114_SPI_2_RXD"), 191 PINCTRL_PIN(96, "GP115_SPI_2_TXD"), 192 PINCTRL_PIN(97, "GP116_SPI_3_CLK"), 193 PINCTRL_PIN(98, "GP117_SPI_3_SS"), 194 PINCTRL_PIN(99, "GP118_SPI_3_RXD"), 195 PINCTRL_PIN(100, "GP119_SPI_3_TXD"), 196 /* Family 7: I2C (14 pins) */ 197 PINCTRL_PIN(101, "GP19_I2C_1_SCL"), 198 PINCTRL_PIN(102, "GP20_I2C_1_SDA"), 199 PINCTRL_PIN(103, "GP21_I2C_2_SCL"), 200 PINCTRL_PIN(104, "GP22_I2C_2_SDA"), 201 PINCTRL_PIN(105, "GP17_I2C_3_SCL_HDMI"), 202 PINCTRL_PIN(106, "GP18_I2C_3_SDA_HDMI"), 203 PINCTRL_PIN(107, "GP23_I2C_4_SCL"), 204 PINCTRL_PIN(108, "GP24_I2C_4_SDA"), 205 PINCTRL_PIN(109, "GP25_I2C_5_SCL"), 206 PINCTRL_PIN(110, "GP26_I2C_5_SDA"), 207 PINCTRL_PIN(111, "GP27_I2C_6_SCL"), 208 PINCTRL_PIN(112, "GP28_I2C_6_SDA"), 209 PINCTRL_PIN(113, "GP29_I2C_7_SCL"), 210 PINCTRL_PIN(114, "GP30_I2C_7_SDA"), 211 /* Family 8: UART (12 pins) */ 212 PINCTRL_PIN(115, "GP124_UART_0_CTS"), 213 PINCTRL_PIN(116, "GP125_UART_0_RTS"), 214 PINCTRL_PIN(117, "GP126_UART_0_RX"), 215 PINCTRL_PIN(118, "GP127_UART_0_TX"), 216 PINCTRL_PIN(119, "GP128_UART_1_CTS"), 217 PINCTRL_PIN(120, "GP129_UART_1_RTS"), 218 PINCTRL_PIN(121, "GP130_UART_1_RX"), 219 PINCTRL_PIN(122, "GP131_UART_1_TX"), 220 PINCTRL_PIN(123, "GP132_UART_2_CTS"), 221 PINCTRL_PIN(124, "GP133_UART_2_RTS"), 222 PINCTRL_PIN(125, "GP134_UART_2_RX"), 223 PINCTRL_PIN(126, "GP135_UART_2_TX"), 224 /* Family 9: GPIO South (19 pins) */ 225 PINCTRL_PIN(127, "GP177"), 226 PINCTRL_PIN(128, "GP178"), 227 PINCTRL_PIN(129, "GP179"), 228 PINCTRL_PIN(130, "GP180"), 229 PINCTRL_PIN(131, "GP181"), 230 PINCTRL_PIN(132, "GP182_PWM2"), 231 PINCTRL_PIN(133, "GP183_PWM3"), 232 PINCTRL_PIN(134, "GP184"), 233 PINCTRL_PIN(135, "GP185"), 234 PINCTRL_PIN(136, "GP186"), 235 PINCTRL_PIN(137, "GP187"), 236 PINCTRL_PIN(138, "GP188"), 237 PINCTRL_PIN(139, "GP189"), 238 PINCTRL_PIN(140, "GP64_FAST_INT0"), 239 PINCTRL_PIN(141, "GP65_FAST_INT1"), 240 PINCTRL_PIN(142, "GP66_FAST_INT2"), 241 PINCTRL_PIN(143, "GP67_FAST_INT3"), 242 PINCTRL_PIN(144, "GP12_PWM0"), 243 PINCTRL_PIN(145, "GP13_PWM1"), 244 /* Family 10: Camera Sideband (12 pins) */ 245 PINCTRL_PIN(146, "GP0"), 246 PINCTRL_PIN(147, "GP1"), 247 PINCTRL_PIN(148, "GP2"), 248 PINCTRL_PIN(149, "GP3"), 249 PINCTRL_PIN(150, "GP4"), 250 PINCTRL_PIN(151, "GP5"), 251 PINCTRL_PIN(152, "GP6"), 252 PINCTRL_PIN(153, "GP7"), 253 PINCTRL_PIN(154, "GP8"), 254 PINCTRL_PIN(155, "GP9"), 255 PINCTRL_PIN(156, "GP10"), 256 PINCTRL_PIN(157, "GP11"), 257 /* Family 11: Clock (22 pins) */ 258 PINCTRL_PIN(158, "GP137"), 259 PINCTRL_PIN(159, "GP138"), 260 PINCTRL_PIN(160, "GP139"), 261 PINCTRL_PIN(161, "GP140"), 262 PINCTRL_PIN(162, "GP141"), 263 PINCTRL_PIN(163, "GP142"), 264 PINCTRL_PIN(164, "GP16_HDMI_HPD"), 265 PINCTRL_PIN(165, "GP68_DSI_A_TE"), 266 PINCTRL_PIN(166, "GP69_DSI_C_TE"), 267 PINCTRL_PIN(167, "OSC_CLK_CTRL0"), 268 PINCTRL_PIN(168, "OSC_CLK_CTRL1"), 269 PINCTRL_PIN(169, "OSC_CLK0"), 270 PINCTRL_PIN(170, "OSC_CLK1"), 271 PINCTRL_PIN(171, "OSC_CLK2"), 272 PINCTRL_PIN(172, "OSC_CLK3"), 273 PINCTRL_PIN(173, "OSC_CLK4"), 274 PINCTRL_PIN(174, "RESETOUT"), 275 PINCTRL_PIN(175, "PMODE"), 276 PINCTRL_PIN(176, "PRDY"), 277 PINCTRL_PIN(177, "PREQ"), 278 PINCTRL_PIN(178, "GP190"), 279 PINCTRL_PIN(179, "GP191"), 280 /* Family 12: MSIC (15 pins) */ 281 PINCTRL_PIN(180, "I2C_0_SCL"), 282 PINCTRL_PIN(181, "I2C_0_SDA"), 283 PINCTRL_PIN(182, "IERR"), 284 PINCTRL_PIN(183, "JTAG_TCK"), 285 PINCTRL_PIN(184, "JTAG_TDI"), 286 PINCTRL_PIN(185, "JTAG_TDO"), 287 PINCTRL_PIN(186, "JTAG_TMS"), 288 PINCTRL_PIN(187, "JTAG_TRST"), 289 PINCTRL_PIN(188, "PROCHOT"), 290 PINCTRL_PIN(189, "RTC_CLK"), 291 PINCTRL_PIN(190, "SVID_ALERT"), 292 PINCTRL_PIN(191, "SVID_CLK"), 293 PINCTRL_PIN(192, "SVID_D"), 294 PINCTRL_PIN(193, "THERMTRIP"), 295 PINCTRL_PIN(194, "STANDBY"), 296 /* Family 13: Keyboard (20 pins) */ 297 PINCTRL_PIN(195, "GP44"), 298 PINCTRL_PIN(196, "GP45"), 299 PINCTRL_PIN(197, "GP46"), 300 PINCTRL_PIN(198, "GP47"), 301 PINCTRL_PIN(199, "GP48"), 302 PINCTRL_PIN(200, "GP49"), 303 PINCTRL_PIN(201, "GP50"), 304 PINCTRL_PIN(202, "GP51"), 305 PINCTRL_PIN(203, "GP52"), 306 PINCTRL_PIN(204, "GP53"), 307 PINCTRL_PIN(205, "GP54"), 308 PINCTRL_PIN(206, "GP55"), 309 PINCTRL_PIN(207, "GP56"), 310 PINCTRL_PIN(208, "GP57"), 311 PINCTRL_PIN(209, "GP58"), 312 PINCTRL_PIN(210, "GP59"), 313 PINCTRL_PIN(211, "GP60"), 314 PINCTRL_PIN(212, "GP61"), 315 PINCTRL_PIN(213, "GP62"), 316 PINCTRL_PIN(214, "GP63"), 317 /* Family 14: GPIO North (13 pins) */ 318 PINCTRL_PIN(215, "GP164"), 319 PINCTRL_PIN(216, "GP165"), 320 PINCTRL_PIN(217, "GP166"), 321 PINCTRL_PIN(218, "GP167"), 322 PINCTRL_PIN(219, "GP168_MJTAG_TCK"), 323 PINCTRL_PIN(220, "GP169_MJTAG_TDI"), 324 PINCTRL_PIN(221, "GP170_MJTAG_TDO"), 325 PINCTRL_PIN(222, "GP171_MJTAG_TMS"), 326 PINCTRL_PIN(223, "GP172_MJTAG_TRST"), 327 PINCTRL_PIN(224, "GP173"), 328 PINCTRL_PIN(225, "GP174"), 329 PINCTRL_PIN(226, "GP175"), 330 PINCTRL_PIN(227, "GP176"), 331 /* Family 15: PTI (5 pins) */ 332 PINCTRL_PIN(228, "GP72_PTI_CLK"), 333 PINCTRL_PIN(229, "GP73_PTI_D0"), 334 PINCTRL_PIN(230, "GP74_PTI_D1"), 335 PINCTRL_PIN(231, "GP75_PTI_D2"), 336 PINCTRL_PIN(232, "GP76_PTI_D3"), 337 /* Family 16: USB3 (0 pins) */ 338 /* Family 17: HSIC (0 pins) */ 339 /* Family 18: Broadcast (0 pins) */ 340 }; 341 342 static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 }; 343 static const unsigned int mrfld_i2s2_pins[] = { 75, 76, 77, 78 }; 344 static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 }; 345 static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 }; 346 static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 }; 347 static const unsigned int mrfld_uart2_pins[] = { 123, 124, 125, 126 }; 348 static const unsigned int mrfld_pwm0_pins[] = { 144 }; 349 static const unsigned int mrfld_pwm1_pins[] = { 145 }; 350 static const unsigned int mrfld_pwm2_pins[] = { 132 }; 351 static const unsigned int mrfld_pwm3_pins[] = { 133 }; 352 353 static const struct intel_pingroup mrfld_groups[] = { 354 PIN_GROUP("sdio_grp", mrfld_sdio_pins, 1), 355 PIN_GROUP("i2s2_grp", mrfld_i2s2_pins, 1), 356 PIN_GROUP("spi5_grp", mrfld_spi5_pins, 1), 357 PIN_GROUP("uart0_grp", mrfld_uart0_pins, 1), 358 PIN_GROUP("uart1_grp", mrfld_uart1_pins, 1), 359 PIN_GROUP("uart2_grp", mrfld_uart2_pins, 1), 360 PIN_GROUP("pwm0_grp", mrfld_pwm0_pins, 1), 361 PIN_GROUP("pwm1_grp", mrfld_pwm1_pins, 1), 362 PIN_GROUP("pwm2_grp", mrfld_pwm2_pins, 1), 363 PIN_GROUP("pwm3_grp", mrfld_pwm3_pins, 1), 364 }; 365 366 static const char * const mrfld_sdio_groups[] = { "sdio_grp" }; 367 static const char * const mrfld_i2s2_groups[] = { "i2s2_grp" }; 368 static const char * const mrfld_spi5_groups[] = { "spi5_grp" }; 369 static const char * const mrfld_uart0_groups[] = { "uart0_grp" }; 370 static const char * const mrfld_uart1_groups[] = { "uart1_grp" }; 371 static const char * const mrfld_uart2_groups[] = { "uart2_grp" }; 372 static const char * const mrfld_pwm0_groups[] = { "pwm0_grp" }; 373 static const char * const mrfld_pwm1_groups[] = { "pwm1_grp" }; 374 static const char * const mrfld_pwm2_groups[] = { "pwm2_grp" }; 375 static const char * const mrfld_pwm3_groups[] = { "pwm3_grp" }; 376 377 static const struct intel_function mrfld_functions[] = { 378 FUNCTION("sdio", mrfld_sdio_groups), 379 FUNCTION("i2s2", mrfld_i2s2_groups), 380 FUNCTION("spi5", mrfld_spi5_groups), 381 FUNCTION("uart0", mrfld_uart0_groups), 382 FUNCTION("uart1", mrfld_uart1_groups), 383 FUNCTION("uart2", mrfld_uart2_groups), 384 FUNCTION("pwm0", mrfld_pwm0_groups), 385 FUNCTION("pwm1", mrfld_pwm1_groups), 386 FUNCTION("pwm2", mrfld_pwm2_groups), 387 FUNCTION("pwm3", mrfld_pwm3_groups), 388 }; 389 390 static const struct mrfld_family mrfld_families[] = { 391 MRFLD_FAMILY(1, 0, 12), 392 MRFLD_FAMILY(2, 13, 36), 393 MRFLD_FAMILY(3, 37, 56), 394 MRFLD_FAMILY(4, 57, 64), 395 MRFLD_FAMILY(5, 65, 78), 396 MRFLD_FAMILY(6, 79, 100), 397 MRFLD_FAMILY_PROTECTED(7, 101, 114), 398 MRFLD_FAMILY(8, 115, 126), 399 MRFLD_FAMILY(9, 127, 145), 400 MRFLD_FAMILY(10, 146, 157), 401 MRFLD_FAMILY(11, 158, 179), 402 MRFLD_FAMILY_PROTECTED(12, 180, 194), 403 MRFLD_FAMILY(13, 195, 214), 404 MRFLD_FAMILY(14, 215, 227), 405 MRFLD_FAMILY(15, 228, 232), 406 }; 407 408 /** 409 * struct mrfld_pinctrl - Intel Merrifield pinctrl private structure 410 * @dev: Pointer to the device structure 411 * @lock: Lock to serialize register access 412 * @pctldesc: Pin controller description 413 * @pctldev: Pointer to the pin controller device 414 * @families: Array of families this pinctrl handles 415 * @nfamilies: Number of families in the array 416 * @functions: Array of functions 417 * @nfunctions: Number of functions in the array 418 * @groups: Array of pin groups 419 * @ngroups: Number of groups in the array 420 * @pins: Array of pins this pinctrl controls 421 * @npins: Number of pins in the array 422 */ 423 struct mrfld_pinctrl { 424 struct device *dev; 425 raw_spinlock_t lock; 426 struct pinctrl_desc pctldesc; 427 struct pinctrl_dev *pctldev; 428 429 /* Pin controller configuration */ 430 const struct mrfld_family *families; 431 size_t nfamilies; 432 const struct intel_function *functions; 433 size_t nfunctions; 434 const struct intel_pingroup *groups; 435 size_t ngroups; 436 const struct pinctrl_pin_desc *pins; 437 size_t npins; 438 }; 439 440 #define pin_to_bufno(f, p) ((p) - (f)->pin_base) 441 442 static const struct mrfld_family *mrfld_get_family(struct mrfld_pinctrl *mp, 443 unsigned int pin) 444 { 445 const struct mrfld_family *family; 446 unsigned int i; 447 448 for (i = 0; i < mp->nfamilies; i++) { 449 family = &mp->families[i]; 450 if (pin >= family->pin_base && 451 pin < family->pin_base + family->npins) 452 return family; 453 } 454 455 dev_warn(mp->dev, "failed to find family for pin %u\n", pin); 456 return NULL; 457 } 458 459 static bool mrfld_buf_available(struct mrfld_pinctrl *mp, unsigned int pin) 460 { 461 const struct mrfld_family *family; 462 463 family = mrfld_get_family(mp, pin); 464 if (!family) 465 return false; 466 467 return !family->protected; 468 } 469 470 static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin) 471 { 472 const struct mrfld_family *family; 473 unsigned int bufno; 474 475 family = mrfld_get_family(mp, pin); 476 if (!family) 477 return NULL; 478 479 bufno = pin_to_bufno(family, pin); 480 return family->regs + BUFCFG_OFFSET + bufno * 4; 481 } 482 483 static int mrfld_read_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, u32 *value) 484 { 485 void __iomem *bufcfg; 486 487 if (!mrfld_buf_available(mp, pin)) 488 return -EBUSY; 489 490 bufcfg = mrfld_get_bufcfg(mp, pin); 491 *value = readl(bufcfg); 492 493 return 0; 494 } 495 496 static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, 497 u32 bits, u32 mask) 498 { 499 void __iomem *bufcfg; 500 u32 value; 501 502 bufcfg = mrfld_get_bufcfg(mp, pin); 503 value = readl(bufcfg); 504 505 value &= ~mask; 506 value |= bits & mask; 507 508 writel(value, bufcfg); 509 } 510 511 static int mrfld_get_groups_count(struct pinctrl_dev *pctldev) 512 { 513 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 514 515 return mp->ngroups; 516 } 517 518 static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev, 519 unsigned int group) 520 { 521 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 522 523 return mp->groups[group].name; 524 } 525 526 static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 527 const unsigned int **pins, unsigned int *npins) 528 { 529 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 530 531 *pins = mp->groups[group].pins; 532 *npins = mp->groups[group].npins; 533 return 0; 534 } 535 536 static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 537 unsigned int pin) 538 { 539 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 540 u32 value, mode; 541 int ret; 542 543 ret = mrfld_read_bufcfg(mp, pin, &value); 544 if (ret) { 545 seq_puts(s, "not available"); 546 return; 547 } 548 549 mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT; 550 if (!mode) 551 seq_puts(s, "GPIO "); 552 else 553 seq_printf(s, "mode %d ", mode); 554 555 seq_printf(s, "0x%08x", value); 556 } 557 558 static const struct pinctrl_ops mrfld_pinctrl_ops = { 559 .get_groups_count = mrfld_get_groups_count, 560 .get_group_name = mrfld_get_group_name, 561 .get_group_pins = mrfld_get_group_pins, 562 .pin_dbg_show = mrfld_pin_dbg_show, 563 }; 564 565 static int mrfld_get_functions_count(struct pinctrl_dev *pctldev) 566 { 567 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 568 569 return mp->nfunctions; 570 } 571 572 static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev, 573 unsigned int function) 574 { 575 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 576 577 return mp->functions[function].name; 578 } 579 580 static int mrfld_get_function_groups(struct pinctrl_dev *pctldev, 581 unsigned int function, 582 const char * const **groups, 583 unsigned int * const ngroups) 584 { 585 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 586 587 *groups = mp->functions[function].groups; 588 *ngroups = mp->functions[function].ngroups; 589 return 0; 590 } 591 592 static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev, 593 unsigned int function, 594 unsigned int group) 595 { 596 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 597 const struct intel_pingroup *grp = &mp->groups[group]; 598 u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT; 599 u32 mask = BUFCFG_PINMODE_MASK; 600 unsigned long flags; 601 unsigned int i; 602 603 /* 604 * All pins in the groups needs to be accessible and writable 605 * before we can enable the mux for this group. 606 */ 607 for (i = 0; i < grp->npins; i++) { 608 if (!mrfld_buf_available(mp, grp->pins[i])) 609 return -EBUSY; 610 } 611 612 /* Now enable the mux setting for each pin in the group */ 613 raw_spin_lock_irqsave(&mp->lock, flags); 614 for (i = 0; i < grp->npins; i++) 615 mrfld_update_bufcfg(mp, grp->pins[i], bits, mask); 616 raw_spin_unlock_irqrestore(&mp->lock, flags); 617 618 return 0; 619 } 620 621 static int mrfld_gpio_request_enable(struct pinctrl_dev *pctldev, 622 struct pinctrl_gpio_range *range, 623 unsigned int pin) 624 { 625 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 626 u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT; 627 u32 mask = BUFCFG_PINMODE_MASK; 628 unsigned long flags; 629 630 if (!mrfld_buf_available(mp, pin)) 631 return -EBUSY; 632 633 raw_spin_lock_irqsave(&mp->lock, flags); 634 mrfld_update_bufcfg(mp, pin, bits, mask); 635 raw_spin_unlock_irqrestore(&mp->lock, flags); 636 637 return 0; 638 } 639 640 static const struct pinmux_ops mrfld_pinmux_ops = { 641 .get_functions_count = mrfld_get_functions_count, 642 .get_function_name = mrfld_get_function_name, 643 .get_function_groups = mrfld_get_function_groups, 644 .set_mux = mrfld_pinmux_set_mux, 645 .gpio_request_enable = mrfld_gpio_request_enable, 646 }; 647 648 static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 649 unsigned long *config) 650 { 651 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 652 enum pin_config_param param = pinconf_to_config_param(*config); 653 u32 value, term; 654 u16 arg = 0; 655 int ret; 656 657 ret = mrfld_read_bufcfg(mp, pin, &value); 658 if (ret) 659 return -ENOTSUPP; 660 661 term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT; 662 663 switch (param) { 664 case PIN_CONFIG_BIAS_DISABLE: 665 if (value & BUFCFG_Px_EN_MASK) 666 return -EINVAL; 667 break; 668 669 case PIN_CONFIG_BIAS_PULL_UP: 670 if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN) 671 return -EINVAL; 672 673 switch (term) { 674 case BUFCFG_PUPD_VAL_910: 675 arg = 910; 676 break; 677 case BUFCFG_PUPD_VAL_2K: 678 arg = 2000; 679 break; 680 case BUFCFG_PUPD_VAL_20K: 681 arg = 20000; 682 break; 683 case BUFCFG_PUPD_VAL_50K: 684 arg = 50000; 685 break; 686 } 687 688 break; 689 690 case PIN_CONFIG_BIAS_PULL_DOWN: 691 if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN) 692 return -EINVAL; 693 694 switch (term) { 695 case BUFCFG_PUPD_VAL_910: 696 arg = 910; 697 break; 698 case BUFCFG_PUPD_VAL_2K: 699 arg = 2000; 700 break; 701 case BUFCFG_PUPD_VAL_20K: 702 arg = 20000; 703 break; 704 case BUFCFG_PUPD_VAL_50K: 705 arg = 50000; 706 break; 707 } 708 709 break; 710 711 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 712 if (!(value & BUFCFG_OD_EN)) 713 return -EINVAL; 714 break; 715 716 case PIN_CONFIG_SLEW_RATE: 717 if (!(value & BUFCFG_SLEWSEL)) 718 arg = 0; 719 else 720 arg = 1; 721 break; 722 723 default: 724 return -ENOTSUPP; 725 } 726 727 *config = pinconf_to_config_packed(param, arg); 728 return 0; 729 } 730 731 static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin, 732 unsigned long config) 733 { 734 unsigned int param = pinconf_to_config_param(config); 735 unsigned int arg = pinconf_to_config_argument(config); 736 u32 bits = 0, mask = 0; 737 unsigned long flags; 738 739 switch (param) { 740 case PIN_CONFIG_BIAS_DISABLE: 741 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; 742 break; 743 744 case PIN_CONFIG_BIAS_PULL_UP: 745 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; 746 bits |= BUFCFG_PU_EN; 747 748 /* Set default strength value in case none is given */ 749 if (arg == 1) 750 arg = 20000; 751 752 switch (arg) { 753 case 50000: 754 bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; 755 break; 756 case 20000: 757 bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; 758 break; 759 case 2000: 760 bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; 761 break; 762 default: 763 return -EINVAL; 764 } 765 766 break; 767 768 case PIN_CONFIG_BIAS_PULL_DOWN: 769 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; 770 bits |= BUFCFG_PD_EN; 771 772 /* Set default strength value in case none is given */ 773 if (arg == 1) 774 arg = 20000; 775 776 switch (arg) { 777 case 50000: 778 bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; 779 break; 780 case 20000: 781 bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; 782 break; 783 case 2000: 784 bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; 785 break; 786 default: 787 return -EINVAL; 788 } 789 790 break; 791 792 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 793 mask |= BUFCFG_OD_EN; 794 if (arg) 795 bits |= BUFCFG_OD_EN; 796 break; 797 798 case PIN_CONFIG_SLEW_RATE: 799 mask |= BUFCFG_SLEWSEL; 800 if (arg) 801 bits |= BUFCFG_SLEWSEL; 802 break; 803 } 804 805 raw_spin_lock_irqsave(&mp->lock, flags); 806 mrfld_update_bufcfg(mp, pin, bits, mask); 807 raw_spin_unlock_irqrestore(&mp->lock, flags); 808 809 return 0; 810 } 811 812 static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 813 unsigned long *configs, unsigned int nconfigs) 814 { 815 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 816 unsigned int i; 817 int ret; 818 819 if (!mrfld_buf_available(mp, pin)) 820 return -ENOTSUPP; 821 822 for (i = 0; i < nconfigs; i++) { 823 switch (pinconf_to_config_param(configs[i])) { 824 case PIN_CONFIG_BIAS_DISABLE: 825 case PIN_CONFIG_BIAS_PULL_UP: 826 case PIN_CONFIG_BIAS_PULL_DOWN: 827 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 828 case PIN_CONFIG_SLEW_RATE: 829 ret = mrfld_config_set_pin(mp, pin, configs[i]); 830 if (ret) 831 return ret; 832 break; 833 834 default: 835 return -ENOTSUPP; 836 } 837 } 838 839 return 0; 840 } 841 842 static int mrfld_config_group_get(struct pinctrl_dev *pctldev, 843 unsigned int group, unsigned long *config) 844 { 845 const unsigned int *pins; 846 unsigned int npins; 847 int ret; 848 849 ret = mrfld_get_group_pins(pctldev, group, &pins, &npins); 850 if (ret) 851 return ret; 852 853 ret = mrfld_config_get(pctldev, pins[0], config); 854 if (ret) 855 return ret; 856 857 return 0; 858 } 859 860 static int mrfld_config_group_set(struct pinctrl_dev *pctldev, 861 unsigned int group, unsigned long *configs, 862 unsigned int num_configs) 863 { 864 const unsigned int *pins; 865 unsigned int npins; 866 int i, ret; 867 868 ret = mrfld_get_group_pins(pctldev, group, &pins, &npins); 869 if (ret) 870 return ret; 871 872 for (i = 0; i < npins; i++) { 873 ret = mrfld_config_set(pctldev, pins[i], configs, num_configs); 874 if (ret) 875 return ret; 876 } 877 878 return 0; 879 } 880 881 static const struct pinconf_ops mrfld_pinconf_ops = { 882 .is_generic = true, 883 .pin_config_get = mrfld_config_get, 884 .pin_config_set = mrfld_config_set, 885 .pin_config_group_get = mrfld_config_group_get, 886 .pin_config_group_set = mrfld_config_group_set, 887 }; 888 889 static const struct pinctrl_desc mrfld_pinctrl_desc = { 890 .pctlops = &mrfld_pinctrl_ops, 891 .pmxops = &mrfld_pinmux_ops, 892 .confops = &mrfld_pinconf_ops, 893 .owner = THIS_MODULE, 894 }; 895 896 static int mrfld_pinctrl_probe(struct platform_device *pdev) 897 { 898 struct mrfld_family *families; 899 struct mrfld_pinctrl *mp; 900 void __iomem *regs; 901 size_t nfamilies; 902 unsigned int i; 903 904 mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL); 905 if (!mp) 906 return -ENOMEM; 907 908 mp->dev = &pdev->dev; 909 raw_spin_lock_init(&mp->lock); 910 911 regs = devm_platform_ioremap_resource(pdev, 0); 912 if (IS_ERR(regs)) 913 return PTR_ERR(regs); 914 915 /* 916 * Make a copy of the families which we can use to hold pointers 917 * to the registers. 918 */ 919 nfamilies = ARRAY_SIZE(mrfld_families), 920 families = devm_kmemdup(&pdev->dev, mrfld_families, 921 sizeof(mrfld_families), 922 GFP_KERNEL); 923 if (!families) 924 return -ENOMEM; 925 926 /* Splice memory resource by chunk per family */ 927 for (i = 0; i < nfamilies; i++) { 928 struct mrfld_family *family = &families[i]; 929 930 family->regs = regs + family->barno * MRFLD_FAMILY_LEN; 931 } 932 933 mp->families = families; 934 mp->nfamilies = nfamilies; 935 mp->functions = mrfld_functions; 936 mp->nfunctions = ARRAY_SIZE(mrfld_functions); 937 mp->groups = mrfld_groups; 938 mp->ngroups = ARRAY_SIZE(mrfld_groups); 939 mp->pctldesc = mrfld_pinctrl_desc; 940 mp->pctldesc.name = dev_name(&pdev->dev); 941 mp->pctldesc.pins = mrfld_pins; 942 mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins); 943 944 mp->pctldev = devm_pinctrl_register(&pdev->dev, &mp->pctldesc, mp); 945 if (IS_ERR(mp->pctldev)) { 946 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 947 return PTR_ERR(mp->pctldev); 948 } 949 950 platform_set_drvdata(pdev, mp); 951 return 0; 952 } 953 954 static const struct acpi_device_id mrfld_acpi_table[] = { 955 { "INTC1002" }, 956 { } 957 }; 958 MODULE_DEVICE_TABLE(acpi, mrfld_acpi_table); 959 960 static struct platform_driver mrfld_pinctrl_driver = { 961 .probe = mrfld_pinctrl_probe, 962 .driver = { 963 .name = "pinctrl-merrifield", 964 .acpi_match_table = mrfld_acpi_table, 965 }, 966 }; 967 968 static int __init mrfld_pinctrl_init(void) 969 { 970 return platform_driver_register(&mrfld_pinctrl_driver); 971 } 972 subsys_initcall(mrfld_pinctrl_init); 973 974 static void __exit mrfld_pinctrl_exit(void) 975 { 976 platform_driver_unregister(&mrfld_pinctrl_driver); 977 } 978 module_exit(mrfld_pinctrl_exit); 979 980 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 981 MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver"); 982 MODULE_LICENSE("GPL v2"); 983 MODULE_ALIAS("platform:pinctrl-merrifield"); 984