1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Lynxpoint PCH pinctrl/GPIO driver 4 * 5 * Copyright (C) 2012-2019 Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/array_size.h> 12 #include <linux/bitops.h> 13 #include <linux/cleanup.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/seq_file.h> 21 #include <linux/slab.h> 22 #include <linux/types.h> 23 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 #include <linux/pinctrl/pinconf.h> 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinmux.h> 29 30 #include "pinctrl-intel.h" 31 32 #define LPTLP_COMMUNITY(p, n, g) \ 33 { \ 34 .pin_base = (p), \ 35 .npins = (n), \ 36 .gpps = (g), \ 37 .ngpps = ARRAY_SIZE(g), \ 38 } 39 40 static const struct pinctrl_pin_desc lptlp_pins[] = { 41 PINCTRL_PIN(0, "GP0_UART1_RXD"), 42 PINCTRL_PIN(1, "GP1_UART1_TXD"), 43 PINCTRL_PIN(2, "GP2_UART1_RTSB"), 44 PINCTRL_PIN(3, "GP3_UART1_CTSB"), 45 PINCTRL_PIN(4, "GP4_I2C0_SDA"), 46 PINCTRL_PIN(5, "GP5_I2C0_SCL"), 47 PINCTRL_PIN(6, "GP6_I2C1_SDA"), 48 PINCTRL_PIN(7, "GP7_I2C1_SCL"), 49 PINCTRL_PIN(8, "GP8"), 50 PINCTRL_PIN(9, "GP9"), 51 PINCTRL_PIN(10, "GP10"), 52 PINCTRL_PIN(11, "GP11_SMBALERTB"), 53 PINCTRL_PIN(12, "GP12_LANPHYPC"), 54 PINCTRL_PIN(13, "GP13"), 55 PINCTRL_PIN(14, "GP14"), 56 PINCTRL_PIN(15, "GP15"), 57 PINCTRL_PIN(16, "GP16_MGPIO9"), 58 PINCTRL_PIN(17, "GP17_MGPIO10"), 59 PINCTRL_PIN(18, "GP18_SRC0CLKRQB"), 60 PINCTRL_PIN(19, "GP19_SRC1CLKRQB"), 61 PINCTRL_PIN(20, "GP20_SRC2CLKRQB"), 62 PINCTRL_PIN(21, "GP21_SRC3CLKRQB"), 63 PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"), 64 PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"), 65 PINCTRL_PIN(24, "GP24_MGPIO0"), 66 PINCTRL_PIN(25, "GP25_USBWAKEOUTB"), 67 PINCTRL_PIN(26, "GP26_MGPIO5"), 68 PINCTRL_PIN(27, "GP27_MGPIO6"), 69 PINCTRL_PIN(28, "GP28_MGPIO7"), 70 PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"), 71 PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"), 72 PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"), 73 PINCTRL_PIN(32, "GP32_CLKRUNB"), 74 PINCTRL_PIN(33, "GP33_DEVSLP0"), 75 PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"), 76 PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"), 77 PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"), 78 PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"), 79 PINCTRL_PIN(38, "GP38_DEVSLP1"), 80 PINCTRL_PIN(39, "GP39_DEVSLP2"), 81 PINCTRL_PIN(40, "GP40_OC0B"), 82 PINCTRL_PIN(41, "GP41_OC1B"), 83 PINCTRL_PIN(42, "GP42_OC2B"), 84 PINCTRL_PIN(43, "GP43_OC3B"), 85 PINCTRL_PIN(44, "GP44"), 86 PINCTRL_PIN(45, "GP45_TMS2"), 87 PINCTRL_PIN(46, "GP46_TDO2"), 88 PINCTRL_PIN(47, "GP47"), 89 PINCTRL_PIN(48, "GP48"), 90 PINCTRL_PIN(49, "GP49"), 91 PINCTRL_PIN(50, "GP50"), 92 PINCTRL_PIN(51, "GP51_GSXDOUT"), 93 PINCTRL_PIN(52, "GP52_GSXSLOAD"), 94 PINCTRL_PIN(53, "GP53_GSXDIN"), 95 PINCTRL_PIN(54, "GP54_GSXSRESETB"), 96 PINCTRL_PIN(55, "GP55_GSXCLK"), 97 PINCTRL_PIN(56, "GP56"), 98 PINCTRL_PIN(57, "GP57"), 99 PINCTRL_PIN(58, "GP58"), 100 PINCTRL_PIN(59, "GP59"), 101 PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"), 102 PINCTRL_PIN(61, "GP61_SUS_STATB"), 103 PINCTRL_PIN(62, "GP62_SUSCLK"), 104 PINCTRL_PIN(63, "GP63_SLP_S5B"), 105 PINCTRL_PIN(64, "GP64_SDIO_CLK"), 106 PINCTRL_PIN(65, "GP65_SDIO_CMD"), 107 PINCTRL_PIN(66, "GP66_SDIO_D0"), 108 PINCTRL_PIN(67, "GP67_SDIO_D1"), 109 PINCTRL_PIN(68, "GP68_SDIO_D2"), 110 PINCTRL_PIN(69, "GP69_SDIO_D3"), 111 PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"), 112 PINCTRL_PIN(71, "GP71_MPHYPC"), 113 PINCTRL_PIN(72, "GP72_BATLOWB"), 114 PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"), 115 PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"), 116 PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"), 117 PINCTRL_PIN(76, "GP76_BMBUSYB"), 118 PINCTRL_PIN(77, "GP77_PIRQAB"), 119 PINCTRL_PIN(78, "GP78_PIRQBB"), 120 PINCTRL_PIN(79, "GP79_PIRQCB"), 121 PINCTRL_PIN(80, "GP80_PIRQDB"), 122 PINCTRL_PIN(81, "GP81_SPKR"), 123 PINCTRL_PIN(82, "GP82_RCINB"), 124 PINCTRL_PIN(83, "GP83_GSPI0_CSB"), 125 PINCTRL_PIN(84, "GP84_GSPI0_CLK"), 126 PINCTRL_PIN(85, "GP85_GSPI0_MISO"), 127 PINCTRL_PIN(86, "GP86_GSPI0_MOSI"), 128 PINCTRL_PIN(87, "GP87_GSPI1_CSB"), 129 PINCTRL_PIN(88, "GP88_GSPI1_CLK"), 130 PINCTRL_PIN(89, "GP89_GSPI1_MISO"), 131 PINCTRL_PIN(90, "GP90_GSPI1_MOSI"), 132 PINCTRL_PIN(91, "GP91_UART0_RXD"), 133 PINCTRL_PIN(92, "GP92_UART0_TXD"), 134 PINCTRL_PIN(93, "GP93_UART0_RTSB"), 135 PINCTRL_PIN(94, "GP94_UART0_CTSB"), 136 }; 137 138 static const struct intel_padgroup lptlp_gpps[] = { 139 INTEL_GPP(0, 0, 31, 0), 140 INTEL_GPP(1, 32, 63, 32), 141 INTEL_GPP(2, 64, 94, 64), 142 }; 143 144 static const struct intel_community lptlp_communities[] = { 145 LPTLP_COMMUNITY(0, 95, lptlp_gpps), 146 }; 147 148 static const struct intel_pinctrl_soc_data lptlp_soc_data = { 149 .pins = lptlp_pins, 150 .npins = ARRAY_SIZE(lptlp_pins), 151 .communities = lptlp_communities, 152 .ncommunities = ARRAY_SIZE(lptlp_communities), 153 }; 154 155 /* LynxPoint chipset has support for 95 GPIO pins */ 156 157 #define LP_NUM_GPIO 95 158 159 /* Bitmapped register offsets */ 160 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ 161 #define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */ 162 #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */ 163 #define LP_INT_STAT 0x80 164 #define LP_INT_ENABLE 0x90 165 166 /* Each pin has two 32 bit config registers, starting at 0x100 */ 167 #define LP_CONFIG1 0x100 168 #define LP_CONFIG2 0x104 169 170 /* LP_CONFIG1 reg bits */ 171 #define OUT_LVL_BIT BIT(31) 172 #define IN_LVL_BIT BIT(30) 173 #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */ 174 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */ 175 #define DIR_BIT BIT(2) /* 0: Output, 1: Input */ 176 #define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */ 177 #define USE_SEL_NATIVE (0 << 0) 178 #define USE_SEL_GPIO (1 << 0) 179 180 /* LP_CONFIG2 reg bits */ 181 #define GPINDIS_BIT BIT(2) /* disable input sensing */ 182 #define GPIWP_MASK GENMASK(1, 0) /* weak pull options */ 183 #define GPIWP_NONE 0 /* none */ 184 #define GPIWP_DOWN 1 /* weak pull down */ 185 #define GPIWP_UP 2 /* weak pull up */ 186 187 /* 188 * Lynxpoint gpios are controlled through both bitmapped registers and 189 * per gpio specific registers. The bitmapped registers are in chunks of 190 * 3 x 32bit registers to cover all 95 GPIOs 191 * 192 * per gpio specific registers consist of two 32bit registers per gpio 193 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of 194 * 190 config registers. 195 * 196 * A simplified view of the register layout look like this: 197 * 198 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers) 199 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63 200 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 201 * ... 202 * LP_INT_ENABLE[31:0] ... 203 * LP_INT_ENABLE[63:32] ... 204 * LP_INT_ENABLE[94:64] ... 205 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) 206 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 207 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1 208 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1 209 * LP2_CONFIG1 (gpio 2) ... 210 * LP2_CONFIG2 (gpio 2) ... 211 * ... 212 * LP94_CONFIG1 (gpio 94) ... 213 * LP94_CONFIG2 (gpio 94) ... 214 * 215 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55. 216 */ 217 218 static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, 219 int reg) 220 { 221 struct intel_pinctrl *lg = gpiochip_get_data(chip); 222 const struct intel_community *comm; 223 int reg_offset; 224 225 comm = intel_get_community(lg, offset); 226 if (!comm) 227 return NULL; 228 229 offset -= comm->pin_base; 230 231 if (reg == LP_CONFIG1 || reg == LP_CONFIG2) 232 /* per gpio specific config registers */ 233 reg_offset = offset * 8; 234 else 235 /* bitmapped registers */ 236 reg_offset = (offset / 32) * 4; 237 238 return comm->regs + reg_offset + reg; 239 } 240 241 static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin) 242 { 243 void __iomem *acpi_use; 244 245 acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED); 246 if (!acpi_use) 247 return true; 248 249 return !(ioread32(acpi_use) & BIT(pin % 32)); 250 } 251 252 static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset) 253 { 254 void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC); 255 u32 value; 256 257 value = ioread32(ioxapic_use); 258 259 if (offset >= 8 && offset <= 10) 260 return !!(value & BIT(offset - 8 + 0)); 261 if (offset >= 13 && offset <= 14) 262 return !!(value & BIT(offset - 13 + 3)); 263 if (offset >= 45 && offset <= 55) 264 return !!(value & BIT(offset - 45 + 5)); 265 266 return false; 267 } 268 269 static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 270 unsigned int pin) 271 { 272 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 273 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 274 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 275 u32 value, mode; 276 277 value = ioread32(reg); 278 279 mode = value & USE_SEL_MASK; 280 if (mode == USE_SEL_GPIO) 281 seq_puts(s, "GPIO "); 282 else 283 seq_printf(s, "mode %d ", mode); 284 285 seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2)); 286 287 if (lp_gpio_acpi_use(lg, pin)) 288 seq_puts(s, " [ACPI]"); 289 } 290 291 static const struct pinctrl_ops lptlp_pinctrl_ops = { 292 .get_groups_count = intel_get_groups_count, 293 .get_group_name = intel_get_group_name, 294 .get_group_pins = intel_get_group_pins, 295 .pin_dbg_show = lp_pin_dbg_show, 296 }; 297 298 static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev, 299 unsigned int function, unsigned int group) 300 { 301 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 302 const struct intel_pingroup *grp = &lg->soc->groups[group]; 303 int i; 304 305 guard(raw_spinlock_irqsave)(&lg->lock); 306 307 /* Now enable the mux setting for each pin in the group */ 308 for (i = 0; i < grp->grp.npins; i++) { 309 void __iomem *reg = lp_gpio_reg(&lg->chip, grp->grp.pins[i], LP_CONFIG1); 310 u32 value; 311 312 value = ioread32(reg); 313 314 value &= ~USE_SEL_MASK; 315 if (grp->modes) 316 value |= grp->modes[i]; 317 else 318 value |= grp->mode; 319 320 iowrite32(value, reg); 321 } 322 323 return 0; 324 } 325 326 static void lp_gpio_enable_input(void __iomem *reg) 327 { 328 iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg); 329 } 330 331 static void lp_gpio_disable_input(void __iomem *reg) 332 { 333 iowrite32(ioread32(reg) | GPINDIS_BIT, reg); 334 } 335 336 static int lp_gpio_request_enable(struct pinctrl_dev *pctldev, 337 struct pinctrl_gpio_range *range, 338 unsigned int pin) 339 { 340 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 341 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 342 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 343 u32 value; 344 345 guard(raw_spinlock_irqsave)(&lg->lock); 346 347 /* 348 * Reconfigure pin to GPIO mode if needed and issue a warning, 349 * since we expect firmware to configure it properly. 350 */ 351 value = ioread32(reg); 352 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { 353 iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); 354 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin); 355 } 356 357 /* Enable input sensing */ 358 lp_gpio_enable_input(conf2); 359 360 return 0; 361 } 362 363 static void lp_gpio_disable_free(struct pinctrl_dev *pctldev, 364 struct pinctrl_gpio_range *range, 365 unsigned int pin) 366 { 367 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 368 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 369 370 guard(raw_spinlock_irqsave)(&lg->lock); 371 372 /* Disable input sensing */ 373 lp_gpio_disable_input(conf2); 374 } 375 376 static int lp_gpio_set_direction(struct pinctrl_dev *pctldev, 377 struct pinctrl_gpio_range *range, 378 unsigned int pin, bool input) 379 { 380 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 381 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 382 u32 value; 383 384 guard(raw_spinlock_irqsave)(&lg->lock); 385 386 value = ioread32(reg); 387 value &= ~DIR_BIT; 388 if (input) { 389 value |= DIR_BIT; 390 } else { 391 /* 392 * Before making any direction modifications, do a check if GPIO 393 * is set for direct IRQ. On Lynxpoint, setting GPIO to output 394 * does not make sense, so let's at least warn the caller before 395 * they shoot themselves in the foot. 396 */ 397 WARN(lp_gpio_ioxapic_use(&lg->chip, pin), 398 "Potential Error: Setting GPIO to output with IOxAPIC redirection"); 399 } 400 iowrite32(value, reg); 401 402 return 0; 403 } 404 405 static const struct pinmux_ops lptlp_pinmux_ops = { 406 .get_functions_count = intel_get_functions_count, 407 .get_function_name = intel_get_function_name, 408 .get_function_groups = intel_get_function_groups, 409 .set_mux = lp_pinmux_set_mux, 410 .gpio_request_enable = lp_gpio_request_enable, 411 .gpio_disable_free = lp_gpio_disable_free, 412 .gpio_set_direction = lp_gpio_set_direction, 413 }; 414 415 static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 416 unsigned long *config) 417 { 418 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 419 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 420 enum pin_config_param param = pinconf_to_config_param(*config); 421 u32 value, pull; 422 u16 arg; 423 424 scoped_guard(raw_spinlock_irqsave, &lg->lock) 425 value = ioread32(conf2); 426 427 pull = value & GPIWP_MASK; 428 429 switch (param) { 430 case PIN_CONFIG_BIAS_DISABLE: 431 if (pull != GPIWP_NONE) 432 return -EINVAL; 433 arg = 0; 434 break; 435 case PIN_CONFIG_BIAS_PULL_DOWN: 436 if (pull != GPIWP_DOWN) 437 return -EINVAL; 438 439 arg = 1; 440 break; 441 case PIN_CONFIG_BIAS_PULL_UP: 442 if (pull != GPIWP_UP) 443 return -EINVAL; 444 445 arg = 1; 446 break; 447 default: 448 return -ENOTSUPP; 449 } 450 451 *config = pinconf_to_config_packed(param, arg); 452 453 return 0; 454 } 455 456 static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 457 unsigned long *configs, unsigned int num_configs) 458 { 459 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 460 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 461 enum pin_config_param param; 462 unsigned int i; 463 u32 value; 464 465 guard(raw_spinlock_irqsave)(&lg->lock); 466 467 value = ioread32(conf2); 468 469 for (i = 0; i < num_configs; i++) { 470 param = pinconf_to_config_param(configs[i]); 471 472 switch (param) { 473 case PIN_CONFIG_BIAS_DISABLE: 474 value &= ~GPIWP_MASK; 475 value |= GPIWP_NONE; 476 break; 477 case PIN_CONFIG_BIAS_PULL_DOWN: 478 value &= ~GPIWP_MASK; 479 value |= GPIWP_DOWN; 480 break; 481 case PIN_CONFIG_BIAS_PULL_UP: 482 value &= ~GPIWP_MASK; 483 value |= GPIWP_UP; 484 break; 485 default: 486 return -ENOTSUPP; 487 } 488 } 489 490 iowrite32(value, conf2); 491 492 return 0; 493 } 494 495 static const struct pinconf_ops lptlp_pinconf_ops = { 496 .is_generic = true, 497 .pin_config_get = lp_pin_config_get, 498 .pin_config_set = lp_pin_config_set, 499 }; 500 501 static const struct pinctrl_desc lptlp_pinctrl_desc = { 502 .pctlops = &lptlp_pinctrl_ops, 503 .pmxops = &lptlp_pinmux_ops, 504 .confops = &lptlp_pinconf_ops, 505 .owner = THIS_MODULE, 506 }; 507 508 static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) 509 { 510 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 511 return !!(ioread32(reg) & IN_LVL_BIT); 512 } 513 514 static int lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 515 { 516 struct intel_pinctrl *lg = gpiochip_get_data(chip); 517 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 518 519 guard(raw_spinlock_irqsave)(&lg->lock); 520 521 if (value) 522 iowrite32(ioread32(reg) | OUT_LVL_BIT, reg); 523 else 524 iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg); 525 526 return 0; 527 } 528 529 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 530 { 531 return pinctrl_gpio_direction_input(chip, offset); 532 } 533 534 static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 535 int value) 536 { 537 lp_gpio_set(chip, offset, value); 538 539 return pinctrl_gpio_direction_output(chip, offset); 540 } 541 542 static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 543 { 544 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 545 546 if (ioread32(reg) & DIR_BIT) 547 return GPIO_LINE_DIRECTION_IN; 548 549 return GPIO_LINE_DIRECTION_OUT; 550 } 551 552 static void lp_gpio_irq_handler(struct irq_desc *desc) 553 { 554 struct irq_data *data = irq_desc_get_irq_data(desc); 555 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 556 struct intel_pinctrl *lg = gpiochip_get_data(gc); 557 struct irq_chip *chip = irq_data_get_irq_chip(data); 558 void __iomem *reg, *ena; 559 unsigned long pending; 560 u32 base, pin; 561 562 chained_irq_enter(chip, desc); 563 564 /* check from GPIO controller which pin triggered the interrupt */ 565 for (base = 0; base < lg->chip.ngpio; base += 32) { 566 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 567 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 568 569 /* Only interrupts that are enabled */ 570 pending = ioread32(reg) & ioread32(ena); 571 572 for_each_set_bit(pin, &pending, 32) 573 generic_handle_domain_irq(lg->chip.irq.domain, base + pin); 574 } 575 576 chained_irq_exit(chip, desc); 577 } 578 579 static void lp_irq_ack(struct irq_data *d) 580 { 581 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 582 struct intel_pinctrl *lg = gpiochip_get_data(gc); 583 irq_hw_number_t hwirq = irqd_to_hwirq(d); 584 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); 585 586 guard(raw_spinlock_irqsave)(&lg->lock); 587 588 iowrite32(BIT(hwirq % 32), reg); 589 } 590 591 static void lp_irq_unmask(struct irq_data *d) 592 { 593 } 594 595 static void lp_irq_mask(struct irq_data *d) 596 { 597 } 598 599 static void lp_irq_enable(struct irq_data *d) 600 { 601 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 602 struct intel_pinctrl *lg = gpiochip_get_data(gc); 603 irq_hw_number_t hwirq = irqd_to_hwirq(d); 604 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 605 606 gpiochip_enable_irq(gc, hwirq); 607 608 scoped_guard(raw_spinlock_irqsave, &lg->lock) 609 iowrite32(ioread32(reg) | BIT(hwirq % 32), reg); 610 } 611 612 static void lp_irq_disable(struct irq_data *d) 613 { 614 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 615 struct intel_pinctrl *lg = gpiochip_get_data(gc); 616 irq_hw_number_t hwirq = irqd_to_hwirq(d); 617 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 618 619 scoped_guard(raw_spinlock_irqsave, &lg->lock) 620 iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg); 621 622 gpiochip_disable_irq(gc, hwirq); 623 } 624 625 static int lp_irq_set_type(struct irq_data *d, unsigned int type) 626 { 627 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 628 struct intel_pinctrl *lg = gpiochip_get_data(gc); 629 irq_hw_number_t hwirq = irqd_to_hwirq(d); 630 void __iomem *reg; 631 u32 value; 632 633 reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); 634 if (!reg) 635 return -EINVAL; 636 637 /* Fail if BIOS reserved pin for ACPI use */ 638 if (lp_gpio_acpi_use(lg, hwirq)) { 639 dev_err(lg->dev, "pin %lu can't be used as IRQ\n", hwirq); 640 return -EBUSY; 641 } 642 643 guard(raw_spinlock_irqsave)(&lg->lock); 644 645 value = ioread32(reg); 646 647 /* set both TRIG_SEL and INV bits to 0 for rising edge */ 648 if (type & IRQ_TYPE_EDGE_RISING) 649 value &= ~(TRIG_SEL_BIT | INT_INV_BIT); 650 651 /* TRIG_SEL bit 0, INV bit 1 for falling edge */ 652 if (type & IRQ_TYPE_EDGE_FALLING) 653 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT; 654 655 /* TRIG_SEL bit 1, INV bit 0 for level low */ 656 if (type & IRQ_TYPE_LEVEL_LOW) 657 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT; 658 659 /* TRIG_SEL bit 1, INV bit 1 for level high */ 660 if (type & IRQ_TYPE_LEVEL_HIGH) 661 value |= TRIG_SEL_BIT | INT_INV_BIT; 662 663 iowrite32(value, reg); 664 665 if (type & IRQ_TYPE_EDGE_BOTH) 666 irq_set_handler_locked(d, handle_edge_irq); 667 else if (type & IRQ_TYPE_LEVEL_MASK) 668 irq_set_handler_locked(d, handle_level_irq); 669 670 return 0; 671 } 672 673 static const struct irq_chip lp_irqchip = { 674 .name = "LP-GPIO", 675 .irq_ack = lp_irq_ack, 676 .irq_mask = lp_irq_mask, 677 .irq_unmask = lp_irq_unmask, 678 .irq_enable = lp_irq_enable, 679 .irq_disable = lp_irq_disable, 680 .irq_set_type = lp_irq_set_type, 681 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 682 GPIOCHIP_IRQ_RESOURCE_HELPERS, 683 }; 684 685 static int lp_gpio_irq_init_hw(struct gpio_chip *chip) 686 { 687 struct intel_pinctrl *lg = gpiochip_get_data(chip); 688 void __iomem *reg; 689 unsigned int base; 690 691 for (base = 0; base < lg->chip.ngpio; base += 32) { 692 /* disable gpio pin interrupts */ 693 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 694 iowrite32(0, reg); 695 /* Clear interrupt status register */ 696 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 697 iowrite32(0xffffffff, reg); 698 } 699 700 return 0; 701 } 702 703 static int lp_gpio_probe(struct platform_device *pdev) 704 { 705 const struct intel_pinctrl_soc_data *soc; 706 struct intel_pinctrl *lg; 707 struct gpio_chip *gc; 708 struct device *dev = &pdev->dev; 709 struct resource *io_rc; 710 void __iomem *regs; 711 unsigned int i; 712 int irq, ret; 713 714 soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev); 715 if (!soc) 716 return -ENODEV; 717 718 lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL); 719 if (!lg) 720 return -ENOMEM; 721 722 lg->dev = dev; 723 lg->soc = soc; 724 725 lg->ncommunities = lg->soc->ncommunities; 726 lg->communities = devm_kcalloc(dev, lg->ncommunities, 727 sizeof(*lg->communities), GFP_KERNEL); 728 if (!lg->communities) 729 return -ENOMEM; 730 731 lg->pctldesc = lptlp_pinctrl_desc; 732 lg->pctldesc.name = dev_name(dev); 733 lg->pctldesc.pins = lg->soc->pins; 734 lg->pctldesc.npins = lg->soc->npins; 735 736 lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg); 737 if (IS_ERR(lg->pctldev)) 738 return PTR_ERR(lg->pctldev); 739 740 platform_set_drvdata(pdev, lg); 741 742 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); 743 if (!io_rc) 744 return dev_err_probe(dev, -EINVAL, "missing IO resources\n"); 745 746 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); 747 if (!regs) 748 return dev_err_probe(dev, -EBUSY, "failed mapping IO region %pR\n", &io_rc); 749 750 for (i = 0; i < lg->soc->ncommunities; i++) { 751 struct intel_community *comm = &lg->communities[i]; 752 753 *comm = lg->soc->communities[i]; 754 755 comm->regs = regs; 756 comm->pad_regs = regs + 0x100; 757 } 758 759 raw_spin_lock_init(&lg->lock); 760 761 gc = &lg->chip; 762 gc->label = dev_name(dev); 763 gc->owner = THIS_MODULE; 764 gc->request = gpiochip_generic_request; 765 gc->free = gpiochip_generic_free; 766 gc->direction_input = lp_gpio_direction_input; 767 gc->direction_output = lp_gpio_direction_output; 768 gc->get = lp_gpio_get; 769 gc->set = lp_gpio_set; 770 gc->set_config = gpiochip_generic_config; 771 gc->get_direction = lp_gpio_get_direction; 772 gc->base = -1; 773 gc->ngpio = LP_NUM_GPIO; 774 gc->can_sleep = false; 775 gc->add_pin_ranges = intel_gpio_add_pin_ranges; 776 gc->parent = dev; 777 778 /* set up interrupts */ 779 irq = platform_get_irq_optional(pdev, 0); 780 if (irq > 0) { 781 struct gpio_irq_chip *girq; 782 783 girq = &gc->irq; 784 gpio_irq_chip_set_chip(girq, &lp_irqchip); 785 girq->init_hw = lp_gpio_irq_init_hw; 786 girq->parent_handler = lp_gpio_irq_handler; 787 girq->num_parents = 1; 788 girq->parents = devm_kcalloc(dev, girq->num_parents, 789 sizeof(*girq->parents), 790 GFP_KERNEL); 791 if (!girq->parents) 792 return -ENOMEM; 793 girq->parents[0] = irq; 794 girq->default_type = IRQ_TYPE_NONE; 795 girq->handler = handle_bad_irq; 796 } 797 798 ret = devm_gpiochip_add_data(dev, gc, lg); 799 if (ret) 800 return dev_err_probe(dev, ret, "failed to register gpiochip\n"); 801 802 return 0; 803 } 804 805 static int lp_gpio_resume(struct device *dev) 806 { 807 struct intel_pinctrl *lg = dev_get_drvdata(dev); 808 struct gpio_chip *chip = &lg->chip; 809 const char *dummy; 810 int i; 811 812 /* on some hardware suspend clears input sensing, re-enable it here */ 813 for_each_requested_gpio(chip, i, dummy) 814 lp_gpio_enable_input(lp_gpio_reg(chip, i, LP_CONFIG2)); 815 816 return 0; 817 } 818 819 static DEFINE_SIMPLE_DEV_PM_OPS(lp_gpio_pm_ops, NULL, lp_gpio_resume); 820 821 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { 822 { "INT33C7", (kernel_ulong_t)&lptlp_soc_data }, 823 { "INT3437", (kernel_ulong_t)&lptlp_soc_data }, 824 { } 825 }; 826 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); 827 828 static struct platform_driver lp_gpio_driver = { 829 .probe = lp_gpio_probe, 830 .driver = { 831 .name = "lp_gpio", 832 .pm = pm_sleep_ptr(&lp_gpio_pm_ops), 833 .acpi_match_table = lynxpoint_gpio_acpi_match, 834 }, 835 }; 836 837 static int __init lp_gpio_init(void) 838 { 839 return platform_driver_register(&lp_gpio_driver); 840 } 841 subsys_initcall(lp_gpio_init); 842 843 static void __exit lp_gpio_exit(void) 844 { 845 platform_driver_unregister(&lp_gpio_driver); 846 } 847 module_exit(lp_gpio_exit); 848 849 MODULE_AUTHOR("Mathias Nyman (Intel)"); 850 MODULE_AUTHOR("Andy Shevchenko (Intel)"); 851 MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver"); 852 MODULE_LICENSE("GPL v2"); 853 MODULE_ALIAS("platform:lp_gpio"); 854 MODULE_IMPORT_NS("PINCTRL_INTEL"); 855