1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Lynxpoint PCH pinctrl/GPIO driver 4 * 5 * Copyright (c) 2012, 2019, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/array_size.h> 12 #include <linux/bitops.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/seq_file.h> 20 #include <linux/slab.h> 21 #include <linux/types.h> 22 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinmux.h> 28 29 #include "pinctrl-intel.h" 30 31 #define COMMUNITY(p, n) \ 32 { \ 33 .pin_base = (p), \ 34 .npins = (n), \ 35 } 36 37 static const struct pinctrl_pin_desc lptlp_pins[] = { 38 PINCTRL_PIN(0, "GP0_UART1_RXD"), 39 PINCTRL_PIN(1, "GP1_UART1_TXD"), 40 PINCTRL_PIN(2, "GP2_UART1_RTSB"), 41 PINCTRL_PIN(3, "GP3_UART1_CTSB"), 42 PINCTRL_PIN(4, "GP4_I2C0_SDA"), 43 PINCTRL_PIN(5, "GP5_I2C0_SCL"), 44 PINCTRL_PIN(6, "GP6_I2C1_SDA"), 45 PINCTRL_PIN(7, "GP7_I2C1_SCL"), 46 PINCTRL_PIN(8, "GP8"), 47 PINCTRL_PIN(9, "GP9"), 48 PINCTRL_PIN(10, "GP10"), 49 PINCTRL_PIN(11, "GP11_SMBALERTB"), 50 PINCTRL_PIN(12, "GP12_LANPHYPC"), 51 PINCTRL_PIN(13, "GP13"), 52 PINCTRL_PIN(14, "GP14"), 53 PINCTRL_PIN(15, "GP15"), 54 PINCTRL_PIN(16, "GP16_MGPIO9"), 55 PINCTRL_PIN(17, "GP17_MGPIO10"), 56 PINCTRL_PIN(18, "GP18_SRC0CLKRQB"), 57 PINCTRL_PIN(19, "GP19_SRC1CLKRQB"), 58 PINCTRL_PIN(20, "GP20_SRC2CLKRQB"), 59 PINCTRL_PIN(21, "GP21_SRC3CLKRQB"), 60 PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"), 61 PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"), 62 PINCTRL_PIN(24, "GP24_MGPIO0"), 63 PINCTRL_PIN(25, "GP25_USBWAKEOUTB"), 64 PINCTRL_PIN(26, "GP26_MGPIO5"), 65 PINCTRL_PIN(27, "GP27_MGPIO6"), 66 PINCTRL_PIN(28, "GP28_MGPIO7"), 67 PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"), 68 PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"), 69 PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"), 70 PINCTRL_PIN(32, "GP32_CLKRUNB"), 71 PINCTRL_PIN(33, "GP33_DEVSLP0"), 72 PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"), 73 PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"), 74 PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"), 75 PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"), 76 PINCTRL_PIN(38, "GP38_DEVSLP1"), 77 PINCTRL_PIN(39, "GP39_DEVSLP2"), 78 PINCTRL_PIN(40, "GP40_OC0B"), 79 PINCTRL_PIN(41, "GP41_OC1B"), 80 PINCTRL_PIN(42, "GP42_OC2B"), 81 PINCTRL_PIN(43, "GP43_OC3B"), 82 PINCTRL_PIN(44, "GP44"), 83 PINCTRL_PIN(45, "GP45_TMS2"), 84 PINCTRL_PIN(46, "GP46_TDO2"), 85 PINCTRL_PIN(47, "GP47"), 86 PINCTRL_PIN(48, "GP48"), 87 PINCTRL_PIN(49, "GP49"), 88 PINCTRL_PIN(50, "GP50"), 89 PINCTRL_PIN(51, "GP51_GSXDOUT"), 90 PINCTRL_PIN(52, "GP52_GSXSLOAD"), 91 PINCTRL_PIN(53, "GP53_GSXDIN"), 92 PINCTRL_PIN(54, "GP54_GSXSRESETB"), 93 PINCTRL_PIN(55, "GP55_GSXCLK"), 94 PINCTRL_PIN(56, "GP56"), 95 PINCTRL_PIN(57, "GP57"), 96 PINCTRL_PIN(58, "GP58"), 97 PINCTRL_PIN(59, "GP59"), 98 PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"), 99 PINCTRL_PIN(61, "GP61_SUS_STATB"), 100 PINCTRL_PIN(62, "GP62_SUSCLK"), 101 PINCTRL_PIN(63, "GP63_SLP_S5B"), 102 PINCTRL_PIN(64, "GP64_SDIO_CLK"), 103 PINCTRL_PIN(65, "GP65_SDIO_CMD"), 104 PINCTRL_PIN(66, "GP66_SDIO_D0"), 105 PINCTRL_PIN(67, "GP67_SDIO_D1"), 106 PINCTRL_PIN(68, "GP68_SDIO_D2"), 107 PINCTRL_PIN(69, "GP69_SDIO_D3"), 108 PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"), 109 PINCTRL_PIN(71, "GP71_MPHYPC"), 110 PINCTRL_PIN(72, "GP72_BATLOWB"), 111 PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"), 112 PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"), 113 PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"), 114 PINCTRL_PIN(76, "GP76_BMBUSYB"), 115 PINCTRL_PIN(77, "GP77_PIRQAB"), 116 PINCTRL_PIN(78, "GP78_PIRQBB"), 117 PINCTRL_PIN(79, "GP79_PIRQCB"), 118 PINCTRL_PIN(80, "GP80_PIRQDB"), 119 PINCTRL_PIN(81, "GP81_SPKR"), 120 PINCTRL_PIN(82, "GP82_RCINB"), 121 PINCTRL_PIN(83, "GP83_GSPI0_CSB"), 122 PINCTRL_PIN(84, "GP84_GSPI0_CLK"), 123 PINCTRL_PIN(85, "GP85_GSPI0_MISO"), 124 PINCTRL_PIN(86, "GP86_GSPI0_MOSI"), 125 PINCTRL_PIN(87, "GP87_GSPI1_CSB"), 126 PINCTRL_PIN(88, "GP88_GSPI1_CLK"), 127 PINCTRL_PIN(89, "GP89_GSPI1_MISO"), 128 PINCTRL_PIN(90, "GP90_GSPI1_MOSI"), 129 PINCTRL_PIN(91, "GP91_UART0_RXD"), 130 PINCTRL_PIN(92, "GP92_UART0_TXD"), 131 PINCTRL_PIN(93, "GP93_UART0_RTSB"), 132 PINCTRL_PIN(94, "GP94_UART0_CTSB"), 133 }; 134 135 static const struct intel_community lptlp_communities[] = { 136 COMMUNITY(0, 95), 137 }; 138 139 static const struct intel_pinctrl_soc_data lptlp_soc_data = { 140 .pins = lptlp_pins, 141 .npins = ARRAY_SIZE(lptlp_pins), 142 .communities = lptlp_communities, 143 .ncommunities = ARRAY_SIZE(lptlp_communities), 144 }; 145 146 /* LynxPoint chipset has support for 95 GPIO pins */ 147 148 #define LP_NUM_GPIO 95 149 150 /* Bitmapped register offsets */ 151 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ 152 #define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */ 153 #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */ 154 #define LP_INT_STAT 0x80 155 #define LP_INT_ENABLE 0x90 156 157 /* Each pin has two 32 bit config registers, starting at 0x100 */ 158 #define LP_CONFIG1 0x100 159 #define LP_CONFIG2 0x104 160 161 /* LP_CONFIG1 reg bits */ 162 #define OUT_LVL_BIT BIT(31) 163 #define IN_LVL_BIT BIT(30) 164 #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */ 165 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */ 166 #define DIR_BIT BIT(2) /* 0: Output, 1: Input */ 167 #define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */ 168 #define USE_SEL_NATIVE (0 << 0) 169 #define USE_SEL_GPIO (1 << 0) 170 171 /* LP_CONFIG2 reg bits */ 172 #define GPINDIS_BIT BIT(2) /* disable input sensing */ 173 #define GPIWP_MASK GENMASK(1, 0) /* weak pull options */ 174 #define GPIWP_NONE 0 /* none */ 175 #define GPIWP_DOWN 1 /* weak pull down */ 176 #define GPIWP_UP 2 /* weak pull up */ 177 178 /* 179 * Lynxpoint gpios are controlled through both bitmapped registers and 180 * per gpio specific registers. The bitmapped registers are in chunks of 181 * 3 x 32bit registers to cover all 95 GPIOs 182 * 183 * per gpio specific registers consist of two 32bit registers per gpio 184 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of 185 * 190 config registers. 186 * 187 * A simplified view of the register layout look like this: 188 * 189 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers) 190 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63 191 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 192 * ... 193 * LP_INT_ENABLE[31:0] ... 194 * LP_INT_ENABLE[63:32] ... 195 * LP_INT_ENABLE[94:64] ... 196 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) 197 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 198 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1 199 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1 200 * LP2_CONFIG1 (gpio 2) ... 201 * LP2_CONFIG2 (gpio 2) ... 202 * ... 203 * LP94_CONFIG1 (gpio 94) ... 204 * LP94_CONFIG2 (gpio 94) ... 205 * 206 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55. 207 */ 208 209 static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, 210 int reg) 211 { 212 struct intel_pinctrl *lg = gpiochip_get_data(chip); 213 struct intel_community *comm; 214 int reg_offset; 215 216 comm = intel_get_community(lg, offset); 217 if (!comm) 218 return NULL; 219 220 offset -= comm->pin_base; 221 222 if (reg == LP_CONFIG1 || reg == LP_CONFIG2) 223 /* per gpio specific config registers */ 224 reg_offset = offset * 8; 225 else 226 /* bitmapped registers */ 227 reg_offset = (offset / 32) * 4; 228 229 return comm->regs + reg_offset + reg; 230 } 231 232 static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin) 233 { 234 void __iomem *acpi_use; 235 236 acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED); 237 if (!acpi_use) 238 return true; 239 240 return !(ioread32(acpi_use) & BIT(pin % 32)); 241 } 242 243 static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset) 244 { 245 void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC); 246 u32 value; 247 248 value = ioread32(ioxapic_use); 249 250 if (offset >= 8 && offset <= 10) 251 return !!(value & BIT(offset - 8 + 0)); 252 if (offset >= 13 && offset <= 14) 253 return !!(value & BIT(offset - 13 + 3)); 254 if (offset >= 45 && offset <= 55) 255 return !!(value & BIT(offset - 45 + 5)); 256 257 return false; 258 } 259 260 static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 261 unsigned int pin) 262 { 263 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 264 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 265 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 266 u32 value, mode; 267 268 value = ioread32(reg); 269 270 mode = value & USE_SEL_MASK; 271 if (mode == USE_SEL_GPIO) 272 seq_puts(s, "GPIO "); 273 else 274 seq_printf(s, "mode %d ", mode); 275 276 seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2)); 277 278 if (lp_gpio_acpi_use(lg, pin)) 279 seq_puts(s, " [ACPI]"); 280 } 281 282 static const struct pinctrl_ops lptlp_pinctrl_ops = { 283 .get_groups_count = intel_get_groups_count, 284 .get_group_name = intel_get_group_name, 285 .get_group_pins = intel_get_group_pins, 286 .pin_dbg_show = lp_pin_dbg_show, 287 }; 288 289 static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev, 290 unsigned int function, unsigned int group) 291 { 292 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 293 const struct intel_pingroup *grp = &lg->soc->groups[group]; 294 unsigned long flags; 295 int i; 296 297 raw_spin_lock_irqsave(&lg->lock, flags); 298 299 /* Now enable the mux setting for each pin in the group */ 300 for (i = 0; i < grp->grp.npins; i++) { 301 void __iomem *reg = lp_gpio_reg(&lg->chip, grp->grp.pins[i], LP_CONFIG1); 302 u32 value; 303 304 value = ioread32(reg); 305 306 value &= ~USE_SEL_MASK; 307 if (grp->modes) 308 value |= grp->modes[i]; 309 else 310 value |= grp->mode; 311 312 iowrite32(value, reg); 313 } 314 315 raw_spin_unlock_irqrestore(&lg->lock, flags); 316 317 return 0; 318 } 319 320 static void lp_gpio_enable_input(void __iomem *reg) 321 { 322 iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg); 323 } 324 325 static void lp_gpio_disable_input(void __iomem *reg) 326 { 327 iowrite32(ioread32(reg) | GPINDIS_BIT, reg); 328 } 329 330 static int lp_gpio_request_enable(struct pinctrl_dev *pctldev, 331 struct pinctrl_gpio_range *range, 332 unsigned int pin) 333 { 334 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 335 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 336 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 337 unsigned long flags; 338 u32 value; 339 340 raw_spin_lock_irqsave(&lg->lock, flags); 341 342 /* 343 * Reconfigure pin to GPIO mode if needed and issue a warning, 344 * since we expect firmware to configure it properly. 345 */ 346 value = ioread32(reg); 347 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { 348 iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); 349 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin); 350 } 351 352 /* Enable input sensing */ 353 lp_gpio_enable_input(conf2); 354 355 raw_spin_unlock_irqrestore(&lg->lock, flags); 356 357 return 0; 358 } 359 360 static void lp_gpio_disable_free(struct pinctrl_dev *pctldev, 361 struct pinctrl_gpio_range *range, 362 unsigned int pin) 363 { 364 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 365 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 366 unsigned long flags; 367 368 raw_spin_lock_irqsave(&lg->lock, flags); 369 370 /* Disable input sensing */ 371 lp_gpio_disable_input(conf2); 372 373 raw_spin_unlock_irqrestore(&lg->lock, flags); 374 } 375 376 static int lp_gpio_set_direction(struct pinctrl_dev *pctldev, 377 struct pinctrl_gpio_range *range, 378 unsigned int pin, bool input) 379 { 380 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 381 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 382 unsigned long flags; 383 u32 value; 384 385 raw_spin_lock_irqsave(&lg->lock, flags); 386 387 value = ioread32(reg); 388 value &= ~DIR_BIT; 389 if (input) { 390 value |= DIR_BIT; 391 } else { 392 /* 393 * Before making any direction modifications, do a check if GPIO 394 * is set for direct IRQ. On Lynxpoint, setting GPIO to output 395 * does not make sense, so let's at least warn the caller before 396 * they shoot themselves in the foot. 397 */ 398 WARN(lp_gpio_ioxapic_use(&lg->chip, pin), 399 "Potential Error: Setting GPIO to output with IOxAPIC redirection"); 400 } 401 iowrite32(value, reg); 402 403 raw_spin_unlock_irqrestore(&lg->lock, flags); 404 405 return 0; 406 } 407 408 static const struct pinmux_ops lptlp_pinmux_ops = { 409 .get_functions_count = intel_get_functions_count, 410 .get_function_name = intel_get_function_name, 411 .get_function_groups = intel_get_function_groups, 412 .set_mux = lp_pinmux_set_mux, 413 .gpio_request_enable = lp_gpio_request_enable, 414 .gpio_disable_free = lp_gpio_disable_free, 415 .gpio_set_direction = lp_gpio_set_direction, 416 }; 417 418 static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 419 unsigned long *config) 420 { 421 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 422 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 423 enum pin_config_param param = pinconf_to_config_param(*config); 424 unsigned long flags; 425 u32 value, pull; 426 u16 arg; 427 428 raw_spin_lock_irqsave(&lg->lock, flags); 429 value = ioread32(conf2); 430 raw_spin_unlock_irqrestore(&lg->lock, flags); 431 432 pull = value & GPIWP_MASK; 433 434 switch (param) { 435 case PIN_CONFIG_BIAS_DISABLE: 436 if (pull != GPIWP_NONE) 437 return -EINVAL; 438 arg = 0; 439 break; 440 case PIN_CONFIG_BIAS_PULL_DOWN: 441 if (pull != GPIWP_DOWN) 442 return -EINVAL; 443 444 arg = 1; 445 break; 446 case PIN_CONFIG_BIAS_PULL_UP: 447 if (pull != GPIWP_UP) 448 return -EINVAL; 449 450 arg = 1; 451 break; 452 default: 453 return -ENOTSUPP; 454 } 455 456 *config = pinconf_to_config_packed(param, arg); 457 458 return 0; 459 } 460 461 static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 462 unsigned long *configs, unsigned int num_configs) 463 { 464 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 465 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 466 enum pin_config_param param; 467 unsigned long flags; 468 int i, ret = 0; 469 u32 value; 470 471 raw_spin_lock_irqsave(&lg->lock, flags); 472 473 value = ioread32(conf2); 474 475 for (i = 0; i < num_configs; i++) { 476 param = pinconf_to_config_param(configs[i]); 477 478 switch (param) { 479 case PIN_CONFIG_BIAS_DISABLE: 480 value &= ~GPIWP_MASK; 481 value |= GPIWP_NONE; 482 break; 483 case PIN_CONFIG_BIAS_PULL_DOWN: 484 value &= ~GPIWP_MASK; 485 value |= GPIWP_DOWN; 486 break; 487 case PIN_CONFIG_BIAS_PULL_UP: 488 value &= ~GPIWP_MASK; 489 value |= GPIWP_UP; 490 break; 491 default: 492 ret = -ENOTSUPP; 493 } 494 495 if (ret) 496 break; 497 } 498 499 if (!ret) 500 iowrite32(value, conf2); 501 502 raw_spin_unlock_irqrestore(&lg->lock, flags); 503 504 return ret; 505 } 506 507 static const struct pinconf_ops lptlp_pinconf_ops = { 508 .is_generic = true, 509 .pin_config_get = lp_pin_config_get, 510 .pin_config_set = lp_pin_config_set, 511 }; 512 513 static const struct pinctrl_desc lptlp_pinctrl_desc = { 514 .pctlops = &lptlp_pinctrl_ops, 515 .pmxops = &lptlp_pinmux_ops, 516 .confops = &lptlp_pinconf_ops, 517 .owner = THIS_MODULE, 518 }; 519 520 static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) 521 { 522 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 523 return !!(ioread32(reg) & IN_LVL_BIT); 524 } 525 526 static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 527 { 528 struct intel_pinctrl *lg = gpiochip_get_data(chip); 529 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 530 unsigned long flags; 531 532 raw_spin_lock_irqsave(&lg->lock, flags); 533 534 if (value) 535 iowrite32(ioread32(reg) | OUT_LVL_BIT, reg); 536 else 537 iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg); 538 539 raw_spin_unlock_irqrestore(&lg->lock, flags); 540 } 541 542 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 543 { 544 return pinctrl_gpio_direction_input(chip, offset); 545 } 546 547 static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 548 int value) 549 { 550 lp_gpio_set(chip, offset, value); 551 552 return pinctrl_gpio_direction_output(chip, offset); 553 } 554 555 static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 556 { 557 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 558 559 if (ioread32(reg) & DIR_BIT) 560 return GPIO_LINE_DIRECTION_IN; 561 562 return GPIO_LINE_DIRECTION_OUT; 563 } 564 565 static void lp_gpio_irq_handler(struct irq_desc *desc) 566 { 567 struct irq_data *data = irq_desc_get_irq_data(desc); 568 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 569 struct intel_pinctrl *lg = gpiochip_get_data(gc); 570 struct irq_chip *chip = irq_data_get_irq_chip(data); 571 void __iomem *reg, *ena; 572 unsigned long pending; 573 u32 base, pin; 574 575 /* check from GPIO controller which pin triggered the interrupt */ 576 for (base = 0; base < lg->chip.ngpio; base += 32) { 577 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 578 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 579 580 /* Only interrupts that are enabled */ 581 pending = ioread32(reg) & ioread32(ena); 582 583 for_each_set_bit(pin, &pending, 32) 584 generic_handle_domain_irq(lg->chip.irq.domain, base + pin); 585 } 586 chip->irq_eoi(data); 587 } 588 589 static void lp_irq_ack(struct irq_data *d) 590 { 591 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 592 struct intel_pinctrl *lg = gpiochip_get_data(gc); 593 irq_hw_number_t hwirq = irqd_to_hwirq(d); 594 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); 595 unsigned long flags; 596 597 raw_spin_lock_irqsave(&lg->lock, flags); 598 iowrite32(BIT(hwirq % 32), reg); 599 raw_spin_unlock_irqrestore(&lg->lock, flags); 600 } 601 602 static void lp_irq_unmask(struct irq_data *d) 603 { 604 } 605 606 static void lp_irq_mask(struct irq_data *d) 607 { 608 } 609 610 static void lp_irq_enable(struct irq_data *d) 611 { 612 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 613 struct intel_pinctrl *lg = gpiochip_get_data(gc); 614 irq_hw_number_t hwirq = irqd_to_hwirq(d); 615 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 616 unsigned long flags; 617 618 gpiochip_enable_irq(gc, hwirq); 619 620 raw_spin_lock_irqsave(&lg->lock, flags); 621 iowrite32(ioread32(reg) | BIT(hwirq % 32), reg); 622 raw_spin_unlock_irqrestore(&lg->lock, flags); 623 } 624 625 static void lp_irq_disable(struct irq_data *d) 626 { 627 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 628 struct intel_pinctrl *lg = gpiochip_get_data(gc); 629 irq_hw_number_t hwirq = irqd_to_hwirq(d); 630 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 631 unsigned long flags; 632 633 raw_spin_lock_irqsave(&lg->lock, flags); 634 iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg); 635 raw_spin_unlock_irqrestore(&lg->lock, flags); 636 637 gpiochip_disable_irq(gc, hwirq); 638 } 639 640 static int lp_irq_set_type(struct irq_data *d, unsigned int type) 641 { 642 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 643 struct intel_pinctrl *lg = gpiochip_get_data(gc); 644 irq_hw_number_t hwirq = irqd_to_hwirq(d); 645 unsigned long flags; 646 void __iomem *reg; 647 u32 value; 648 649 reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); 650 if (!reg) 651 return -EINVAL; 652 653 /* Fail if BIOS reserved pin for ACPI use */ 654 if (lp_gpio_acpi_use(lg, hwirq)) { 655 dev_err(lg->dev, "pin %lu can't be used as IRQ\n", hwirq); 656 return -EBUSY; 657 } 658 659 raw_spin_lock_irqsave(&lg->lock, flags); 660 value = ioread32(reg); 661 662 /* set both TRIG_SEL and INV bits to 0 for rising edge */ 663 if (type & IRQ_TYPE_EDGE_RISING) 664 value &= ~(TRIG_SEL_BIT | INT_INV_BIT); 665 666 /* TRIG_SEL bit 0, INV bit 1 for falling edge */ 667 if (type & IRQ_TYPE_EDGE_FALLING) 668 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT; 669 670 /* TRIG_SEL bit 1, INV bit 0 for level low */ 671 if (type & IRQ_TYPE_LEVEL_LOW) 672 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT; 673 674 /* TRIG_SEL bit 1, INV bit 1 for level high */ 675 if (type & IRQ_TYPE_LEVEL_HIGH) 676 value |= TRIG_SEL_BIT | INT_INV_BIT; 677 678 iowrite32(value, reg); 679 680 if (type & IRQ_TYPE_EDGE_BOTH) 681 irq_set_handler_locked(d, handle_edge_irq); 682 else if (type & IRQ_TYPE_LEVEL_MASK) 683 irq_set_handler_locked(d, handle_level_irq); 684 685 raw_spin_unlock_irqrestore(&lg->lock, flags); 686 687 return 0; 688 } 689 690 static const struct irq_chip lp_irqchip = { 691 .name = "LP-GPIO", 692 .irq_ack = lp_irq_ack, 693 .irq_mask = lp_irq_mask, 694 .irq_unmask = lp_irq_unmask, 695 .irq_enable = lp_irq_enable, 696 .irq_disable = lp_irq_disable, 697 .irq_set_type = lp_irq_set_type, 698 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 699 GPIOCHIP_IRQ_RESOURCE_HELPERS, 700 }; 701 702 static int lp_gpio_irq_init_hw(struct gpio_chip *chip) 703 { 704 struct intel_pinctrl *lg = gpiochip_get_data(chip); 705 void __iomem *reg; 706 unsigned int base; 707 708 for (base = 0; base < lg->chip.ngpio; base += 32) { 709 /* disable gpio pin interrupts */ 710 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 711 iowrite32(0, reg); 712 /* Clear interrupt status register */ 713 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 714 iowrite32(0xffffffff, reg); 715 } 716 717 return 0; 718 } 719 720 static int lp_gpio_add_pin_ranges(struct gpio_chip *chip) 721 { 722 struct intel_pinctrl *lg = gpiochip_get_data(chip); 723 struct device *dev = lg->dev; 724 int ret; 725 726 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins); 727 if (ret) 728 dev_err(dev, "failed to add GPIO pin range\n"); 729 730 return ret; 731 } 732 733 static int lp_gpio_probe(struct platform_device *pdev) 734 { 735 const struct intel_pinctrl_soc_data *soc; 736 struct intel_pinctrl *lg; 737 struct gpio_chip *gc; 738 struct device *dev = &pdev->dev; 739 struct resource *io_rc; 740 void __iomem *regs; 741 unsigned int i; 742 int irq, ret; 743 744 soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev); 745 if (!soc) 746 return -ENODEV; 747 748 lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL); 749 if (!lg) 750 return -ENOMEM; 751 752 lg->dev = dev; 753 lg->soc = soc; 754 755 lg->ncommunities = lg->soc->ncommunities; 756 lg->communities = devm_kcalloc(dev, lg->ncommunities, 757 sizeof(*lg->communities), GFP_KERNEL); 758 if (!lg->communities) 759 return -ENOMEM; 760 761 lg->pctldesc = lptlp_pinctrl_desc; 762 lg->pctldesc.name = dev_name(dev); 763 lg->pctldesc.pins = lg->soc->pins; 764 lg->pctldesc.npins = lg->soc->npins; 765 766 lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg); 767 if (IS_ERR(lg->pctldev)) { 768 dev_err(dev, "failed to register pinctrl driver\n"); 769 return PTR_ERR(lg->pctldev); 770 } 771 772 platform_set_drvdata(pdev, lg); 773 774 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); 775 if (!io_rc) { 776 dev_err(dev, "missing IO resources\n"); 777 return -EINVAL; 778 } 779 780 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); 781 if (!regs) { 782 dev_err(dev, "failed mapping IO region %pR\n", &io_rc); 783 return -EBUSY; 784 } 785 786 for (i = 0; i < lg->soc->ncommunities; i++) { 787 struct intel_community *comm = &lg->communities[i]; 788 789 *comm = lg->soc->communities[i]; 790 791 comm->regs = regs; 792 comm->pad_regs = regs + 0x100; 793 } 794 795 raw_spin_lock_init(&lg->lock); 796 797 gc = &lg->chip; 798 gc->label = dev_name(dev); 799 gc->owner = THIS_MODULE; 800 gc->request = gpiochip_generic_request; 801 gc->free = gpiochip_generic_free; 802 gc->direction_input = lp_gpio_direction_input; 803 gc->direction_output = lp_gpio_direction_output; 804 gc->get = lp_gpio_get; 805 gc->set = lp_gpio_set; 806 gc->set_config = gpiochip_generic_config; 807 gc->get_direction = lp_gpio_get_direction; 808 gc->base = -1; 809 gc->ngpio = LP_NUM_GPIO; 810 gc->can_sleep = false; 811 gc->add_pin_ranges = lp_gpio_add_pin_ranges; 812 gc->parent = dev; 813 814 /* set up interrupts */ 815 irq = platform_get_irq_optional(pdev, 0); 816 if (irq > 0) { 817 struct gpio_irq_chip *girq; 818 819 girq = &gc->irq; 820 gpio_irq_chip_set_chip(girq, &lp_irqchip); 821 girq->init_hw = lp_gpio_irq_init_hw; 822 girq->parent_handler = lp_gpio_irq_handler; 823 girq->num_parents = 1; 824 girq->parents = devm_kcalloc(dev, girq->num_parents, 825 sizeof(*girq->parents), 826 GFP_KERNEL); 827 if (!girq->parents) 828 return -ENOMEM; 829 girq->parents[0] = irq; 830 girq->default_type = IRQ_TYPE_NONE; 831 girq->handler = handle_bad_irq; 832 } 833 834 ret = devm_gpiochip_add_data(dev, gc, lg); 835 if (ret) { 836 dev_err(dev, "failed adding lp-gpio chip\n"); 837 return ret; 838 } 839 840 return 0; 841 } 842 843 static int lp_gpio_resume(struct device *dev) 844 { 845 struct intel_pinctrl *lg = dev_get_drvdata(dev); 846 struct gpio_chip *chip = &lg->chip; 847 const char *dummy; 848 int i; 849 850 /* on some hardware suspend clears input sensing, re-enable it here */ 851 for_each_requested_gpio(chip, i, dummy) 852 lp_gpio_enable_input(lp_gpio_reg(chip, i, LP_CONFIG2)); 853 854 return 0; 855 } 856 857 static DEFINE_SIMPLE_DEV_PM_OPS(lp_gpio_pm_ops, NULL, lp_gpio_resume); 858 859 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { 860 { "INT33C7", (kernel_ulong_t)&lptlp_soc_data }, 861 { "INT3437", (kernel_ulong_t)&lptlp_soc_data }, 862 { } 863 }; 864 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); 865 866 static struct platform_driver lp_gpio_driver = { 867 .probe = lp_gpio_probe, 868 .driver = { 869 .name = "lp_gpio", 870 .pm = pm_sleep_ptr(&lp_gpio_pm_ops), 871 .acpi_match_table = lynxpoint_gpio_acpi_match, 872 }, 873 }; 874 875 static int __init lp_gpio_init(void) 876 { 877 return platform_driver_register(&lp_gpio_driver); 878 } 879 subsys_initcall(lp_gpio_init); 880 881 static void __exit lp_gpio_exit(void) 882 { 883 platform_driver_unregister(&lp_gpio_driver); 884 } 885 module_exit(lp_gpio_exit); 886 887 MODULE_AUTHOR("Mathias Nyman (Intel)"); 888 MODULE_AUTHOR("Andy Shevchenko (Intel)"); 889 MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver"); 890 MODULE_LICENSE("GPL v2"); 891 MODULE_ALIAS("platform:lp_gpio"); 892 MODULE_IMPORT_NS(PINCTRL_INTEL); 893