1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel pinctrl/GPIO core driver. 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/log2.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/seq_file.h> 18 #include <linux/string_helpers.h> 19 #include <linux/time.h> 20 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 27 #include <linux/platform_data/x86/pwm-lpss.h> 28 29 #include "../core.h" 30 #include "pinctrl-intel.h" 31 32 /* Offset from regs */ 33 #define REVID 0x000 34 #define REVID_SHIFT 16 35 #define REVID_MASK GENMASK(31, 16) 36 37 #define CAPLIST 0x004 38 #define CAPLIST_ID_SHIFT 16 39 #define CAPLIST_ID_MASK GENMASK(23, 16) 40 #define CAPLIST_ID_GPIO_HW_INFO 1 41 #define CAPLIST_ID_PWM 2 42 #define CAPLIST_ID_BLINK 3 43 #define CAPLIST_ID_EXP 4 44 #define CAPLIST_NEXT_SHIFT 0 45 #define CAPLIST_NEXT_MASK GENMASK(15, 0) 46 47 #define PADBAR 0x00c 48 49 #define PADOWN_BITS 4 50 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 51 #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) 52 #define PADOWN_GPP(p) ((p) / 8) 53 54 #define PWMC 0x204 55 56 /* Offset from pad_regs */ 57 #define PADCFG0 0x000 58 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25) 59 #define PADCFG0_RXEVCFG_LEVEL (0 << 25) 60 #define PADCFG0_RXEVCFG_EDGE (1 << 25) 61 #define PADCFG0_RXEVCFG_DISABLED (2 << 25) 62 #define PADCFG0_RXEVCFG_EDGE_BOTH (3 << 25) 63 #define PADCFG0_PREGFRXSEL BIT(24) 64 #define PADCFG0_RXINV BIT(23) 65 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 66 #define PADCFG0_GPIROUTSCI BIT(19) 67 #define PADCFG0_GPIROUTSMI BIT(18) 68 #define PADCFG0_GPIROUTNMI BIT(17) 69 #define PADCFG0_PMODE_SHIFT 10 70 #define PADCFG0_PMODE_MASK GENMASK(13, 10) 71 #define PADCFG0_PMODE_GPIO 0 72 #define PADCFG0_GPIORXDIS BIT(9) 73 #define PADCFG0_GPIOTXDIS BIT(8) 74 #define PADCFG0_GPIORXSTATE BIT(1) 75 #define PADCFG0_GPIOTXSTATE BIT(0) 76 77 #define PADCFG1 0x004 78 #define PADCFG1_TERM_UP BIT(13) 79 #define PADCFG1_TERM_SHIFT 10 80 #define PADCFG1_TERM_MASK GENMASK(12, 10) 81 #define PADCFG1_TERM_20K BIT(2) 82 #define PADCFG1_TERM_5K BIT(1) 83 #define PADCFG1_TERM_4K (BIT(2) | BIT(1)) 84 #define PADCFG1_TERM_1K BIT(0) 85 #define PADCFG1_TERM_952 (BIT(2) | BIT(0)) 86 #define PADCFG1_TERM_833 (BIT(1) | BIT(0)) 87 #define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0)) 88 89 #define PADCFG2 0x008 90 #define PADCFG2_DEBOUNCE_SHIFT 1 91 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) 92 #define PADCFG2_DEBEN BIT(0) 93 94 #define DEBOUNCE_PERIOD_NSEC 31250 95 96 struct intel_pad_context { 97 u32 padcfg0; 98 u32 padcfg1; 99 u32 padcfg2; 100 }; 101 102 struct intel_community_context { 103 u32 *intmask; 104 u32 *hostown; 105 }; 106 107 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 108 #define padgroup_offset(g, p) ((p) - (g)->base) 109 110 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 111 unsigned int pin) 112 { 113 struct intel_community *community; 114 int i; 115 116 for (i = 0; i < pctrl->ncommunities; i++) { 117 community = &pctrl->communities[i]; 118 if (pin >= community->pin_base && 119 pin < community->pin_base + community->npins) 120 return community; 121 } 122 123 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 124 return NULL; 125 } 126 127 static const struct intel_padgroup * 128 intel_community_get_padgroup(const struct intel_community *community, 129 unsigned int pin) 130 { 131 int i; 132 133 for (i = 0; i < community->ngpps; i++) { 134 const struct intel_padgroup *padgrp = &community->gpps[i]; 135 136 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) 137 return padgrp; 138 } 139 140 return NULL; 141 } 142 143 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, 144 unsigned int pin, unsigned int reg) 145 { 146 const struct intel_community *community; 147 unsigned int padno; 148 size_t nregs; 149 150 community = intel_get_community(pctrl, pin); 151 if (!community) 152 return NULL; 153 154 padno = pin_to_padno(community, pin); 155 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; 156 157 if (reg >= nregs * 4) 158 return NULL; 159 160 return community->pad_regs + reg + padno * nregs * 4; 161 } 162 163 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin) 164 { 165 const struct intel_community *community; 166 const struct intel_padgroup *padgrp; 167 unsigned int gpp, offset, gpp_offset; 168 void __iomem *padown; 169 170 community = intel_get_community(pctrl, pin); 171 if (!community) 172 return false; 173 if (!community->padown_offset) 174 return true; 175 176 padgrp = intel_community_get_padgroup(community, pin); 177 if (!padgrp) 178 return false; 179 180 gpp_offset = padgroup_offset(padgrp, pin); 181 gpp = PADOWN_GPP(gpp_offset); 182 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; 183 padown = community->regs + offset; 184 185 return !(readl(padown) & PADOWN_MASK(gpp_offset)); 186 } 187 188 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin) 189 { 190 const struct intel_community *community; 191 const struct intel_padgroup *padgrp; 192 unsigned int offset, gpp_offset; 193 void __iomem *hostown; 194 195 community = intel_get_community(pctrl, pin); 196 if (!community) 197 return true; 198 if (!community->hostown_offset) 199 return false; 200 201 padgrp = intel_community_get_padgroup(community, pin); 202 if (!padgrp) 203 return true; 204 205 gpp_offset = padgroup_offset(padgrp, pin); 206 offset = community->hostown_offset + padgrp->reg_num * 4; 207 hostown = community->regs + offset; 208 209 return !(readl(hostown) & BIT(gpp_offset)); 210 } 211 212 /** 213 * enum - Locking variants of the pad configuration 214 * 215 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers 216 * @PAD_LOCKED: pad configuration registers, except TX state, are locked 217 * @PAD_LOCKED_TX: pad configuration TX state is locked 218 * @PAD_LOCKED_FULL: pad configuration registers are locked completely 219 * 220 * Locking is considered as read-only mode for corresponding registers and 221 * their respective fields. That said, TX state bit is locked separately from 222 * the main locking scheme. 223 */ 224 enum { 225 PAD_UNLOCKED = 0, 226 PAD_LOCKED = 1, 227 PAD_LOCKED_TX = 2, 228 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX, 229 }; 230 231 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin) 232 { 233 struct intel_community *community; 234 const struct intel_padgroup *padgrp; 235 unsigned int offset, gpp_offset; 236 u32 value; 237 int ret = PAD_UNLOCKED; 238 239 community = intel_get_community(pctrl, pin); 240 if (!community) 241 return PAD_LOCKED_FULL; 242 if (!community->padcfglock_offset) 243 return PAD_UNLOCKED; 244 245 padgrp = intel_community_get_padgroup(community, pin); 246 if (!padgrp) 247 return PAD_LOCKED_FULL; 248 249 gpp_offset = padgroup_offset(padgrp, pin); 250 251 /* 252 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 253 * the pad is considered unlocked. Any other case means that it is 254 * either fully or partially locked. 255 */ 256 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; 257 value = readl(community->regs + offset); 258 if (value & BIT(gpp_offset)) 259 ret |= PAD_LOCKED; 260 261 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; 262 value = readl(community->regs + offset); 263 if (value & BIT(gpp_offset)) 264 ret |= PAD_LOCKED_TX; 265 266 return ret; 267 } 268 269 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin) 270 { 271 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED; 272 } 273 274 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) 275 { 276 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); 277 } 278 279 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 280 { 281 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 282 283 return pctrl->soc->ngroups; 284 } 285 286 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 287 unsigned int group) 288 { 289 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 290 291 return pctrl->soc->groups[group].grp.name; 292 } 293 294 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 295 const unsigned int **pins, unsigned int *npins) 296 { 297 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 298 299 *pins = pctrl->soc->groups[group].grp.pins; 300 *npins = pctrl->soc->groups[group].grp.npins; 301 return 0; 302 } 303 304 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 305 unsigned int pin) 306 { 307 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 308 void __iomem *padcfg; 309 u32 cfg0, cfg1, mode; 310 int locked; 311 bool acpi; 312 313 if (!intel_pad_owned_by_host(pctrl, pin)) { 314 seq_puts(s, "not available"); 315 return; 316 } 317 318 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 319 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 320 321 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 322 if (mode == PADCFG0_PMODE_GPIO) 323 seq_puts(s, "GPIO "); 324 else 325 seq_printf(s, "mode %d ", mode); 326 327 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 328 329 /* Dump the additional PADCFG registers if available */ 330 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); 331 if (padcfg) 332 seq_printf(s, " 0x%08x", readl(padcfg)); 333 334 locked = intel_pad_locked(pctrl, pin); 335 acpi = intel_pad_acpi_mode(pctrl, pin); 336 337 if (locked || acpi) { 338 seq_puts(s, " ["); 339 if (locked) 340 seq_puts(s, "LOCKED"); 341 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) 342 seq_puts(s, " tx"); 343 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) 344 seq_puts(s, " full"); 345 346 if (locked && acpi) 347 seq_puts(s, ", "); 348 349 if (acpi) 350 seq_puts(s, "ACPI"); 351 seq_puts(s, "]"); 352 } 353 } 354 355 static const struct pinctrl_ops intel_pinctrl_ops = { 356 .get_groups_count = intel_get_groups_count, 357 .get_group_name = intel_get_group_name, 358 .get_group_pins = intel_get_group_pins, 359 .pin_dbg_show = intel_pin_dbg_show, 360 }; 361 362 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 363 { 364 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 365 366 return pctrl->soc->nfunctions; 367 } 368 369 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 370 unsigned int function) 371 { 372 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 373 374 return pctrl->soc->functions[function].func.name; 375 } 376 377 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 378 unsigned int function, 379 const char * const **groups, 380 unsigned int * const ngroups) 381 { 382 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 383 384 *groups = pctrl->soc->functions[function].func.groups; 385 *ngroups = pctrl->soc->functions[function].func.ngroups; 386 return 0; 387 } 388 389 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, 390 unsigned int function, unsigned int group) 391 { 392 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 393 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 394 unsigned long flags; 395 int i; 396 397 raw_spin_lock_irqsave(&pctrl->lock, flags); 398 399 /* 400 * All pins in the groups needs to be accessible and writable 401 * before we can enable the mux for this group. 402 */ 403 for (i = 0; i < grp->grp.npins; i++) { 404 if (!intel_pad_usable(pctrl, grp->grp.pins[i])) { 405 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 406 return -EBUSY; 407 } 408 } 409 410 /* Now enable the mux setting for each pin in the group */ 411 for (i = 0; i < grp->grp.npins; i++) { 412 void __iomem *padcfg0; 413 u32 value, pmode; 414 415 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0); 416 417 value = readl(padcfg0); 418 value &= ~PADCFG0_PMODE_MASK; 419 420 if (grp->modes) 421 pmode = grp->modes[i]; 422 else 423 pmode = grp->mode; 424 425 value |= pmode << PADCFG0_PMODE_SHIFT; 426 writel(value, padcfg0); 427 } 428 429 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 430 431 return 0; 432 } 433 434 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) 435 { 436 u32 value; 437 438 value = readl(padcfg0); 439 if (input) { 440 value &= ~PADCFG0_GPIORXDIS; 441 value |= PADCFG0_GPIOTXDIS; 442 } else { 443 value &= ~PADCFG0_GPIOTXDIS; 444 value |= PADCFG0_GPIORXDIS; 445 } 446 writel(value, padcfg0); 447 } 448 449 static int __intel_gpio_get_gpio_mode(u32 value) 450 { 451 return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 452 } 453 454 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) 455 { 456 return __intel_gpio_get_gpio_mode(readl(padcfg0)); 457 } 458 459 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) 460 { 461 u32 value; 462 463 value = readl(padcfg0); 464 465 /* Put the pad into GPIO mode */ 466 value &= ~PADCFG0_PMODE_MASK; 467 value |= PADCFG0_PMODE_GPIO; 468 469 /* Disable TX buffer and enable RX (this will be input) */ 470 value &= ~PADCFG0_GPIORXDIS; 471 value |= PADCFG0_GPIOTXDIS; 472 473 /* Disable SCI/SMI/NMI generation */ 474 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 475 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 476 477 writel(value, padcfg0); 478 } 479 480 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 481 struct pinctrl_gpio_range *range, 482 unsigned int pin) 483 { 484 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 485 void __iomem *padcfg0; 486 unsigned long flags; 487 488 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 489 490 raw_spin_lock_irqsave(&pctrl->lock, flags); 491 492 if (!intel_pad_owned_by_host(pctrl, pin)) { 493 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 494 return -EBUSY; 495 } 496 497 if (!intel_pad_is_unlocked(pctrl, pin)) { 498 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 499 return 0; 500 } 501 502 /* 503 * If pin is already configured in GPIO mode, we assume that 504 * firmware provides correct settings. In such case we avoid 505 * potential glitches on the pin. Otherwise, for the pin in 506 * alternative mode, consumer has to supply respective flags. 507 */ 508 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) { 509 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 510 return 0; 511 } 512 513 intel_gpio_set_gpio_mode(padcfg0); 514 515 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 516 517 return 0; 518 } 519 520 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 521 struct pinctrl_gpio_range *range, 522 unsigned int pin, bool input) 523 { 524 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 525 void __iomem *padcfg0; 526 unsigned long flags; 527 528 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 529 530 raw_spin_lock_irqsave(&pctrl->lock, flags); 531 __intel_gpio_set_direction(padcfg0, input); 532 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 533 534 return 0; 535 } 536 537 static const struct pinmux_ops intel_pinmux_ops = { 538 .get_functions_count = intel_get_functions_count, 539 .get_function_name = intel_get_function_name, 540 .get_function_groups = intel_get_function_groups, 541 .set_mux = intel_pinmux_set_mux, 542 .gpio_request_enable = intel_gpio_request_enable, 543 .gpio_set_direction = intel_gpio_set_direction, 544 }; 545 546 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin, 547 enum pin_config_param param, u32 *arg) 548 { 549 const struct intel_community *community; 550 void __iomem *padcfg1; 551 unsigned long flags; 552 u32 value, term; 553 554 community = intel_get_community(pctrl, pin); 555 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 556 557 raw_spin_lock_irqsave(&pctrl->lock, flags); 558 value = readl(padcfg1); 559 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 560 561 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 562 563 switch (param) { 564 case PIN_CONFIG_BIAS_DISABLE: 565 if (term) 566 return -EINVAL; 567 break; 568 569 case PIN_CONFIG_BIAS_PULL_UP: 570 if (!term || !(value & PADCFG1_TERM_UP)) 571 return -EINVAL; 572 573 switch (term) { 574 case PADCFG1_TERM_833: 575 *arg = 833; 576 break; 577 case PADCFG1_TERM_1K: 578 *arg = 1000; 579 break; 580 case PADCFG1_TERM_4K: 581 *arg = 4000; 582 break; 583 case PADCFG1_TERM_5K: 584 *arg = 5000; 585 break; 586 case PADCFG1_TERM_20K: 587 *arg = 20000; 588 break; 589 } 590 591 break; 592 593 case PIN_CONFIG_BIAS_PULL_DOWN: 594 if (!term || value & PADCFG1_TERM_UP) 595 return -EINVAL; 596 597 switch (term) { 598 case PADCFG1_TERM_833: 599 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 600 return -EINVAL; 601 *arg = 833; 602 break; 603 case PADCFG1_TERM_1K: 604 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 605 return -EINVAL; 606 *arg = 1000; 607 break; 608 case PADCFG1_TERM_4K: 609 *arg = 4000; 610 break; 611 case PADCFG1_TERM_5K: 612 *arg = 5000; 613 break; 614 case PADCFG1_TERM_20K: 615 *arg = 20000; 616 break; 617 } 618 619 break; 620 621 default: 622 return -EINVAL; 623 } 624 625 return 0; 626 } 627 628 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin, 629 enum pin_config_param param, u32 *arg) 630 { 631 void __iomem *padcfg2; 632 unsigned long flags; 633 unsigned long v; 634 u32 value2; 635 636 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 637 if (!padcfg2) 638 return -ENOTSUPP; 639 640 raw_spin_lock_irqsave(&pctrl->lock, flags); 641 value2 = readl(padcfg2); 642 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 643 if (!(value2 & PADCFG2_DEBEN)) 644 return -EINVAL; 645 646 v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; 647 *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC; 648 649 return 0; 650 } 651 652 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 653 unsigned long *config) 654 { 655 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 656 enum pin_config_param param = pinconf_to_config_param(*config); 657 u32 arg = 0; 658 int ret; 659 660 if (!intel_pad_owned_by_host(pctrl, pin)) 661 return -ENOTSUPP; 662 663 switch (param) { 664 case PIN_CONFIG_BIAS_DISABLE: 665 case PIN_CONFIG_BIAS_PULL_UP: 666 case PIN_CONFIG_BIAS_PULL_DOWN: 667 ret = intel_config_get_pull(pctrl, pin, param, &arg); 668 if (ret) 669 return ret; 670 break; 671 672 case PIN_CONFIG_INPUT_DEBOUNCE: 673 ret = intel_config_get_debounce(pctrl, pin, param, &arg); 674 if (ret) 675 return ret; 676 break; 677 678 default: 679 return -ENOTSUPP; 680 } 681 682 *config = pinconf_to_config_packed(param, arg); 683 return 0; 684 } 685 686 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 687 unsigned long config) 688 { 689 unsigned int param = pinconf_to_config_param(config); 690 unsigned int arg = pinconf_to_config_argument(config); 691 const struct intel_community *community; 692 void __iomem *padcfg1; 693 unsigned long flags; 694 int ret = 0; 695 u32 value; 696 697 community = intel_get_community(pctrl, pin); 698 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 699 700 raw_spin_lock_irqsave(&pctrl->lock, flags); 701 702 value = readl(padcfg1); 703 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 704 705 /* Set default strength value in case none is given */ 706 if (arg == 1) 707 arg = 5000; 708 709 switch (param) { 710 case PIN_CONFIG_BIAS_DISABLE: 711 break; 712 713 case PIN_CONFIG_BIAS_PULL_UP: 714 switch (arg) { 715 case 20000: 716 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 717 break; 718 case 5000: 719 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 720 break; 721 case 4000: 722 value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT; 723 break; 724 case 1000: 725 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 726 break; 727 case 833: 728 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; 729 break; 730 default: 731 ret = -EINVAL; 732 break; 733 } 734 735 value |= PADCFG1_TERM_UP; 736 break; 737 738 case PIN_CONFIG_BIAS_PULL_DOWN: 739 switch (arg) { 740 case 20000: 741 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 742 break; 743 case 5000: 744 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 745 break; 746 case 4000: 747 value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT; 748 break; 749 case 1000: 750 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 751 ret = -EINVAL; 752 break; 753 } 754 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 755 break; 756 case 833: 757 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 758 ret = -EINVAL; 759 break; 760 } 761 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; 762 break; 763 default: 764 ret = -EINVAL; 765 break; 766 } 767 768 break; 769 770 default: 771 ret = -EINVAL; 772 break; 773 } 774 775 if (!ret) 776 writel(value, padcfg1); 777 778 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 779 780 return ret; 781 } 782 783 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, 784 unsigned int pin, unsigned int debounce) 785 { 786 void __iomem *padcfg0, *padcfg2; 787 unsigned long flags; 788 u32 value0, value2; 789 790 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 791 if (!padcfg2) 792 return -ENOTSUPP; 793 794 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 795 796 raw_spin_lock_irqsave(&pctrl->lock, flags); 797 798 value0 = readl(padcfg0); 799 value2 = readl(padcfg2); 800 801 /* Disable glitch filter and debouncer */ 802 value0 &= ~PADCFG0_PREGFRXSEL; 803 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); 804 805 if (debounce) { 806 unsigned long v; 807 808 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC); 809 if (v < 3 || v > 15) { 810 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 811 return -EINVAL; 812 } 813 814 /* Enable glitch filter and debouncer */ 815 value0 |= PADCFG0_PREGFRXSEL; 816 value2 |= v << PADCFG2_DEBOUNCE_SHIFT; 817 value2 |= PADCFG2_DEBEN; 818 } 819 820 writel(value0, padcfg0); 821 writel(value2, padcfg2); 822 823 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 824 825 return 0; 826 } 827 828 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 829 unsigned long *configs, unsigned int nconfigs) 830 { 831 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 832 int i, ret; 833 834 if (!intel_pad_usable(pctrl, pin)) 835 return -ENOTSUPP; 836 837 for (i = 0; i < nconfigs; i++) { 838 switch (pinconf_to_config_param(configs[i])) { 839 case PIN_CONFIG_BIAS_DISABLE: 840 case PIN_CONFIG_BIAS_PULL_UP: 841 case PIN_CONFIG_BIAS_PULL_DOWN: 842 ret = intel_config_set_pull(pctrl, pin, configs[i]); 843 if (ret) 844 return ret; 845 break; 846 847 case PIN_CONFIG_INPUT_DEBOUNCE: 848 ret = intel_config_set_debounce(pctrl, pin, 849 pinconf_to_config_argument(configs[i])); 850 if (ret) 851 return ret; 852 break; 853 854 default: 855 return -ENOTSUPP; 856 } 857 } 858 859 return 0; 860 } 861 862 static const struct pinconf_ops intel_pinconf_ops = { 863 .is_generic = true, 864 .pin_config_get = intel_config_get, 865 .pin_config_set = intel_config_set, 866 }; 867 868 static const struct pinctrl_desc intel_pinctrl_desc = { 869 .pctlops = &intel_pinctrl_ops, 870 .pmxops = &intel_pinmux_ops, 871 .confops = &intel_pinconf_ops, 872 .owner = THIS_MODULE, 873 }; 874 875 /** 876 * intel_gpio_to_pin() - Translate from GPIO offset to pin number 877 * @pctrl: Pinctrl structure 878 * @offset: GPIO offset from gpiolib 879 * @community: Community is filled here if not %NULL 880 * @padgrp: Pad group is filled here if not %NULL 881 * 882 * When coming through gpiolib irqchip, the GPIO offset is not 883 * automatically translated to pinctrl pin number. This function can be 884 * used to find out the corresponding pinctrl pin. 885 * 886 * Return: a pin number and pointers to the community and pad group, which 887 * the pin belongs to, or negative error code if translation can't be done. 888 */ 889 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, 890 const struct intel_community **community, 891 const struct intel_padgroup **padgrp) 892 { 893 int i; 894 895 for (i = 0; i < pctrl->ncommunities; i++) { 896 const struct intel_community *comm = &pctrl->communities[i]; 897 int j; 898 899 for (j = 0; j < comm->ngpps; j++) { 900 const struct intel_padgroup *pgrp = &comm->gpps[j]; 901 902 if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 903 continue; 904 905 if (offset >= pgrp->gpio_base && 906 offset < pgrp->gpio_base + pgrp->size) { 907 int pin; 908 909 pin = pgrp->base + offset - pgrp->gpio_base; 910 if (community) 911 *community = comm; 912 if (padgrp) 913 *padgrp = pgrp; 914 915 return pin; 916 } 917 } 918 } 919 920 return -EINVAL; 921 } 922 923 /** 924 * intel_pin_to_gpio() - Translate from pin number to GPIO offset 925 * @pctrl: Pinctrl structure 926 * @pin: pin number 927 * 928 * Translate the pin number of pinctrl to GPIO offset 929 * 930 * Return: a GPIO offset, or negative error code if translation can't be done. 931 */ 932 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin) 933 { 934 const struct intel_community *community; 935 const struct intel_padgroup *padgrp; 936 937 community = intel_get_community(pctrl, pin); 938 if (!community) 939 return -EINVAL; 940 941 padgrp = intel_community_get_padgroup(community, pin); 942 if (!padgrp) 943 return -EINVAL; 944 945 return pin - padgrp->base + padgrp->gpio_base; 946 } 947 948 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) 949 { 950 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 951 void __iomem *reg; 952 u32 padcfg0; 953 int pin; 954 955 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 956 if (pin < 0) 957 return -EINVAL; 958 959 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 960 if (!reg) 961 return -EINVAL; 962 963 padcfg0 = readl(reg); 964 if (!(padcfg0 & PADCFG0_GPIOTXDIS)) 965 return !!(padcfg0 & PADCFG0_GPIOTXSTATE); 966 967 return !!(padcfg0 & PADCFG0_GPIORXSTATE); 968 } 969 970 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, 971 int value) 972 { 973 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 974 unsigned long flags; 975 void __iomem *reg; 976 u32 padcfg0; 977 int pin; 978 979 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 980 if (pin < 0) 981 return; 982 983 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 984 if (!reg) 985 return; 986 987 raw_spin_lock_irqsave(&pctrl->lock, flags); 988 padcfg0 = readl(reg); 989 if (value) 990 padcfg0 |= PADCFG0_GPIOTXSTATE; 991 else 992 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 993 writel(padcfg0, reg); 994 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 995 } 996 997 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 998 { 999 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1000 unsigned long flags; 1001 void __iomem *reg; 1002 u32 padcfg0; 1003 int pin; 1004 1005 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 1006 if (pin < 0) 1007 return -EINVAL; 1008 1009 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1010 if (!reg) 1011 return -EINVAL; 1012 1013 raw_spin_lock_irqsave(&pctrl->lock, flags); 1014 padcfg0 = readl(reg); 1015 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1016 if (padcfg0 & PADCFG0_PMODE_MASK) 1017 return -EINVAL; 1018 1019 if (padcfg0 & PADCFG0_GPIOTXDIS) 1020 return GPIO_LINE_DIRECTION_IN; 1021 1022 return GPIO_LINE_DIRECTION_OUT; 1023 } 1024 1025 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1026 { 1027 return pinctrl_gpio_direction_input(chip->base + offset); 1028 } 1029 1030 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 1031 int value) 1032 { 1033 intel_gpio_set(chip, offset, value); 1034 return pinctrl_gpio_direction_output(chip->base + offset); 1035 } 1036 1037 static const struct gpio_chip intel_gpio_chip = { 1038 .owner = THIS_MODULE, 1039 .request = gpiochip_generic_request, 1040 .free = gpiochip_generic_free, 1041 .get_direction = intel_gpio_get_direction, 1042 .direction_input = intel_gpio_direction_input, 1043 .direction_output = intel_gpio_direction_output, 1044 .get = intel_gpio_get, 1045 .set = intel_gpio_set, 1046 .set_config = gpiochip_generic_config, 1047 }; 1048 1049 static void intel_gpio_irq_ack(struct irq_data *d) 1050 { 1051 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1052 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1053 const struct intel_community *community; 1054 const struct intel_padgroup *padgrp; 1055 int pin; 1056 1057 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 1058 if (pin >= 0) { 1059 unsigned int gpp, gpp_offset, is_offset; 1060 1061 gpp = padgrp->reg_num; 1062 gpp_offset = padgroup_offset(padgrp, pin); 1063 is_offset = community->is_offset + gpp * 4; 1064 1065 raw_spin_lock(&pctrl->lock); 1066 writel(BIT(gpp_offset), community->regs + is_offset); 1067 raw_spin_unlock(&pctrl->lock); 1068 } 1069 } 1070 1071 static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) 1072 { 1073 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1074 const struct intel_community *community; 1075 const struct intel_padgroup *padgrp; 1076 int pin; 1077 1078 pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp); 1079 if (pin >= 0) { 1080 unsigned int gpp, gpp_offset; 1081 unsigned long flags; 1082 void __iomem *reg, *is; 1083 u32 value; 1084 1085 gpp = padgrp->reg_num; 1086 gpp_offset = padgroup_offset(padgrp, pin); 1087 1088 reg = community->regs + community->ie_offset + gpp * 4; 1089 is = community->regs + community->is_offset + gpp * 4; 1090 1091 raw_spin_lock_irqsave(&pctrl->lock, flags); 1092 1093 /* Clear interrupt status first to avoid unexpected interrupt */ 1094 writel(BIT(gpp_offset), is); 1095 1096 value = readl(reg); 1097 if (mask) 1098 value &= ~BIT(gpp_offset); 1099 else 1100 value |= BIT(gpp_offset); 1101 writel(value, reg); 1102 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1103 } 1104 } 1105 1106 static void intel_gpio_irq_mask(struct irq_data *d) 1107 { 1108 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1109 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1110 1111 intel_gpio_irq_mask_unmask(gc, hwirq, true); 1112 gpiochip_disable_irq(gc, hwirq); 1113 } 1114 1115 static void intel_gpio_irq_unmask(struct irq_data *d) 1116 { 1117 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1118 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1119 1120 gpiochip_enable_irq(gc, hwirq); 1121 intel_gpio_irq_mask_unmask(gc, hwirq, false); 1122 } 1123 1124 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) 1125 { 1126 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1127 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1128 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1129 u32 rxevcfg, rxinv, value; 1130 unsigned long flags; 1131 void __iomem *reg; 1132 1133 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1134 if (!reg) 1135 return -EINVAL; 1136 1137 /* 1138 * If the pin is in ACPI mode it is still usable as a GPIO but it 1139 * cannot be used as IRQ because GPI_IS status bit will not be 1140 * updated by the host controller hardware. 1141 */ 1142 if (intel_pad_acpi_mode(pctrl, pin)) { 1143 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 1144 return -EPERM; 1145 } 1146 1147 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 1148 rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH; 1149 } else if (type & IRQ_TYPE_EDGE_FALLING) { 1150 rxevcfg = PADCFG0_RXEVCFG_EDGE; 1151 } else if (type & IRQ_TYPE_EDGE_RISING) { 1152 rxevcfg = PADCFG0_RXEVCFG_EDGE; 1153 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1154 rxevcfg = PADCFG0_RXEVCFG_LEVEL; 1155 } else { 1156 rxevcfg = PADCFG0_RXEVCFG_DISABLED; 1157 } 1158 1159 if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) 1160 rxinv = PADCFG0_RXINV; 1161 else 1162 rxinv = 0; 1163 1164 raw_spin_lock_irqsave(&pctrl->lock, flags); 1165 1166 intel_gpio_set_gpio_mode(reg); 1167 1168 value = readl(reg); 1169 1170 value = (value & ~PADCFG0_RXEVCFG_MASK) | rxevcfg; 1171 value = (value & ~PADCFG0_RXINV) | rxinv; 1172 1173 writel(value, reg); 1174 1175 if (type & IRQ_TYPE_EDGE_BOTH) 1176 irq_set_handler_locked(d, handle_edge_irq); 1177 else if (type & IRQ_TYPE_LEVEL_MASK) 1178 irq_set_handler_locked(d, handle_level_irq); 1179 1180 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1181 1182 return 0; 1183 } 1184 1185 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 1186 { 1187 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1188 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1189 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1190 1191 if (on) 1192 enable_irq_wake(pctrl->irq); 1193 else 1194 disable_irq_wake(pctrl->irq); 1195 1196 dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin); 1197 return 0; 1198 } 1199 1200 static const struct irq_chip intel_gpio_irq_chip = { 1201 .name = "intel-gpio", 1202 .irq_ack = intel_gpio_irq_ack, 1203 .irq_mask = intel_gpio_irq_mask, 1204 .irq_unmask = intel_gpio_irq_unmask, 1205 .irq_set_type = intel_gpio_irq_type, 1206 .irq_set_wake = intel_gpio_irq_wake, 1207 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 1208 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1209 }; 1210 1211 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 1212 const struct intel_community *community) 1213 { 1214 struct gpio_chip *gc = &pctrl->chip; 1215 unsigned int gpp; 1216 int ret = 0; 1217 1218 for (gpp = 0; gpp < community->ngpps; gpp++) { 1219 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1220 unsigned long pending, enabled, gpp_offset; 1221 1222 raw_spin_lock(&pctrl->lock); 1223 1224 pending = readl(community->regs + community->is_offset + 1225 padgrp->reg_num * 4); 1226 enabled = readl(community->regs + community->ie_offset + 1227 padgrp->reg_num * 4); 1228 1229 raw_spin_unlock(&pctrl->lock); 1230 1231 /* Only interrupts that are enabled */ 1232 pending &= enabled; 1233 1234 for_each_set_bit(gpp_offset, &pending, padgrp->size) 1235 generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset); 1236 1237 ret += pending ? 1 : 0; 1238 } 1239 1240 return ret; 1241 } 1242 1243 static irqreturn_t intel_gpio_irq(int irq, void *data) 1244 { 1245 const struct intel_community *community; 1246 struct intel_pinctrl *pctrl = data; 1247 unsigned int i; 1248 int ret = 0; 1249 1250 /* Need to check all communities for pending interrupts */ 1251 for (i = 0; i < pctrl->ncommunities; i++) { 1252 community = &pctrl->communities[i]; 1253 ret += intel_gpio_community_irq_handler(pctrl, community); 1254 } 1255 1256 return IRQ_RETVAL(ret); 1257 } 1258 1259 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1260 { 1261 int i; 1262 1263 for (i = 0; i < pctrl->ncommunities; i++) { 1264 const struct intel_community *community; 1265 void __iomem *base; 1266 unsigned int gpp; 1267 1268 community = &pctrl->communities[i]; 1269 base = community->regs; 1270 1271 for (gpp = 0; gpp < community->ngpps; gpp++) { 1272 /* Mask and clear all interrupts */ 1273 writel(0, base + community->ie_offset + gpp * 4); 1274 writel(0xffff, base + community->is_offset + gpp * 4); 1275 } 1276 } 1277 } 1278 1279 static int intel_gpio_irq_init_hw(struct gpio_chip *gc) 1280 { 1281 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1282 1283 /* 1284 * Make sure the interrupt lines are in a proper state before 1285 * further configuration. 1286 */ 1287 intel_gpio_irq_init(pctrl); 1288 1289 return 0; 1290 } 1291 1292 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl, 1293 const struct intel_community *community) 1294 { 1295 int ret = 0, i; 1296 1297 for (i = 0; i < community->ngpps; i++) { 1298 const struct intel_padgroup *gpp = &community->gpps[i]; 1299 1300 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1301 continue; 1302 1303 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1304 gpp->gpio_base, gpp->base, 1305 gpp->size); 1306 if (ret) 1307 return ret; 1308 } 1309 1310 return ret; 1311 } 1312 1313 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) 1314 { 1315 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1316 int ret, i; 1317 1318 for (i = 0; i < pctrl->ncommunities; i++) { 1319 struct intel_community *community = &pctrl->communities[i]; 1320 1321 ret = intel_gpio_add_community_ranges(pctrl, community); 1322 if (ret) { 1323 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1324 return ret; 1325 } 1326 } 1327 1328 return 0; 1329 } 1330 1331 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1332 { 1333 const struct intel_community *community; 1334 unsigned int ngpio = 0; 1335 int i, j; 1336 1337 for (i = 0; i < pctrl->ncommunities; i++) { 1338 community = &pctrl->communities[i]; 1339 for (j = 0; j < community->ngpps; j++) { 1340 const struct intel_padgroup *gpp = &community->gpps[j]; 1341 1342 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1343 continue; 1344 1345 if (gpp->gpio_base + gpp->size > ngpio) 1346 ngpio = gpp->gpio_base + gpp->size; 1347 } 1348 } 1349 1350 return ngpio; 1351 } 1352 1353 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1354 { 1355 int ret; 1356 struct gpio_irq_chip *girq; 1357 1358 pctrl->chip = intel_gpio_chip; 1359 1360 /* Setup GPIO chip */ 1361 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); 1362 pctrl->chip.label = dev_name(pctrl->dev); 1363 pctrl->chip.parent = pctrl->dev; 1364 pctrl->chip.base = -1; 1365 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; 1366 pctrl->irq = irq; 1367 1368 /* 1369 * On some platforms several GPIO controllers share the same interrupt 1370 * line. 1371 */ 1372 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1373 IRQF_SHARED | IRQF_NO_THREAD, 1374 dev_name(pctrl->dev), pctrl); 1375 if (ret) { 1376 dev_err(pctrl->dev, "failed to request interrupt\n"); 1377 return ret; 1378 } 1379 1380 /* Setup IRQ chip */ 1381 girq = &pctrl->chip.irq; 1382 gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip); 1383 /* This will let us handle the IRQ in the driver */ 1384 girq->parent_handler = NULL; 1385 girq->num_parents = 0; 1386 girq->default_type = IRQ_TYPE_NONE; 1387 girq->handler = handle_bad_irq; 1388 girq->init_hw = intel_gpio_irq_init_hw; 1389 1390 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1391 if (ret) { 1392 dev_err(pctrl->dev, "failed to register gpiochip\n"); 1393 return ret; 1394 } 1395 1396 return 0; 1397 } 1398 1399 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl, 1400 struct intel_community *community) 1401 { 1402 struct intel_padgroup *gpps; 1403 unsigned int padown_num = 0; 1404 size_t i, ngpps = community->ngpps; 1405 1406 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1407 if (!gpps) 1408 return -ENOMEM; 1409 1410 for (i = 0; i < ngpps; i++) { 1411 gpps[i] = community->gpps[i]; 1412 1413 if (gpps[i].size > INTEL_PINCTRL_MAX_GPP_SIZE) 1414 return -EINVAL; 1415 1416 /* Special treatment for GPIO base */ 1417 switch (gpps[i].gpio_base) { 1418 case INTEL_GPIO_BASE_MATCH: 1419 gpps[i].gpio_base = gpps[i].base; 1420 break; 1421 case INTEL_GPIO_BASE_ZERO: 1422 gpps[i].gpio_base = 0; 1423 break; 1424 case INTEL_GPIO_BASE_NOMAP: 1425 break; 1426 default: 1427 break; 1428 } 1429 1430 gpps[i].padown_num = padown_num; 1431 padown_num += DIV_ROUND_UP(gpps[i].size * 4, INTEL_PINCTRL_MAX_GPP_SIZE); 1432 } 1433 1434 community->gpps = gpps; 1435 1436 return 0; 1437 } 1438 1439 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl, 1440 struct intel_community *community) 1441 { 1442 struct intel_padgroup *gpps; 1443 unsigned int npins = community->npins; 1444 unsigned int padown_num = 0; 1445 size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size); 1446 1447 if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE) 1448 return -EINVAL; 1449 1450 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1451 if (!gpps) 1452 return -ENOMEM; 1453 1454 for (i = 0; i < ngpps; i++) { 1455 unsigned int gpp_size = community->gpp_size; 1456 1457 gpps[i].reg_num = i; 1458 gpps[i].base = community->pin_base + i * gpp_size; 1459 gpps[i].size = min(gpp_size, npins); 1460 npins -= gpps[i].size; 1461 1462 gpps[i].gpio_base = gpps[i].base; 1463 gpps[i].padown_num = padown_num; 1464 1465 padown_num += community->gpp_num_padown_regs; 1466 } 1467 1468 community->ngpps = ngpps; 1469 community->gpps = gpps; 1470 1471 return 0; 1472 } 1473 1474 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 1475 { 1476 #ifdef CONFIG_PM_SLEEP 1477 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 1478 struct intel_community_context *communities; 1479 struct intel_pad_context *pads; 1480 int i; 1481 1482 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 1483 if (!pads) 1484 return -ENOMEM; 1485 1486 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 1487 sizeof(*communities), GFP_KERNEL); 1488 if (!communities) 1489 return -ENOMEM; 1490 1491 1492 for (i = 0; i < pctrl->ncommunities; i++) { 1493 struct intel_community *community = &pctrl->communities[i]; 1494 u32 *intmask, *hostown; 1495 1496 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1497 sizeof(*intmask), GFP_KERNEL); 1498 if (!intmask) 1499 return -ENOMEM; 1500 1501 communities[i].intmask = intmask; 1502 1503 hostown = devm_kcalloc(pctrl->dev, community->ngpps, 1504 sizeof(*hostown), GFP_KERNEL); 1505 if (!hostown) 1506 return -ENOMEM; 1507 1508 communities[i].hostown = hostown; 1509 } 1510 1511 pctrl->context.pads = pads; 1512 pctrl->context.communities = communities; 1513 #endif 1514 1515 return 0; 1516 } 1517 1518 static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, 1519 struct intel_community *community) 1520 { 1521 static const struct pwm_lpss_boardinfo info = { 1522 .clk_rate = 19200000, 1523 .npwm = 1, 1524 .base_unit_bits = 22, 1525 .bypass = true, 1526 }; 1527 struct pwm_lpss_chip *pwm; 1528 1529 if (!(community->features & PINCTRL_FEATURE_PWM)) 1530 return 0; 1531 1532 if (!IS_REACHABLE(CONFIG_PWM_LPSS)) 1533 return 0; 1534 1535 pwm = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); 1536 return PTR_ERR_OR_ZERO(pwm); 1537 } 1538 1539 static int intel_pinctrl_probe(struct platform_device *pdev, 1540 const struct intel_pinctrl_soc_data *soc_data) 1541 { 1542 struct device *dev = &pdev->dev; 1543 struct intel_pinctrl *pctrl; 1544 int i, ret, irq; 1545 1546 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 1547 if (!pctrl) 1548 return -ENOMEM; 1549 1550 pctrl->dev = dev; 1551 pctrl->soc = soc_data; 1552 raw_spin_lock_init(&pctrl->lock); 1553 1554 /* 1555 * Make a copy of the communities which we can use to hold pointers 1556 * to the registers. 1557 */ 1558 pctrl->ncommunities = pctrl->soc->ncommunities; 1559 pctrl->communities = devm_kcalloc(dev, pctrl->ncommunities, 1560 sizeof(*pctrl->communities), GFP_KERNEL); 1561 if (!pctrl->communities) 1562 return -ENOMEM; 1563 1564 for (i = 0; i < pctrl->ncommunities; i++) { 1565 struct intel_community *community = &pctrl->communities[i]; 1566 void __iomem *regs; 1567 u32 offset; 1568 u32 value; 1569 1570 *community = pctrl->soc->communities[i]; 1571 1572 regs = devm_platform_ioremap_resource(pdev, community->barno); 1573 if (IS_ERR(regs)) 1574 return PTR_ERR(regs); 1575 1576 /* 1577 * Determine community features based on the revision. 1578 * A value of all ones means the device is not present. 1579 */ 1580 value = readl(regs + REVID); 1581 if (value == ~0u) 1582 return -ENODEV; 1583 if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) { 1584 community->features |= PINCTRL_FEATURE_DEBOUNCE; 1585 community->features |= PINCTRL_FEATURE_1K_PD; 1586 } 1587 1588 /* Determine community features based on the capabilities */ 1589 offset = CAPLIST; 1590 do { 1591 value = readl(regs + offset); 1592 switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) { 1593 case CAPLIST_ID_GPIO_HW_INFO: 1594 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO; 1595 break; 1596 case CAPLIST_ID_PWM: 1597 community->features |= PINCTRL_FEATURE_PWM; 1598 break; 1599 case CAPLIST_ID_BLINK: 1600 community->features |= PINCTRL_FEATURE_BLINK; 1601 break; 1602 case CAPLIST_ID_EXP: 1603 community->features |= PINCTRL_FEATURE_EXP; 1604 break; 1605 default: 1606 break; 1607 } 1608 offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT; 1609 } while (offset); 1610 1611 dev_dbg(dev, "Community%d features: %#08x\n", i, community->features); 1612 1613 /* Read offset of the pad configuration registers */ 1614 offset = readl(regs + PADBAR); 1615 1616 community->regs = regs; 1617 community->pad_regs = regs + offset; 1618 1619 if (community->gpps) 1620 ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community); 1621 else 1622 ret = intel_pinctrl_add_padgroups_by_size(pctrl, community); 1623 if (ret) 1624 return ret; 1625 1626 ret = intel_pinctrl_probe_pwm(pctrl, community); 1627 if (ret) 1628 return ret; 1629 } 1630 1631 irq = platform_get_irq(pdev, 0); 1632 if (irq < 0) 1633 return irq; 1634 1635 ret = intel_pinctrl_pm_init(pctrl); 1636 if (ret) 1637 return ret; 1638 1639 pctrl->pctldesc = intel_pinctrl_desc; 1640 pctrl->pctldesc.name = dev_name(dev); 1641 pctrl->pctldesc.pins = pctrl->soc->pins; 1642 pctrl->pctldesc.npins = pctrl->soc->npins; 1643 1644 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); 1645 if (IS_ERR(pctrl->pctldev)) { 1646 dev_err(dev, "failed to register pinctrl driver\n"); 1647 return PTR_ERR(pctrl->pctldev); 1648 } 1649 1650 ret = intel_gpio_probe(pctrl, irq); 1651 if (ret) 1652 return ret; 1653 1654 platform_set_drvdata(pdev, pctrl); 1655 1656 return 0; 1657 } 1658 1659 int intel_pinctrl_probe_by_hid(struct platform_device *pdev) 1660 { 1661 const struct intel_pinctrl_soc_data *data; 1662 1663 data = device_get_match_data(&pdev->dev); 1664 if (!data) 1665 return -ENODATA; 1666 1667 return intel_pinctrl_probe(pdev, data); 1668 } 1669 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); 1670 1671 int intel_pinctrl_probe_by_uid(struct platform_device *pdev) 1672 { 1673 const struct intel_pinctrl_soc_data *data; 1674 1675 data = intel_pinctrl_get_soc_data(pdev); 1676 if (IS_ERR(data)) 1677 return PTR_ERR(data); 1678 1679 return intel_pinctrl_probe(pdev, data); 1680 } 1681 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); 1682 1683 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) 1684 { 1685 const struct intel_pinctrl_soc_data * const *table; 1686 const struct intel_pinctrl_soc_data *data = NULL; 1687 struct device *dev = &pdev->dev; 1688 1689 table = device_get_match_data(dev); 1690 if (table) { 1691 struct acpi_device *adev = ACPI_COMPANION(dev); 1692 unsigned int i; 1693 1694 for (i = 0; table[i]; i++) { 1695 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) { 1696 data = table[i]; 1697 break; 1698 } 1699 } 1700 } else { 1701 const struct platform_device_id *id; 1702 1703 id = platform_get_device_id(pdev); 1704 if (!id) 1705 return ERR_PTR(-ENODEV); 1706 1707 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data; 1708 data = table[pdev->id]; 1709 } 1710 1711 return data ?: ERR_PTR(-ENODATA); 1712 } 1713 EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data); 1714 1715 #ifdef CONFIG_PM_SLEEP 1716 static bool __intel_gpio_is_direct_irq(u32 value) 1717 { 1718 return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) && 1719 (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO); 1720 } 1721 1722 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) 1723 { 1724 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1725 u32 value; 1726 1727 if (!pd || !intel_pad_usable(pctrl, pin)) 1728 return false; 1729 1730 /* 1731 * Only restore the pin if it is actually in use by the kernel (or 1732 * by userspace). It is possible that some pins are used by the 1733 * BIOS during resume and those are not always locked down so leave 1734 * them alone. 1735 */ 1736 if (pd->mux_owner || pd->gpio_owner || 1737 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) 1738 return true; 1739 1740 /* 1741 * The firmware on some systems may configure GPIO pins to be 1742 * an interrupt source in so called "direct IRQ" mode. In such 1743 * cases the GPIO controller driver has no idea if those pins 1744 * are being used or not. At the same time, there is a known bug 1745 * in the firmwares that don't restore the pin settings correctly 1746 * after suspend, i.e. by an unknown reason the Rx value becomes 1747 * inverted. 1748 * 1749 * Hence, let's save and restore the pins that are configured 1750 * as GPIOs in the input mode with GPIROUTIOXAPIC bit set. 1751 * 1752 * See https://bugzilla.kernel.org/show_bug.cgi?id=214749. 1753 */ 1754 value = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 1755 if (__intel_gpio_is_direct_irq(value)) 1756 return true; 1757 1758 return false; 1759 } 1760 1761 int intel_pinctrl_suspend_noirq(struct device *dev) 1762 { 1763 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1764 struct intel_community_context *communities; 1765 struct intel_pad_context *pads; 1766 int i; 1767 1768 pads = pctrl->context.pads; 1769 for (i = 0; i < pctrl->soc->npins; i++) { 1770 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1771 void __iomem *padcfg; 1772 u32 val; 1773 1774 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1775 continue; 1776 1777 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1778 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1779 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1780 pads[i].padcfg1 = val; 1781 1782 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1783 if (padcfg) 1784 pads[i].padcfg2 = readl(padcfg); 1785 } 1786 1787 communities = pctrl->context.communities; 1788 for (i = 0; i < pctrl->ncommunities; i++) { 1789 struct intel_community *community = &pctrl->communities[i]; 1790 void __iomem *base; 1791 unsigned int gpp; 1792 1793 base = community->regs + community->ie_offset; 1794 for (gpp = 0; gpp < community->ngpps; gpp++) 1795 communities[i].intmask[gpp] = readl(base + gpp * 4); 1796 1797 base = community->regs + community->hostown_offset; 1798 for (gpp = 0; gpp < community->ngpps; gpp++) 1799 communities[i].hostown[gpp] = readl(base + gpp * 4); 1800 } 1801 1802 return 0; 1803 } 1804 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq); 1805 1806 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value) 1807 { 1808 u32 curr, updated; 1809 1810 curr = readl(reg); 1811 1812 updated = (curr & ~mask) | (value & mask); 1813 if (curr == updated) 1814 return false; 1815 1816 writel(updated, reg); 1817 return true; 1818 } 1819 1820 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, 1821 void __iomem *base, unsigned int gpp, u32 saved) 1822 { 1823 const struct intel_community *community = &pctrl->communities[c]; 1824 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1825 struct device *dev = pctrl->dev; 1826 const char *dummy; 1827 u32 requested = 0; 1828 unsigned int i; 1829 1830 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1831 return; 1832 1833 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy) 1834 requested |= BIT(i); 1835 1836 if (!intel_gpio_update_reg(base + gpp * 4, requested, saved)) 1837 return; 1838 1839 dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1840 } 1841 1842 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, 1843 void __iomem *base, unsigned int gpp, u32 saved) 1844 { 1845 struct device *dev = pctrl->dev; 1846 1847 if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved)) 1848 return; 1849 1850 dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1851 } 1852 1853 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, 1854 unsigned int reg, u32 saved) 1855 { 1856 u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0; 1857 unsigned int n = reg / sizeof(u32); 1858 struct device *dev = pctrl->dev; 1859 void __iomem *padcfg; 1860 1861 padcfg = intel_get_padcfg(pctrl, pin, reg); 1862 if (!padcfg) 1863 return; 1864 1865 if (!intel_gpio_update_reg(padcfg, ~mask, saved)) 1866 return; 1867 1868 dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg)); 1869 } 1870 1871 int intel_pinctrl_resume_noirq(struct device *dev) 1872 { 1873 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1874 const struct intel_community_context *communities; 1875 const struct intel_pad_context *pads; 1876 int i; 1877 1878 /* Mask all interrupts */ 1879 intel_gpio_irq_init(pctrl); 1880 1881 pads = pctrl->context.pads; 1882 for (i = 0; i < pctrl->soc->npins; i++) { 1883 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1884 1885 if (!(intel_pinctrl_should_save(pctrl, desc->number) || 1886 /* 1887 * If the firmware mangled the register contents too much, 1888 * check the saved value for the Direct IRQ mode. 1889 */ 1890 __intel_gpio_is_direct_irq(pads[i].padcfg0))) 1891 continue; 1892 1893 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); 1894 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); 1895 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); 1896 } 1897 1898 communities = pctrl->context.communities; 1899 for (i = 0; i < pctrl->ncommunities; i++) { 1900 struct intel_community *community = &pctrl->communities[i]; 1901 void __iomem *base; 1902 unsigned int gpp; 1903 1904 base = community->regs + community->ie_offset; 1905 for (gpp = 0; gpp < community->ngpps; gpp++) 1906 intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]); 1907 1908 base = community->regs + community->hostown_offset; 1909 for (gpp = 0; gpp < community->ngpps; gpp++) 1910 intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]); 1911 } 1912 1913 return 0; 1914 } 1915 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq); 1916 #endif 1917 1918 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1919 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1920 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1921 MODULE_LICENSE("GPL v2"); 1922