1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel pinctrl/GPIO core driver. 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/log2.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/seq_file.h> 18 #include <linux/string_helpers.h> 19 #include <linux/time.h> 20 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 27 #include <linux/platform_data/x86/pwm-lpss.h> 28 29 #include "../core.h" 30 #include "pinctrl-intel.h" 31 32 /* Offset from regs */ 33 #define REVID 0x000 34 #define REVID_SHIFT 16 35 #define REVID_MASK GENMASK(31, 16) 36 37 #define CAPLIST 0x004 38 #define CAPLIST_ID_SHIFT 16 39 #define CAPLIST_ID_MASK GENMASK(23, 16) 40 #define CAPLIST_ID_GPIO_HW_INFO 1 41 #define CAPLIST_ID_PWM 2 42 #define CAPLIST_ID_BLINK 3 43 #define CAPLIST_ID_EXP 4 44 #define CAPLIST_NEXT_SHIFT 0 45 #define CAPLIST_NEXT_MASK GENMASK(15, 0) 46 47 #define PADBAR 0x00c 48 49 #define PADOWN_BITS 4 50 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 51 #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) 52 #define PADOWN_GPP(p) ((p) / 8) 53 54 #define PWMC 0x204 55 56 /* Offset from pad_regs */ 57 #define PADCFG0 0x000 58 #define PADCFG0_RXEVCFG_SHIFT 25 59 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25) 60 #define PADCFG0_RXEVCFG_LEVEL 0 61 #define PADCFG0_RXEVCFG_EDGE 1 62 #define PADCFG0_RXEVCFG_DISABLED 2 63 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 64 #define PADCFG0_PREGFRXSEL BIT(24) 65 #define PADCFG0_RXINV BIT(23) 66 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 67 #define PADCFG0_GPIROUTSCI BIT(19) 68 #define PADCFG0_GPIROUTSMI BIT(18) 69 #define PADCFG0_GPIROUTNMI BIT(17) 70 #define PADCFG0_PMODE_SHIFT 10 71 #define PADCFG0_PMODE_MASK GENMASK(13, 10) 72 #define PADCFG0_PMODE_GPIO 0 73 #define PADCFG0_GPIORXDIS BIT(9) 74 #define PADCFG0_GPIOTXDIS BIT(8) 75 #define PADCFG0_GPIORXSTATE BIT(1) 76 #define PADCFG0_GPIOTXSTATE BIT(0) 77 78 #define PADCFG1 0x004 79 #define PADCFG1_TERM_UP BIT(13) 80 #define PADCFG1_TERM_SHIFT 10 81 #define PADCFG1_TERM_MASK GENMASK(12, 10) 82 #define PADCFG1_TERM_20K BIT(2) 83 #define PADCFG1_TERM_5K BIT(1) 84 #define PADCFG1_TERM_4K (BIT(2) | BIT(1)) 85 #define PADCFG1_TERM_1K BIT(0) 86 #define PADCFG1_TERM_952 (BIT(2) | BIT(0)) 87 #define PADCFG1_TERM_833 (BIT(1) | BIT(0)) 88 #define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0)) 89 90 #define PADCFG2 0x008 91 #define PADCFG2_DEBOUNCE_SHIFT 1 92 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) 93 #define PADCFG2_DEBEN BIT(0) 94 95 #define DEBOUNCE_PERIOD_NSEC 31250 96 97 struct intel_pad_context { 98 u32 padcfg0; 99 u32 padcfg1; 100 u32 padcfg2; 101 }; 102 103 struct intel_community_context { 104 u32 *intmask; 105 u32 *hostown; 106 }; 107 108 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 109 #define padgroup_offset(g, p) ((p) - (g)->base) 110 111 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 112 unsigned int pin) 113 { 114 struct intel_community *community; 115 int i; 116 117 for (i = 0; i < pctrl->ncommunities; i++) { 118 community = &pctrl->communities[i]; 119 if (pin >= community->pin_base && 120 pin < community->pin_base + community->npins) 121 return community; 122 } 123 124 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 125 return NULL; 126 } 127 128 static const struct intel_padgroup * 129 intel_community_get_padgroup(const struct intel_community *community, 130 unsigned int pin) 131 { 132 int i; 133 134 for (i = 0; i < community->ngpps; i++) { 135 const struct intel_padgroup *padgrp = &community->gpps[i]; 136 137 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) 138 return padgrp; 139 } 140 141 return NULL; 142 } 143 144 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, 145 unsigned int pin, unsigned int reg) 146 { 147 const struct intel_community *community; 148 unsigned int padno; 149 size_t nregs; 150 151 community = intel_get_community(pctrl, pin); 152 if (!community) 153 return NULL; 154 155 padno = pin_to_padno(community, pin); 156 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; 157 158 if (reg >= nregs * 4) 159 return NULL; 160 161 return community->pad_regs + reg + padno * nregs * 4; 162 } 163 164 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin) 165 { 166 const struct intel_community *community; 167 const struct intel_padgroup *padgrp; 168 unsigned int gpp, offset, gpp_offset; 169 void __iomem *padown; 170 171 community = intel_get_community(pctrl, pin); 172 if (!community) 173 return false; 174 if (!community->padown_offset) 175 return true; 176 177 padgrp = intel_community_get_padgroup(community, pin); 178 if (!padgrp) 179 return false; 180 181 gpp_offset = padgroup_offset(padgrp, pin); 182 gpp = PADOWN_GPP(gpp_offset); 183 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; 184 padown = community->regs + offset; 185 186 return !(readl(padown) & PADOWN_MASK(gpp_offset)); 187 } 188 189 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin) 190 { 191 const struct intel_community *community; 192 const struct intel_padgroup *padgrp; 193 unsigned int offset, gpp_offset; 194 void __iomem *hostown; 195 196 community = intel_get_community(pctrl, pin); 197 if (!community) 198 return true; 199 if (!community->hostown_offset) 200 return false; 201 202 padgrp = intel_community_get_padgroup(community, pin); 203 if (!padgrp) 204 return true; 205 206 gpp_offset = padgroup_offset(padgrp, pin); 207 offset = community->hostown_offset + padgrp->reg_num * 4; 208 hostown = community->regs + offset; 209 210 return !(readl(hostown) & BIT(gpp_offset)); 211 } 212 213 /** 214 * enum - Locking variants of the pad configuration 215 * 216 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers 217 * @PAD_LOCKED: pad configuration registers, except TX state, are locked 218 * @PAD_LOCKED_TX: pad configuration TX state is locked 219 * @PAD_LOCKED_FULL: pad configuration registers are locked completely 220 * 221 * Locking is considered as read-only mode for corresponding registers and 222 * their respective fields. That said, TX state bit is locked separately from 223 * the main locking scheme. 224 */ 225 enum { 226 PAD_UNLOCKED = 0, 227 PAD_LOCKED = 1, 228 PAD_LOCKED_TX = 2, 229 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX, 230 }; 231 232 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin) 233 { 234 struct intel_community *community; 235 const struct intel_padgroup *padgrp; 236 unsigned int offset, gpp_offset; 237 u32 value; 238 int ret = PAD_UNLOCKED; 239 240 community = intel_get_community(pctrl, pin); 241 if (!community) 242 return PAD_LOCKED_FULL; 243 if (!community->padcfglock_offset) 244 return PAD_UNLOCKED; 245 246 padgrp = intel_community_get_padgroup(community, pin); 247 if (!padgrp) 248 return PAD_LOCKED_FULL; 249 250 gpp_offset = padgroup_offset(padgrp, pin); 251 252 /* 253 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 254 * the pad is considered unlocked. Any other case means that it is 255 * either fully or partially locked. 256 */ 257 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; 258 value = readl(community->regs + offset); 259 if (value & BIT(gpp_offset)) 260 ret |= PAD_LOCKED; 261 262 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; 263 value = readl(community->regs + offset); 264 if (value & BIT(gpp_offset)) 265 ret |= PAD_LOCKED_TX; 266 267 return ret; 268 } 269 270 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin) 271 { 272 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED; 273 } 274 275 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) 276 { 277 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); 278 } 279 280 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 281 { 282 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 283 284 return pctrl->soc->ngroups; 285 } 286 287 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 288 unsigned int group) 289 { 290 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 291 292 return pctrl->soc->groups[group].grp.name; 293 } 294 295 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 296 const unsigned int **pins, unsigned int *npins) 297 { 298 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 299 300 *pins = pctrl->soc->groups[group].grp.pins; 301 *npins = pctrl->soc->groups[group].grp.npins; 302 return 0; 303 } 304 305 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 306 unsigned int pin) 307 { 308 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 309 void __iomem *padcfg; 310 u32 cfg0, cfg1, mode; 311 int locked; 312 bool acpi; 313 314 if (!intel_pad_owned_by_host(pctrl, pin)) { 315 seq_puts(s, "not available"); 316 return; 317 } 318 319 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 320 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 321 322 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 323 if (mode == PADCFG0_PMODE_GPIO) 324 seq_puts(s, "GPIO "); 325 else 326 seq_printf(s, "mode %d ", mode); 327 328 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 329 330 /* Dump the additional PADCFG registers if available */ 331 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); 332 if (padcfg) 333 seq_printf(s, " 0x%08x", readl(padcfg)); 334 335 locked = intel_pad_locked(pctrl, pin); 336 acpi = intel_pad_acpi_mode(pctrl, pin); 337 338 if (locked || acpi) { 339 seq_puts(s, " ["); 340 if (locked) 341 seq_puts(s, "LOCKED"); 342 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) 343 seq_puts(s, " tx"); 344 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) 345 seq_puts(s, " full"); 346 347 if (locked && acpi) 348 seq_puts(s, ", "); 349 350 if (acpi) 351 seq_puts(s, "ACPI"); 352 seq_puts(s, "]"); 353 } 354 } 355 356 static const struct pinctrl_ops intel_pinctrl_ops = { 357 .get_groups_count = intel_get_groups_count, 358 .get_group_name = intel_get_group_name, 359 .get_group_pins = intel_get_group_pins, 360 .pin_dbg_show = intel_pin_dbg_show, 361 }; 362 363 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 364 { 365 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 366 367 return pctrl->soc->nfunctions; 368 } 369 370 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 371 unsigned int function) 372 { 373 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 374 375 return pctrl->soc->functions[function].func.name; 376 } 377 378 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 379 unsigned int function, 380 const char * const **groups, 381 unsigned int * const ngroups) 382 { 383 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 384 385 *groups = pctrl->soc->functions[function].func.groups; 386 *ngroups = pctrl->soc->functions[function].func.ngroups; 387 return 0; 388 } 389 390 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, 391 unsigned int function, unsigned int group) 392 { 393 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 394 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 395 unsigned long flags; 396 int i; 397 398 raw_spin_lock_irqsave(&pctrl->lock, flags); 399 400 /* 401 * All pins in the groups needs to be accessible and writable 402 * before we can enable the mux for this group. 403 */ 404 for (i = 0; i < grp->grp.npins; i++) { 405 if (!intel_pad_usable(pctrl, grp->grp.pins[i])) { 406 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 407 return -EBUSY; 408 } 409 } 410 411 /* Now enable the mux setting for each pin in the group */ 412 for (i = 0; i < grp->grp.npins; i++) { 413 void __iomem *padcfg0; 414 u32 value; 415 416 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0); 417 value = readl(padcfg0); 418 419 value &= ~PADCFG0_PMODE_MASK; 420 421 if (grp->modes) 422 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; 423 else 424 value |= grp->mode << PADCFG0_PMODE_SHIFT; 425 426 writel(value, padcfg0); 427 } 428 429 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 430 431 return 0; 432 } 433 434 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) 435 { 436 u32 value; 437 438 value = readl(padcfg0); 439 if (input) { 440 value &= ~PADCFG0_GPIORXDIS; 441 value |= PADCFG0_GPIOTXDIS; 442 } else { 443 value &= ~PADCFG0_GPIOTXDIS; 444 value |= PADCFG0_GPIORXDIS; 445 } 446 writel(value, padcfg0); 447 } 448 449 static int __intel_gpio_get_gpio_mode(u32 value) 450 { 451 return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 452 } 453 454 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) 455 { 456 return __intel_gpio_get_gpio_mode(readl(padcfg0)); 457 } 458 459 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) 460 { 461 u32 value; 462 463 value = readl(padcfg0); 464 465 /* Put the pad into GPIO mode */ 466 value &= ~PADCFG0_PMODE_MASK; 467 value |= PADCFG0_PMODE_GPIO; 468 469 /* Disable TX buffer and enable RX (this will be input) */ 470 value &= ~PADCFG0_GPIORXDIS; 471 value |= PADCFG0_GPIOTXDIS; 472 473 /* Disable SCI/SMI/NMI generation */ 474 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 475 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 476 477 writel(value, padcfg0); 478 } 479 480 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 481 struct pinctrl_gpio_range *range, 482 unsigned int pin) 483 { 484 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 485 void __iomem *padcfg0; 486 unsigned long flags; 487 488 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 489 490 raw_spin_lock_irqsave(&pctrl->lock, flags); 491 492 if (!intel_pad_owned_by_host(pctrl, pin)) { 493 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 494 return -EBUSY; 495 } 496 497 if (!intel_pad_is_unlocked(pctrl, pin)) { 498 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 499 return 0; 500 } 501 502 /* 503 * If pin is already configured in GPIO mode, we assume that 504 * firmware provides correct settings. In such case we avoid 505 * potential glitches on the pin. Otherwise, for the pin in 506 * alternative mode, consumer has to supply respective flags. 507 */ 508 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) { 509 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 510 return 0; 511 } 512 513 intel_gpio_set_gpio_mode(padcfg0); 514 515 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 516 517 return 0; 518 } 519 520 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 521 struct pinctrl_gpio_range *range, 522 unsigned int pin, bool input) 523 { 524 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 525 void __iomem *padcfg0; 526 unsigned long flags; 527 528 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 529 530 raw_spin_lock_irqsave(&pctrl->lock, flags); 531 __intel_gpio_set_direction(padcfg0, input); 532 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 533 534 return 0; 535 } 536 537 static const struct pinmux_ops intel_pinmux_ops = { 538 .get_functions_count = intel_get_functions_count, 539 .get_function_name = intel_get_function_name, 540 .get_function_groups = intel_get_function_groups, 541 .set_mux = intel_pinmux_set_mux, 542 .gpio_request_enable = intel_gpio_request_enable, 543 .gpio_set_direction = intel_gpio_set_direction, 544 }; 545 546 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin, 547 enum pin_config_param param, u32 *arg) 548 { 549 const struct intel_community *community; 550 void __iomem *padcfg1; 551 unsigned long flags; 552 u32 value, term; 553 554 community = intel_get_community(pctrl, pin); 555 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 556 557 raw_spin_lock_irqsave(&pctrl->lock, flags); 558 value = readl(padcfg1); 559 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 560 561 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 562 563 switch (param) { 564 case PIN_CONFIG_BIAS_DISABLE: 565 if (term) 566 return -EINVAL; 567 break; 568 569 case PIN_CONFIG_BIAS_PULL_UP: 570 if (!term || !(value & PADCFG1_TERM_UP)) 571 return -EINVAL; 572 573 switch (term) { 574 case PADCFG1_TERM_833: 575 *arg = 833; 576 break; 577 case PADCFG1_TERM_1K: 578 *arg = 1000; 579 break; 580 case PADCFG1_TERM_4K: 581 *arg = 4000; 582 break; 583 case PADCFG1_TERM_5K: 584 *arg = 5000; 585 break; 586 case PADCFG1_TERM_20K: 587 *arg = 20000; 588 break; 589 } 590 591 break; 592 593 case PIN_CONFIG_BIAS_PULL_DOWN: 594 if (!term || value & PADCFG1_TERM_UP) 595 return -EINVAL; 596 597 switch (term) { 598 case PADCFG1_TERM_833: 599 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 600 return -EINVAL; 601 *arg = 833; 602 break; 603 case PADCFG1_TERM_1K: 604 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 605 return -EINVAL; 606 *arg = 1000; 607 break; 608 case PADCFG1_TERM_4K: 609 *arg = 4000; 610 break; 611 case PADCFG1_TERM_5K: 612 *arg = 5000; 613 break; 614 case PADCFG1_TERM_20K: 615 *arg = 20000; 616 break; 617 } 618 619 break; 620 621 default: 622 return -EINVAL; 623 } 624 625 return 0; 626 } 627 628 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin, 629 enum pin_config_param param, u32 *arg) 630 { 631 void __iomem *padcfg2; 632 unsigned long flags; 633 unsigned long v; 634 u32 value2; 635 636 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 637 if (!padcfg2) 638 return -ENOTSUPP; 639 640 raw_spin_lock_irqsave(&pctrl->lock, flags); 641 value2 = readl(padcfg2); 642 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 643 if (!(value2 & PADCFG2_DEBEN)) 644 return -EINVAL; 645 646 v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; 647 *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC; 648 649 return 0; 650 } 651 652 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 653 unsigned long *config) 654 { 655 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 656 enum pin_config_param param = pinconf_to_config_param(*config); 657 u32 arg = 0; 658 int ret; 659 660 if (!intel_pad_owned_by_host(pctrl, pin)) 661 return -ENOTSUPP; 662 663 switch (param) { 664 case PIN_CONFIG_BIAS_DISABLE: 665 case PIN_CONFIG_BIAS_PULL_UP: 666 case PIN_CONFIG_BIAS_PULL_DOWN: 667 ret = intel_config_get_pull(pctrl, pin, param, &arg); 668 if (ret) 669 return ret; 670 break; 671 672 case PIN_CONFIG_INPUT_DEBOUNCE: 673 ret = intel_config_get_debounce(pctrl, pin, param, &arg); 674 if (ret) 675 return ret; 676 break; 677 678 default: 679 return -ENOTSUPP; 680 } 681 682 *config = pinconf_to_config_packed(param, arg); 683 return 0; 684 } 685 686 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 687 unsigned long config) 688 { 689 unsigned int param = pinconf_to_config_param(config); 690 unsigned int arg = pinconf_to_config_argument(config); 691 const struct intel_community *community; 692 void __iomem *padcfg1; 693 unsigned long flags; 694 int ret = 0; 695 u32 value; 696 697 community = intel_get_community(pctrl, pin); 698 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 699 700 raw_spin_lock_irqsave(&pctrl->lock, flags); 701 702 value = readl(padcfg1); 703 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 704 705 /* Set default strength value in case none is given */ 706 if (arg == 1) 707 arg = 5000; 708 709 switch (param) { 710 case PIN_CONFIG_BIAS_DISABLE: 711 break; 712 713 case PIN_CONFIG_BIAS_PULL_UP: 714 switch (arg) { 715 case 20000: 716 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 717 break; 718 case 5000: 719 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 720 break; 721 case 4000: 722 value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT; 723 break; 724 case 1000: 725 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 726 break; 727 case 833: 728 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; 729 break; 730 default: 731 ret = -EINVAL; 732 break; 733 } 734 735 value |= PADCFG1_TERM_UP; 736 break; 737 738 case PIN_CONFIG_BIAS_PULL_DOWN: 739 switch (arg) { 740 case 20000: 741 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 742 break; 743 case 5000: 744 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 745 break; 746 case 4000: 747 value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT; 748 break; 749 case 1000: 750 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 751 ret = -EINVAL; 752 break; 753 } 754 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 755 break; 756 case 833: 757 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 758 ret = -EINVAL; 759 break; 760 } 761 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; 762 break; 763 default: 764 ret = -EINVAL; 765 break; 766 } 767 768 break; 769 770 default: 771 ret = -EINVAL; 772 break; 773 } 774 775 if (!ret) 776 writel(value, padcfg1); 777 778 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 779 780 return ret; 781 } 782 783 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, 784 unsigned int pin, unsigned int debounce) 785 { 786 void __iomem *padcfg0, *padcfg2; 787 unsigned long flags; 788 u32 value0, value2; 789 790 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 791 if (!padcfg2) 792 return -ENOTSUPP; 793 794 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 795 796 raw_spin_lock_irqsave(&pctrl->lock, flags); 797 798 value0 = readl(padcfg0); 799 value2 = readl(padcfg2); 800 801 /* Disable glitch filter and debouncer */ 802 value0 &= ~PADCFG0_PREGFRXSEL; 803 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); 804 805 if (debounce) { 806 unsigned long v; 807 808 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC); 809 if (v < 3 || v > 15) { 810 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 811 return -EINVAL; 812 } 813 814 /* Enable glitch filter and debouncer */ 815 value0 |= PADCFG0_PREGFRXSEL; 816 value2 |= v << PADCFG2_DEBOUNCE_SHIFT; 817 value2 |= PADCFG2_DEBEN; 818 } 819 820 writel(value0, padcfg0); 821 writel(value2, padcfg2); 822 823 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 824 825 return 0; 826 } 827 828 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 829 unsigned long *configs, unsigned int nconfigs) 830 { 831 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 832 int i, ret; 833 834 if (!intel_pad_usable(pctrl, pin)) 835 return -ENOTSUPP; 836 837 for (i = 0; i < nconfigs; i++) { 838 switch (pinconf_to_config_param(configs[i])) { 839 case PIN_CONFIG_BIAS_DISABLE: 840 case PIN_CONFIG_BIAS_PULL_UP: 841 case PIN_CONFIG_BIAS_PULL_DOWN: 842 ret = intel_config_set_pull(pctrl, pin, configs[i]); 843 if (ret) 844 return ret; 845 break; 846 847 case PIN_CONFIG_INPUT_DEBOUNCE: 848 ret = intel_config_set_debounce(pctrl, pin, 849 pinconf_to_config_argument(configs[i])); 850 if (ret) 851 return ret; 852 break; 853 854 default: 855 return -ENOTSUPP; 856 } 857 } 858 859 return 0; 860 } 861 862 static const struct pinconf_ops intel_pinconf_ops = { 863 .is_generic = true, 864 .pin_config_get = intel_config_get, 865 .pin_config_set = intel_config_set, 866 }; 867 868 static const struct pinctrl_desc intel_pinctrl_desc = { 869 .pctlops = &intel_pinctrl_ops, 870 .pmxops = &intel_pinmux_ops, 871 .confops = &intel_pinconf_ops, 872 .owner = THIS_MODULE, 873 }; 874 875 /** 876 * intel_gpio_to_pin() - Translate from GPIO offset to pin number 877 * @pctrl: Pinctrl structure 878 * @offset: GPIO offset from gpiolib 879 * @community: Community is filled here if not %NULL 880 * @padgrp: Pad group is filled here if not %NULL 881 * 882 * When coming through gpiolib irqchip, the GPIO offset is not 883 * automatically translated to pinctrl pin number. This function can be 884 * used to find out the corresponding pinctrl pin. 885 * 886 * Return: a pin number and pointers to the community and pad group, which 887 * the pin belongs to, or negative error code if translation can't be done. 888 */ 889 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, 890 const struct intel_community **community, 891 const struct intel_padgroup **padgrp) 892 { 893 int i; 894 895 for (i = 0; i < pctrl->ncommunities; i++) { 896 const struct intel_community *comm = &pctrl->communities[i]; 897 int j; 898 899 for (j = 0; j < comm->ngpps; j++) { 900 const struct intel_padgroup *pgrp = &comm->gpps[j]; 901 902 if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 903 continue; 904 905 if (offset >= pgrp->gpio_base && 906 offset < pgrp->gpio_base + pgrp->size) { 907 int pin; 908 909 pin = pgrp->base + offset - pgrp->gpio_base; 910 if (community) 911 *community = comm; 912 if (padgrp) 913 *padgrp = pgrp; 914 915 return pin; 916 } 917 } 918 } 919 920 return -EINVAL; 921 } 922 923 /** 924 * intel_pin_to_gpio() - Translate from pin number to GPIO offset 925 * @pctrl: Pinctrl structure 926 * @pin: pin number 927 * 928 * Translate the pin number of pinctrl to GPIO offset 929 * 930 * Return: a GPIO offset, or negative error code if translation can't be done. 931 */ 932 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin) 933 { 934 const struct intel_community *community; 935 const struct intel_padgroup *padgrp; 936 937 community = intel_get_community(pctrl, pin); 938 if (!community) 939 return -EINVAL; 940 941 padgrp = intel_community_get_padgroup(community, pin); 942 if (!padgrp) 943 return -EINVAL; 944 945 return pin - padgrp->base + padgrp->gpio_base; 946 } 947 948 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) 949 { 950 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 951 void __iomem *reg; 952 u32 padcfg0; 953 int pin; 954 955 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 956 if (pin < 0) 957 return -EINVAL; 958 959 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 960 if (!reg) 961 return -EINVAL; 962 963 padcfg0 = readl(reg); 964 if (!(padcfg0 & PADCFG0_GPIOTXDIS)) 965 return !!(padcfg0 & PADCFG0_GPIOTXSTATE); 966 967 return !!(padcfg0 & PADCFG0_GPIORXSTATE); 968 } 969 970 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, 971 int value) 972 { 973 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 974 unsigned long flags; 975 void __iomem *reg; 976 u32 padcfg0; 977 int pin; 978 979 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 980 if (pin < 0) 981 return; 982 983 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 984 if (!reg) 985 return; 986 987 raw_spin_lock_irqsave(&pctrl->lock, flags); 988 padcfg0 = readl(reg); 989 if (value) 990 padcfg0 |= PADCFG0_GPIOTXSTATE; 991 else 992 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 993 writel(padcfg0, reg); 994 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 995 } 996 997 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 998 { 999 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1000 unsigned long flags; 1001 void __iomem *reg; 1002 u32 padcfg0; 1003 int pin; 1004 1005 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 1006 if (pin < 0) 1007 return -EINVAL; 1008 1009 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1010 if (!reg) 1011 return -EINVAL; 1012 1013 raw_spin_lock_irqsave(&pctrl->lock, flags); 1014 padcfg0 = readl(reg); 1015 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1016 if (padcfg0 & PADCFG0_PMODE_MASK) 1017 return -EINVAL; 1018 1019 if (padcfg0 & PADCFG0_GPIOTXDIS) 1020 return GPIO_LINE_DIRECTION_IN; 1021 1022 return GPIO_LINE_DIRECTION_OUT; 1023 } 1024 1025 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1026 { 1027 return pinctrl_gpio_direction_input(chip->base + offset); 1028 } 1029 1030 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 1031 int value) 1032 { 1033 intel_gpio_set(chip, offset, value); 1034 return pinctrl_gpio_direction_output(chip->base + offset); 1035 } 1036 1037 static const struct gpio_chip intel_gpio_chip = { 1038 .owner = THIS_MODULE, 1039 .request = gpiochip_generic_request, 1040 .free = gpiochip_generic_free, 1041 .get_direction = intel_gpio_get_direction, 1042 .direction_input = intel_gpio_direction_input, 1043 .direction_output = intel_gpio_direction_output, 1044 .get = intel_gpio_get, 1045 .set = intel_gpio_set, 1046 .set_config = gpiochip_generic_config, 1047 }; 1048 1049 static void intel_gpio_irq_ack(struct irq_data *d) 1050 { 1051 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1052 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1053 const struct intel_community *community; 1054 const struct intel_padgroup *padgrp; 1055 int pin; 1056 1057 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 1058 if (pin >= 0) { 1059 unsigned int gpp, gpp_offset, is_offset; 1060 1061 gpp = padgrp->reg_num; 1062 gpp_offset = padgroup_offset(padgrp, pin); 1063 is_offset = community->is_offset + gpp * 4; 1064 1065 raw_spin_lock(&pctrl->lock); 1066 writel(BIT(gpp_offset), community->regs + is_offset); 1067 raw_spin_unlock(&pctrl->lock); 1068 } 1069 } 1070 1071 static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) 1072 { 1073 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1074 const struct intel_community *community; 1075 const struct intel_padgroup *padgrp; 1076 int pin; 1077 1078 pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp); 1079 if (pin >= 0) { 1080 unsigned int gpp, gpp_offset; 1081 unsigned long flags; 1082 void __iomem *reg, *is; 1083 u32 value; 1084 1085 gpp = padgrp->reg_num; 1086 gpp_offset = padgroup_offset(padgrp, pin); 1087 1088 reg = community->regs + community->ie_offset + gpp * 4; 1089 is = community->regs + community->is_offset + gpp * 4; 1090 1091 raw_spin_lock_irqsave(&pctrl->lock, flags); 1092 1093 /* Clear interrupt status first to avoid unexpected interrupt */ 1094 writel(BIT(gpp_offset), is); 1095 1096 value = readl(reg); 1097 if (mask) 1098 value &= ~BIT(gpp_offset); 1099 else 1100 value |= BIT(gpp_offset); 1101 writel(value, reg); 1102 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1103 } 1104 } 1105 1106 static void intel_gpio_irq_mask(struct irq_data *d) 1107 { 1108 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1109 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1110 1111 intel_gpio_irq_mask_unmask(gc, hwirq, true); 1112 gpiochip_disable_irq(gc, hwirq); 1113 } 1114 1115 static void intel_gpio_irq_unmask(struct irq_data *d) 1116 { 1117 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1118 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1119 1120 gpiochip_enable_irq(gc, hwirq); 1121 intel_gpio_irq_mask_unmask(gc, hwirq, false); 1122 } 1123 1124 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) 1125 { 1126 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1127 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1128 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1129 unsigned long flags; 1130 void __iomem *reg; 1131 u32 value; 1132 1133 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1134 if (!reg) 1135 return -EINVAL; 1136 1137 /* 1138 * If the pin is in ACPI mode it is still usable as a GPIO but it 1139 * cannot be used as IRQ because GPI_IS status bit will not be 1140 * updated by the host controller hardware. 1141 */ 1142 if (intel_pad_acpi_mode(pctrl, pin)) { 1143 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 1144 return -EPERM; 1145 } 1146 1147 raw_spin_lock_irqsave(&pctrl->lock, flags); 1148 1149 intel_gpio_set_gpio_mode(reg); 1150 1151 value = readl(reg); 1152 1153 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 1154 1155 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 1156 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 1157 } else if (type & IRQ_TYPE_EDGE_FALLING) { 1158 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1159 value |= PADCFG0_RXINV; 1160 } else if (type & IRQ_TYPE_EDGE_RISING) { 1161 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1162 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1163 if (type & IRQ_TYPE_LEVEL_LOW) 1164 value |= PADCFG0_RXINV; 1165 } else { 1166 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 1167 } 1168 1169 writel(value, reg); 1170 1171 if (type & IRQ_TYPE_EDGE_BOTH) 1172 irq_set_handler_locked(d, handle_edge_irq); 1173 else if (type & IRQ_TYPE_LEVEL_MASK) 1174 irq_set_handler_locked(d, handle_level_irq); 1175 1176 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1177 1178 return 0; 1179 } 1180 1181 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 1182 { 1183 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1184 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1185 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1186 1187 if (on) 1188 enable_irq_wake(pctrl->irq); 1189 else 1190 disable_irq_wake(pctrl->irq); 1191 1192 dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin); 1193 return 0; 1194 } 1195 1196 static const struct irq_chip intel_gpio_irq_chip = { 1197 .name = "intel-gpio", 1198 .irq_ack = intel_gpio_irq_ack, 1199 .irq_mask = intel_gpio_irq_mask, 1200 .irq_unmask = intel_gpio_irq_unmask, 1201 .irq_set_type = intel_gpio_irq_type, 1202 .irq_set_wake = intel_gpio_irq_wake, 1203 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 1204 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1205 }; 1206 1207 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 1208 const struct intel_community *community) 1209 { 1210 struct gpio_chip *gc = &pctrl->chip; 1211 unsigned int gpp; 1212 int ret = 0; 1213 1214 for (gpp = 0; gpp < community->ngpps; gpp++) { 1215 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1216 unsigned long pending, enabled, gpp_offset; 1217 1218 raw_spin_lock(&pctrl->lock); 1219 1220 pending = readl(community->regs + community->is_offset + 1221 padgrp->reg_num * 4); 1222 enabled = readl(community->regs + community->ie_offset + 1223 padgrp->reg_num * 4); 1224 1225 raw_spin_unlock(&pctrl->lock); 1226 1227 /* Only interrupts that are enabled */ 1228 pending &= enabled; 1229 1230 for_each_set_bit(gpp_offset, &pending, padgrp->size) 1231 generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset); 1232 1233 ret += pending ? 1 : 0; 1234 } 1235 1236 return ret; 1237 } 1238 1239 static irqreturn_t intel_gpio_irq(int irq, void *data) 1240 { 1241 const struct intel_community *community; 1242 struct intel_pinctrl *pctrl = data; 1243 unsigned int i; 1244 int ret = 0; 1245 1246 /* Need to check all communities for pending interrupts */ 1247 for (i = 0; i < pctrl->ncommunities; i++) { 1248 community = &pctrl->communities[i]; 1249 ret += intel_gpio_community_irq_handler(pctrl, community); 1250 } 1251 1252 return IRQ_RETVAL(ret); 1253 } 1254 1255 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1256 { 1257 int i; 1258 1259 for (i = 0; i < pctrl->ncommunities; i++) { 1260 const struct intel_community *community; 1261 void __iomem *base; 1262 unsigned int gpp; 1263 1264 community = &pctrl->communities[i]; 1265 base = community->regs; 1266 1267 for (gpp = 0; gpp < community->ngpps; gpp++) { 1268 /* Mask and clear all interrupts */ 1269 writel(0, base + community->ie_offset + gpp * 4); 1270 writel(0xffff, base + community->is_offset + gpp * 4); 1271 } 1272 } 1273 } 1274 1275 static int intel_gpio_irq_init_hw(struct gpio_chip *gc) 1276 { 1277 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1278 1279 /* 1280 * Make sure the interrupt lines are in a proper state before 1281 * further configuration. 1282 */ 1283 intel_gpio_irq_init(pctrl); 1284 1285 return 0; 1286 } 1287 1288 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl, 1289 const struct intel_community *community) 1290 { 1291 int ret = 0, i; 1292 1293 for (i = 0; i < community->ngpps; i++) { 1294 const struct intel_padgroup *gpp = &community->gpps[i]; 1295 1296 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1297 continue; 1298 1299 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1300 gpp->gpio_base, gpp->base, 1301 gpp->size); 1302 if (ret) 1303 return ret; 1304 } 1305 1306 return ret; 1307 } 1308 1309 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) 1310 { 1311 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1312 int ret, i; 1313 1314 for (i = 0; i < pctrl->ncommunities; i++) { 1315 struct intel_community *community = &pctrl->communities[i]; 1316 1317 ret = intel_gpio_add_community_ranges(pctrl, community); 1318 if (ret) { 1319 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1320 return ret; 1321 } 1322 } 1323 1324 return 0; 1325 } 1326 1327 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1328 { 1329 const struct intel_community *community; 1330 unsigned int ngpio = 0; 1331 int i, j; 1332 1333 for (i = 0; i < pctrl->ncommunities; i++) { 1334 community = &pctrl->communities[i]; 1335 for (j = 0; j < community->ngpps; j++) { 1336 const struct intel_padgroup *gpp = &community->gpps[j]; 1337 1338 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1339 continue; 1340 1341 if (gpp->gpio_base + gpp->size > ngpio) 1342 ngpio = gpp->gpio_base + gpp->size; 1343 } 1344 } 1345 1346 return ngpio; 1347 } 1348 1349 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1350 { 1351 int ret; 1352 struct gpio_irq_chip *girq; 1353 1354 pctrl->chip = intel_gpio_chip; 1355 1356 /* Setup GPIO chip */ 1357 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); 1358 pctrl->chip.label = dev_name(pctrl->dev); 1359 pctrl->chip.parent = pctrl->dev; 1360 pctrl->chip.base = -1; 1361 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; 1362 pctrl->irq = irq; 1363 1364 /* 1365 * On some platforms several GPIO controllers share the same interrupt 1366 * line. 1367 */ 1368 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1369 IRQF_SHARED | IRQF_NO_THREAD, 1370 dev_name(pctrl->dev), pctrl); 1371 if (ret) { 1372 dev_err(pctrl->dev, "failed to request interrupt\n"); 1373 return ret; 1374 } 1375 1376 /* Setup IRQ chip */ 1377 girq = &pctrl->chip.irq; 1378 gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip); 1379 /* This will let us handle the IRQ in the driver */ 1380 girq->parent_handler = NULL; 1381 girq->num_parents = 0; 1382 girq->default_type = IRQ_TYPE_NONE; 1383 girq->handler = handle_bad_irq; 1384 girq->init_hw = intel_gpio_irq_init_hw; 1385 1386 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1387 if (ret) { 1388 dev_err(pctrl->dev, "failed to register gpiochip\n"); 1389 return ret; 1390 } 1391 1392 return 0; 1393 } 1394 1395 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl, 1396 struct intel_community *community) 1397 { 1398 struct intel_padgroup *gpps; 1399 unsigned int padown_num = 0; 1400 size_t i, ngpps = community->ngpps; 1401 1402 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1403 if (!gpps) 1404 return -ENOMEM; 1405 1406 for (i = 0; i < ngpps; i++) { 1407 gpps[i] = community->gpps[i]; 1408 1409 if (gpps[i].size > INTEL_PINCTRL_MAX_GPP_SIZE) 1410 return -EINVAL; 1411 1412 /* Special treatment for GPIO base */ 1413 switch (gpps[i].gpio_base) { 1414 case INTEL_GPIO_BASE_MATCH: 1415 gpps[i].gpio_base = gpps[i].base; 1416 break; 1417 case INTEL_GPIO_BASE_ZERO: 1418 gpps[i].gpio_base = 0; 1419 break; 1420 case INTEL_GPIO_BASE_NOMAP: 1421 break; 1422 default: 1423 break; 1424 } 1425 1426 gpps[i].padown_num = padown_num; 1427 padown_num += DIV_ROUND_UP(gpps[i].size * 4, INTEL_PINCTRL_MAX_GPP_SIZE); 1428 } 1429 1430 community->gpps = gpps; 1431 1432 return 0; 1433 } 1434 1435 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl, 1436 struct intel_community *community) 1437 { 1438 struct intel_padgroup *gpps; 1439 unsigned int npins = community->npins; 1440 unsigned int padown_num = 0; 1441 size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size); 1442 1443 if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE) 1444 return -EINVAL; 1445 1446 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1447 if (!gpps) 1448 return -ENOMEM; 1449 1450 for (i = 0; i < ngpps; i++) { 1451 unsigned int gpp_size = community->gpp_size; 1452 1453 gpps[i].reg_num = i; 1454 gpps[i].base = community->pin_base + i * gpp_size; 1455 gpps[i].size = min(gpp_size, npins); 1456 npins -= gpps[i].size; 1457 1458 gpps[i].gpio_base = gpps[i].base; 1459 gpps[i].padown_num = padown_num; 1460 1461 padown_num += community->gpp_num_padown_regs; 1462 } 1463 1464 community->ngpps = ngpps; 1465 community->gpps = gpps; 1466 1467 return 0; 1468 } 1469 1470 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 1471 { 1472 #ifdef CONFIG_PM_SLEEP 1473 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 1474 struct intel_community_context *communities; 1475 struct intel_pad_context *pads; 1476 int i; 1477 1478 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 1479 if (!pads) 1480 return -ENOMEM; 1481 1482 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 1483 sizeof(*communities), GFP_KERNEL); 1484 if (!communities) 1485 return -ENOMEM; 1486 1487 1488 for (i = 0; i < pctrl->ncommunities; i++) { 1489 struct intel_community *community = &pctrl->communities[i]; 1490 u32 *intmask, *hostown; 1491 1492 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1493 sizeof(*intmask), GFP_KERNEL); 1494 if (!intmask) 1495 return -ENOMEM; 1496 1497 communities[i].intmask = intmask; 1498 1499 hostown = devm_kcalloc(pctrl->dev, community->ngpps, 1500 sizeof(*hostown), GFP_KERNEL); 1501 if (!hostown) 1502 return -ENOMEM; 1503 1504 communities[i].hostown = hostown; 1505 } 1506 1507 pctrl->context.pads = pads; 1508 pctrl->context.communities = communities; 1509 #endif 1510 1511 return 0; 1512 } 1513 1514 static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, 1515 struct intel_community *community) 1516 { 1517 static const struct pwm_lpss_boardinfo info = { 1518 .clk_rate = 19200000, 1519 .npwm = 1, 1520 .base_unit_bits = 22, 1521 .bypass = true, 1522 }; 1523 struct pwm_lpss_chip *pwm; 1524 1525 if (!(community->features & PINCTRL_FEATURE_PWM)) 1526 return 0; 1527 1528 if (!IS_REACHABLE(CONFIG_PWM_LPSS)) 1529 return 0; 1530 1531 pwm = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); 1532 return PTR_ERR_OR_ZERO(pwm); 1533 } 1534 1535 static int intel_pinctrl_probe(struct platform_device *pdev, 1536 const struct intel_pinctrl_soc_data *soc_data) 1537 { 1538 struct device *dev = &pdev->dev; 1539 struct intel_pinctrl *pctrl; 1540 int i, ret, irq; 1541 1542 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 1543 if (!pctrl) 1544 return -ENOMEM; 1545 1546 pctrl->dev = dev; 1547 pctrl->soc = soc_data; 1548 raw_spin_lock_init(&pctrl->lock); 1549 1550 /* 1551 * Make a copy of the communities which we can use to hold pointers 1552 * to the registers. 1553 */ 1554 pctrl->ncommunities = pctrl->soc->ncommunities; 1555 pctrl->communities = devm_kcalloc(dev, pctrl->ncommunities, 1556 sizeof(*pctrl->communities), GFP_KERNEL); 1557 if (!pctrl->communities) 1558 return -ENOMEM; 1559 1560 for (i = 0; i < pctrl->ncommunities; i++) { 1561 struct intel_community *community = &pctrl->communities[i]; 1562 void __iomem *regs; 1563 u32 offset; 1564 u32 value; 1565 1566 *community = pctrl->soc->communities[i]; 1567 1568 regs = devm_platform_ioremap_resource(pdev, community->barno); 1569 if (IS_ERR(regs)) 1570 return PTR_ERR(regs); 1571 1572 /* 1573 * Determine community features based on the revision. 1574 * A value of all ones means the device is not present. 1575 */ 1576 value = readl(regs + REVID); 1577 if (value == ~0u) 1578 return -ENODEV; 1579 if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) { 1580 community->features |= PINCTRL_FEATURE_DEBOUNCE; 1581 community->features |= PINCTRL_FEATURE_1K_PD; 1582 } 1583 1584 /* Determine community features based on the capabilities */ 1585 offset = CAPLIST; 1586 do { 1587 value = readl(regs + offset); 1588 switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) { 1589 case CAPLIST_ID_GPIO_HW_INFO: 1590 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO; 1591 break; 1592 case CAPLIST_ID_PWM: 1593 community->features |= PINCTRL_FEATURE_PWM; 1594 break; 1595 case CAPLIST_ID_BLINK: 1596 community->features |= PINCTRL_FEATURE_BLINK; 1597 break; 1598 case CAPLIST_ID_EXP: 1599 community->features |= PINCTRL_FEATURE_EXP; 1600 break; 1601 default: 1602 break; 1603 } 1604 offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT; 1605 } while (offset); 1606 1607 dev_dbg(dev, "Community%d features: %#08x\n", i, community->features); 1608 1609 /* Read offset of the pad configuration registers */ 1610 offset = readl(regs + PADBAR); 1611 1612 community->regs = regs; 1613 community->pad_regs = regs + offset; 1614 1615 if (community->gpps) 1616 ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community); 1617 else 1618 ret = intel_pinctrl_add_padgroups_by_size(pctrl, community); 1619 if (ret) 1620 return ret; 1621 1622 ret = intel_pinctrl_probe_pwm(pctrl, community); 1623 if (ret) 1624 return ret; 1625 } 1626 1627 irq = platform_get_irq(pdev, 0); 1628 if (irq < 0) 1629 return irq; 1630 1631 ret = intel_pinctrl_pm_init(pctrl); 1632 if (ret) 1633 return ret; 1634 1635 pctrl->pctldesc = intel_pinctrl_desc; 1636 pctrl->pctldesc.name = dev_name(dev); 1637 pctrl->pctldesc.pins = pctrl->soc->pins; 1638 pctrl->pctldesc.npins = pctrl->soc->npins; 1639 1640 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); 1641 if (IS_ERR(pctrl->pctldev)) { 1642 dev_err(dev, "failed to register pinctrl driver\n"); 1643 return PTR_ERR(pctrl->pctldev); 1644 } 1645 1646 ret = intel_gpio_probe(pctrl, irq); 1647 if (ret) 1648 return ret; 1649 1650 platform_set_drvdata(pdev, pctrl); 1651 1652 return 0; 1653 } 1654 1655 int intel_pinctrl_probe_by_hid(struct platform_device *pdev) 1656 { 1657 const struct intel_pinctrl_soc_data *data; 1658 1659 data = device_get_match_data(&pdev->dev); 1660 if (!data) 1661 return -ENODATA; 1662 1663 return intel_pinctrl_probe(pdev, data); 1664 } 1665 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); 1666 1667 int intel_pinctrl_probe_by_uid(struct platform_device *pdev) 1668 { 1669 const struct intel_pinctrl_soc_data *data; 1670 1671 data = intel_pinctrl_get_soc_data(pdev); 1672 if (IS_ERR(data)) 1673 return PTR_ERR(data); 1674 1675 return intel_pinctrl_probe(pdev, data); 1676 } 1677 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); 1678 1679 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) 1680 { 1681 const struct intel_pinctrl_soc_data * const *table; 1682 const struct intel_pinctrl_soc_data *data = NULL; 1683 struct device *dev = &pdev->dev; 1684 1685 table = device_get_match_data(dev); 1686 if (table) { 1687 struct acpi_device *adev = ACPI_COMPANION(dev); 1688 unsigned int i; 1689 1690 for (i = 0; table[i]; i++) { 1691 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) { 1692 data = table[i]; 1693 break; 1694 } 1695 } 1696 } else { 1697 const struct platform_device_id *id; 1698 1699 id = platform_get_device_id(pdev); 1700 if (!id) 1701 return ERR_PTR(-ENODEV); 1702 1703 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data; 1704 data = table[pdev->id]; 1705 } 1706 1707 return data ?: ERR_PTR(-ENODATA); 1708 } 1709 EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data); 1710 1711 #ifdef CONFIG_PM_SLEEP 1712 static bool __intel_gpio_is_direct_irq(u32 value) 1713 { 1714 return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) && 1715 (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO); 1716 } 1717 1718 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) 1719 { 1720 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1721 u32 value; 1722 1723 if (!pd || !intel_pad_usable(pctrl, pin)) 1724 return false; 1725 1726 /* 1727 * Only restore the pin if it is actually in use by the kernel (or 1728 * by userspace). It is possible that some pins are used by the 1729 * BIOS during resume and those are not always locked down so leave 1730 * them alone. 1731 */ 1732 if (pd->mux_owner || pd->gpio_owner || 1733 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) 1734 return true; 1735 1736 /* 1737 * The firmware on some systems may configure GPIO pins to be 1738 * an interrupt source in so called "direct IRQ" mode. In such 1739 * cases the GPIO controller driver has no idea if those pins 1740 * are being used or not. At the same time, there is a known bug 1741 * in the firmwares that don't restore the pin settings correctly 1742 * after suspend, i.e. by an unknown reason the Rx value becomes 1743 * inverted. 1744 * 1745 * Hence, let's save and restore the pins that are configured 1746 * as GPIOs in the input mode with GPIROUTIOXAPIC bit set. 1747 * 1748 * See https://bugzilla.kernel.org/show_bug.cgi?id=214749. 1749 */ 1750 value = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 1751 if (__intel_gpio_is_direct_irq(value)) 1752 return true; 1753 1754 return false; 1755 } 1756 1757 int intel_pinctrl_suspend_noirq(struct device *dev) 1758 { 1759 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1760 struct intel_community_context *communities; 1761 struct intel_pad_context *pads; 1762 int i; 1763 1764 pads = pctrl->context.pads; 1765 for (i = 0; i < pctrl->soc->npins; i++) { 1766 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1767 void __iomem *padcfg; 1768 u32 val; 1769 1770 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1771 continue; 1772 1773 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1774 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1775 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1776 pads[i].padcfg1 = val; 1777 1778 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1779 if (padcfg) 1780 pads[i].padcfg2 = readl(padcfg); 1781 } 1782 1783 communities = pctrl->context.communities; 1784 for (i = 0; i < pctrl->ncommunities; i++) { 1785 struct intel_community *community = &pctrl->communities[i]; 1786 void __iomem *base; 1787 unsigned int gpp; 1788 1789 base = community->regs + community->ie_offset; 1790 for (gpp = 0; gpp < community->ngpps; gpp++) 1791 communities[i].intmask[gpp] = readl(base + gpp * 4); 1792 1793 base = community->regs + community->hostown_offset; 1794 for (gpp = 0; gpp < community->ngpps; gpp++) 1795 communities[i].hostown[gpp] = readl(base + gpp * 4); 1796 } 1797 1798 return 0; 1799 } 1800 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq); 1801 1802 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value) 1803 { 1804 u32 curr, updated; 1805 1806 curr = readl(reg); 1807 1808 updated = (curr & ~mask) | (value & mask); 1809 if (curr == updated) 1810 return false; 1811 1812 writel(updated, reg); 1813 return true; 1814 } 1815 1816 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, 1817 void __iomem *base, unsigned int gpp, u32 saved) 1818 { 1819 const struct intel_community *community = &pctrl->communities[c]; 1820 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1821 struct device *dev = pctrl->dev; 1822 const char *dummy; 1823 u32 requested = 0; 1824 unsigned int i; 1825 1826 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1827 return; 1828 1829 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy) 1830 requested |= BIT(i); 1831 1832 if (!intel_gpio_update_reg(base + gpp * 4, requested, saved)) 1833 return; 1834 1835 dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1836 } 1837 1838 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, 1839 void __iomem *base, unsigned int gpp, u32 saved) 1840 { 1841 struct device *dev = pctrl->dev; 1842 1843 if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved)) 1844 return; 1845 1846 dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1847 } 1848 1849 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, 1850 unsigned int reg, u32 saved) 1851 { 1852 u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0; 1853 unsigned int n = reg / sizeof(u32); 1854 struct device *dev = pctrl->dev; 1855 void __iomem *padcfg; 1856 1857 padcfg = intel_get_padcfg(pctrl, pin, reg); 1858 if (!padcfg) 1859 return; 1860 1861 if (!intel_gpio_update_reg(padcfg, ~mask, saved)) 1862 return; 1863 1864 dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg)); 1865 } 1866 1867 int intel_pinctrl_resume_noirq(struct device *dev) 1868 { 1869 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1870 const struct intel_community_context *communities; 1871 const struct intel_pad_context *pads; 1872 int i; 1873 1874 /* Mask all interrupts */ 1875 intel_gpio_irq_init(pctrl); 1876 1877 pads = pctrl->context.pads; 1878 for (i = 0; i < pctrl->soc->npins; i++) { 1879 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1880 1881 if (!(intel_pinctrl_should_save(pctrl, desc->number) || 1882 /* 1883 * If the firmware mangled the register contents too much, 1884 * check the saved value for the Direct IRQ mode. 1885 */ 1886 __intel_gpio_is_direct_irq(pads[i].padcfg0))) 1887 continue; 1888 1889 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); 1890 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); 1891 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); 1892 } 1893 1894 communities = pctrl->context.communities; 1895 for (i = 0; i < pctrl->ncommunities; i++) { 1896 struct intel_community *community = &pctrl->communities[i]; 1897 void __iomem *base; 1898 unsigned int gpp; 1899 1900 base = community->regs + community->ie_offset; 1901 for (gpp = 0; gpp < community->ngpps; gpp++) 1902 intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]); 1903 1904 base = community->regs + community->hostown_offset; 1905 for (gpp = 0; gpp < community->ngpps; gpp++) 1906 intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]); 1907 } 1908 1909 return 0; 1910 } 1911 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq); 1912 #endif 1913 1914 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1915 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1916 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1917 MODULE_LICENSE("GPL v2"); 1918