1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel pinctrl/GPIO core driver. 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/cleanup.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/interrupt.h> 14 #include <linux/log2.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/seq_file.h> 19 #include <linux/string_helpers.h> 20 #include <linux/time.h> 21 22 #include <linux/pinctrl/consumer.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 28 #include <linux/platform_data/x86/pwm-lpss.h> 29 30 #include "../core.h" 31 #include "pinctrl-intel.h" 32 33 /* Offset from regs */ 34 #define REVID 0x000 35 #define REVID_SHIFT 16 36 #define REVID_MASK GENMASK(31, 16) 37 38 #define CAPLIST 0x004 39 #define CAPLIST_ID_SHIFT 16 40 #define CAPLIST_ID_MASK GENMASK(23, 16) 41 #define CAPLIST_ID_GPIO_HW_INFO 1 42 #define CAPLIST_ID_PWM 2 43 #define CAPLIST_ID_BLINK 3 44 #define CAPLIST_ID_EXP 4 45 #define CAPLIST_NEXT_SHIFT 0 46 #define CAPLIST_NEXT_MASK GENMASK(15, 0) 47 48 #define PADBAR 0x00c 49 50 #define PADOWN_BITS 4 51 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 52 #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) 53 #define PADOWN_GPP(p) ((p) / 8) 54 55 #define PWMC 0x204 56 57 /* Offset from pad_regs */ 58 #define PADCFG0 0x000 59 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25) 60 #define PADCFG0_RXEVCFG_LEVEL (0 << 25) 61 #define PADCFG0_RXEVCFG_EDGE (1 << 25) 62 #define PADCFG0_RXEVCFG_DISABLED (2 << 25) 63 #define PADCFG0_RXEVCFG_EDGE_BOTH (3 << 25) 64 #define PADCFG0_PREGFRXSEL BIT(24) 65 #define PADCFG0_RXINV BIT(23) 66 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 67 #define PADCFG0_GPIROUTSCI BIT(19) 68 #define PADCFG0_GPIROUTSMI BIT(18) 69 #define PADCFG0_GPIROUTNMI BIT(17) 70 #define PADCFG0_PMODE_SHIFT 10 71 #define PADCFG0_PMODE_MASK GENMASK(13, 10) 72 #define PADCFG0_PMODE_GPIO 0 73 #define PADCFG0_GPIODIS_SHIFT 8 74 #define PADCFG0_GPIODIS_MASK GENMASK(9, 8) 75 #define PADCFG0_GPIODIS_NONE 0 76 #define PADCFG0_GPIODIS_OUTPUT 1 77 #define PADCFG0_GPIODIS_INPUT 2 78 #define PADCFG0_GPIODIS_FULL 3 79 #define PADCFG0_GPIORXDIS BIT(9) 80 #define PADCFG0_GPIOTXDIS BIT(8) 81 #define PADCFG0_GPIORXSTATE BIT(1) 82 #define PADCFG0_GPIOTXSTATE BIT(0) 83 84 #define PADCFG1 0x004 85 #define PADCFG1_TERM_UP BIT(13) 86 #define PADCFG1_TERM_SHIFT 10 87 #define PADCFG1_TERM_MASK GENMASK(12, 10) 88 #define PADCFG1_TERM_20K BIT(2) 89 #define PADCFG1_TERM_5K BIT(1) 90 #define PADCFG1_TERM_4K (BIT(2) | BIT(1)) 91 #define PADCFG1_TERM_1K BIT(0) 92 #define PADCFG1_TERM_952 (BIT(2) | BIT(0)) 93 #define PADCFG1_TERM_833 (BIT(1) | BIT(0)) 94 #define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0)) 95 96 #define PADCFG2 0x008 97 #define PADCFG2_DEBOUNCE_SHIFT 1 98 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) 99 #define PADCFG2_DEBEN BIT(0) 100 101 #define DEBOUNCE_PERIOD_NSEC 31250 102 103 struct intel_pad_context { 104 u32 padcfg0; 105 u32 padcfg1; 106 u32 padcfg2; 107 }; 108 109 struct intel_community_context { 110 u32 *intmask; 111 u32 *hostown; 112 }; 113 114 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 115 #define padgroup_offset(g, p) ((p) - (g)->base) 116 117 #define for_each_intel_pin_community(pctrl, community) \ 118 for (unsigned int __ci = 0; \ 119 __ci < pctrl->ncommunities && (community = &pctrl->communities[__ci]); \ 120 __ci++) \ 121 122 #define for_each_intel_community_pad_group(community, grp) \ 123 for (unsigned int __gi = 0; \ 124 __gi < community->ngpps && (grp = &community->gpps[__gi]); \ 125 __gi++) \ 126 127 #define for_each_intel_pad_group(pctrl, community, grp) \ 128 for_each_intel_pin_community(pctrl, community) \ 129 for_each_intel_community_pad_group(community, grp) 130 131 #define for_each_intel_gpio_group(pctrl, community, grp) \ 132 for_each_intel_pad_group(pctrl, community, grp) \ 133 if (grp->gpio_base == INTEL_GPIO_BASE_NOMAP) {} else 134 135 const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl, 136 unsigned int pin) 137 { 138 const struct intel_community *community; 139 140 for_each_intel_pin_community(pctrl, community) { 141 if (pin >= community->pin_base && 142 pin < community->pin_base + community->npins) 143 return community; 144 } 145 146 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 147 return NULL; 148 } 149 EXPORT_SYMBOL_NS_GPL(intel_get_community, PINCTRL_INTEL); 150 151 static const struct intel_padgroup * 152 intel_community_get_padgroup(const struct intel_community *community, 153 unsigned int pin) 154 { 155 const struct intel_padgroup *padgrp; 156 157 for_each_intel_community_pad_group(community, padgrp) { 158 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) 159 return padgrp; 160 } 161 162 return NULL; 163 } 164 165 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, 166 unsigned int pin, unsigned int reg) 167 { 168 const struct intel_community *community; 169 unsigned int padno; 170 size_t nregs; 171 172 community = intel_get_community(pctrl, pin); 173 if (!community) 174 return NULL; 175 176 padno = pin_to_padno(community, pin); 177 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; 178 179 if (reg >= nregs * 4) 180 return NULL; 181 182 return community->pad_regs + reg + padno * nregs * 4; 183 } 184 185 static bool intel_pad_owned_by_host(const struct intel_pinctrl *pctrl, unsigned int pin) 186 { 187 const struct intel_community *community; 188 const struct intel_padgroup *padgrp; 189 unsigned int gpp, offset, gpp_offset; 190 void __iomem *padown; 191 192 community = intel_get_community(pctrl, pin); 193 if (!community) 194 return false; 195 if (!community->padown_offset) 196 return true; 197 198 padgrp = intel_community_get_padgroup(community, pin); 199 if (!padgrp) 200 return false; 201 202 gpp_offset = padgroup_offset(padgrp, pin); 203 gpp = PADOWN_GPP(gpp_offset); 204 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; 205 padown = community->regs + offset; 206 207 return !(readl(padown) & PADOWN_MASK(gpp_offset)); 208 } 209 210 static bool intel_pad_acpi_mode(const struct intel_pinctrl *pctrl, unsigned int pin) 211 { 212 const struct intel_community *community; 213 const struct intel_padgroup *padgrp; 214 unsigned int offset, gpp_offset; 215 void __iomem *hostown; 216 217 community = intel_get_community(pctrl, pin); 218 if (!community) 219 return true; 220 if (!community->hostown_offset) 221 return false; 222 223 padgrp = intel_community_get_padgroup(community, pin); 224 if (!padgrp) 225 return true; 226 227 gpp_offset = padgroup_offset(padgrp, pin); 228 offset = community->hostown_offset + padgrp->reg_num * 4; 229 hostown = community->regs + offset; 230 231 return !(readl(hostown) & BIT(gpp_offset)); 232 } 233 234 /** 235 * enum - Locking variants of the pad configuration 236 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers 237 * @PAD_LOCKED: pad configuration registers, except TX state, are locked 238 * @PAD_LOCKED_TX: pad configuration TX state is locked 239 * @PAD_LOCKED_FULL: pad configuration registers are locked completely 240 * 241 * Locking is considered as read-only mode for corresponding registers and 242 * their respective fields. That said, TX state bit is locked separately from 243 * the main locking scheme. 244 */ 245 enum { 246 PAD_UNLOCKED = 0, 247 PAD_LOCKED = 1, 248 PAD_LOCKED_TX = 2, 249 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX, 250 }; 251 252 static int intel_pad_locked(const struct intel_pinctrl *pctrl, unsigned int pin) 253 { 254 const struct intel_community *community; 255 const struct intel_padgroup *padgrp; 256 unsigned int offset, gpp_offset; 257 u32 value; 258 int ret = PAD_UNLOCKED; 259 260 community = intel_get_community(pctrl, pin); 261 if (!community) 262 return PAD_LOCKED_FULL; 263 if (!community->padcfglock_offset) 264 return PAD_UNLOCKED; 265 266 padgrp = intel_community_get_padgroup(community, pin); 267 if (!padgrp) 268 return PAD_LOCKED_FULL; 269 270 gpp_offset = padgroup_offset(padgrp, pin); 271 272 /* 273 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 274 * the pad is considered unlocked. Any other case means that it is 275 * either fully or partially locked. 276 */ 277 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; 278 value = readl(community->regs + offset); 279 if (value & BIT(gpp_offset)) 280 ret |= PAD_LOCKED; 281 282 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; 283 value = readl(community->regs + offset); 284 if (value & BIT(gpp_offset)) 285 ret |= PAD_LOCKED_TX; 286 287 return ret; 288 } 289 290 static bool intel_pad_is_unlocked(const struct intel_pinctrl *pctrl, unsigned int pin) 291 { 292 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED; 293 } 294 295 static bool intel_pad_usable(const struct intel_pinctrl *pctrl, unsigned int pin) 296 { 297 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); 298 } 299 300 int intel_get_groups_count(struct pinctrl_dev *pctldev) 301 { 302 const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 303 304 return pctrl->soc->ngroups; 305 } 306 EXPORT_SYMBOL_NS_GPL(intel_get_groups_count, PINCTRL_INTEL); 307 308 const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group) 309 { 310 const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 311 312 return pctrl->soc->groups[group].grp.name; 313 } 314 EXPORT_SYMBOL_NS_GPL(intel_get_group_name, PINCTRL_INTEL); 315 316 int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 317 const unsigned int **pins, unsigned int *npins) 318 { 319 const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 320 321 *pins = pctrl->soc->groups[group].grp.pins; 322 *npins = pctrl->soc->groups[group].grp.npins; 323 return 0; 324 } 325 EXPORT_SYMBOL_NS_GPL(intel_get_group_pins, PINCTRL_INTEL); 326 327 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 328 unsigned int pin) 329 { 330 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 331 void __iomem *padcfg; 332 u32 cfg0, cfg1, mode; 333 int locked; 334 bool acpi; 335 336 if (!intel_pad_owned_by_host(pctrl, pin)) { 337 seq_puts(s, "not available"); 338 return; 339 } 340 341 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 342 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 343 344 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 345 if (mode == PADCFG0_PMODE_GPIO) 346 seq_puts(s, "GPIO "); 347 else 348 seq_printf(s, "mode %d ", mode); 349 350 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 351 352 /* Dump the additional PADCFG registers if available */ 353 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); 354 if (padcfg) 355 seq_printf(s, " 0x%08x", readl(padcfg)); 356 357 locked = intel_pad_locked(pctrl, pin); 358 acpi = intel_pad_acpi_mode(pctrl, pin); 359 360 if (locked || acpi) { 361 seq_puts(s, " ["); 362 if (locked) 363 seq_puts(s, "LOCKED"); 364 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) 365 seq_puts(s, " tx"); 366 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) 367 seq_puts(s, " full"); 368 369 if (locked && acpi) 370 seq_puts(s, ", "); 371 372 if (acpi) 373 seq_puts(s, "ACPI"); 374 seq_puts(s, "]"); 375 } 376 } 377 378 static const struct pinctrl_ops intel_pinctrl_ops = { 379 .get_groups_count = intel_get_groups_count, 380 .get_group_name = intel_get_group_name, 381 .get_group_pins = intel_get_group_pins, 382 .pin_dbg_show = intel_pin_dbg_show, 383 }; 384 385 int intel_get_functions_count(struct pinctrl_dev *pctldev) 386 { 387 const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 388 389 return pctrl->soc->nfunctions; 390 } 391 EXPORT_SYMBOL_NS_GPL(intel_get_functions_count, PINCTRL_INTEL); 392 393 const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function) 394 { 395 const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 396 397 return pctrl->soc->functions[function].func.name; 398 } 399 EXPORT_SYMBOL_NS_GPL(intel_get_function_name, PINCTRL_INTEL); 400 401 int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function, 402 const char * const **groups, unsigned int * const ngroups) 403 { 404 const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 405 406 *groups = pctrl->soc->functions[function].func.groups; 407 *ngroups = pctrl->soc->functions[function].func.ngroups; 408 return 0; 409 } 410 EXPORT_SYMBOL_NS_GPL(intel_get_function_groups, PINCTRL_INTEL); 411 412 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, 413 unsigned int function, unsigned int group) 414 { 415 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 416 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 417 int i; 418 419 guard(raw_spinlock_irqsave)(&pctrl->lock); 420 421 /* 422 * All pins in the groups needs to be accessible and writable 423 * before we can enable the mux for this group. 424 */ 425 for (i = 0; i < grp->grp.npins; i++) { 426 if (!intel_pad_usable(pctrl, grp->grp.pins[i])) 427 return -EBUSY; 428 } 429 430 /* Now enable the mux setting for each pin in the group */ 431 for (i = 0; i < grp->grp.npins; i++) { 432 void __iomem *padcfg0; 433 u32 value, pmode; 434 435 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0); 436 437 value = readl(padcfg0); 438 value &= ~PADCFG0_PMODE_MASK; 439 440 if (grp->modes) 441 pmode = grp->modes[i]; 442 else 443 pmode = grp->mode; 444 445 value |= pmode << PADCFG0_PMODE_SHIFT; 446 writel(value, padcfg0); 447 } 448 449 return 0; 450 } 451 452 /** 453 * enum - Possible pad physical connections 454 * @PAD_CONNECT_NONE: pad is fully disconnected 455 * @PAD_CONNECT_INPUT: pad is in input only mode 456 * @PAD_CONNECT_OUTPUT: pad is in output only mode 457 * @PAD_CONNECT_FULL: pad is fully connected 458 */ 459 enum { 460 PAD_CONNECT_NONE = 0, 461 PAD_CONNECT_INPUT = 1, 462 PAD_CONNECT_OUTPUT = 2, 463 PAD_CONNECT_FULL = PAD_CONNECT_INPUT | PAD_CONNECT_OUTPUT, 464 }; 465 466 static int __intel_gpio_get_direction(u32 value) 467 { 468 switch ((value & PADCFG0_GPIODIS_MASK) >> PADCFG0_GPIODIS_SHIFT) { 469 case PADCFG0_GPIODIS_FULL: 470 return PAD_CONNECT_NONE; 471 case PADCFG0_GPIODIS_OUTPUT: 472 return PAD_CONNECT_INPUT; 473 case PADCFG0_GPIODIS_INPUT: 474 return PAD_CONNECT_OUTPUT; 475 case PADCFG0_GPIODIS_NONE: 476 return PAD_CONNECT_FULL; 477 default: 478 return -ENOTSUPP; 479 }; 480 } 481 482 static u32 __intel_gpio_set_direction(u32 value, bool input, bool output) 483 { 484 if (input) 485 value &= ~PADCFG0_GPIORXDIS; 486 else 487 value |= PADCFG0_GPIORXDIS; 488 489 if (output) 490 value &= ~PADCFG0_GPIOTXDIS; 491 else 492 value |= PADCFG0_GPIOTXDIS; 493 494 return value; 495 } 496 497 static int __intel_gpio_get_gpio_mode(u32 value) 498 { 499 return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 500 } 501 502 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) 503 { 504 return __intel_gpio_get_gpio_mode(readl(padcfg0)); 505 } 506 507 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) 508 { 509 u32 value; 510 511 value = readl(padcfg0); 512 513 /* Put the pad into GPIO mode */ 514 value &= ~PADCFG0_PMODE_MASK; 515 value |= PADCFG0_PMODE_GPIO; 516 517 /* Disable TX buffer and enable RX (this will be input) */ 518 value = __intel_gpio_set_direction(value, true, false); 519 520 /* Disable SCI/SMI/NMI generation */ 521 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 522 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 523 524 writel(value, padcfg0); 525 } 526 527 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 528 struct pinctrl_gpio_range *range, 529 unsigned int pin) 530 { 531 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 532 void __iomem *padcfg0; 533 534 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 535 536 guard(raw_spinlock_irqsave)(&pctrl->lock); 537 538 if (!intel_pad_owned_by_host(pctrl, pin)) 539 return -EBUSY; 540 541 if (!intel_pad_is_unlocked(pctrl, pin)) 542 return 0; 543 544 /* 545 * If pin is already configured in GPIO mode, we assume that 546 * firmware provides correct settings. In such case we avoid 547 * potential glitches on the pin. Otherwise, for the pin in 548 * alternative mode, consumer has to supply respective flags. 549 */ 550 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) 551 return 0; 552 553 intel_gpio_set_gpio_mode(padcfg0); 554 555 return 0; 556 } 557 558 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 559 struct pinctrl_gpio_range *range, 560 unsigned int pin, bool input) 561 { 562 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 563 void __iomem *padcfg0; 564 u32 value; 565 566 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 567 568 guard(raw_spinlock_irqsave)(&pctrl->lock); 569 570 value = readl(padcfg0); 571 if (input) 572 value = __intel_gpio_set_direction(value, true, false); 573 else 574 value = __intel_gpio_set_direction(value, false, true); 575 writel(value, padcfg0); 576 577 return 0; 578 } 579 580 static const struct pinmux_ops intel_pinmux_ops = { 581 .get_functions_count = intel_get_functions_count, 582 .get_function_name = intel_get_function_name, 583 .get_function_groups = intel_get_function_groups, 584 .set_mux = intel_pinmux_set_mux, 585 .gpio_request_enable = intel_gpio_request_enable, 586 .gpio_set_direction = intel_gpio_set_direction, 587 }; 588 589 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin, 590 enum pin_config_param param, u32 *arg) 591 { 592 void __iomem *padcfg1; 593 u32 value, term; 594 595 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 596 597 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) 598 value = readl(padcfg1); 599 600 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 601 602 switch (param) { 603 case PIN_CONFIG_BIAS_DISABLE: 604 if (term) 605 return -EINVAL; 606 break; 607 608 case PIN_CONFIG_BIAS_PULL_UP: 609 if (!term || !(value & PADCFG1_TERM_UP)) 610 return -EINVAL; 611 612 switch (term) { 613 case PADCFG1_TERM_833: 614 *arg = 833; 615 break; 616 case PADCFG1_TERM_1K: 617 *arg = 1000; 618 break; 619 case PADCFG1_TERM_4K: 620 *arg = 4000; 621 break; 622 case PADCFG1_TERM_5K: 623 *arg = 5000; 624 break; 625 case PADCFG1_TERM_20K: 626 *arg = 20000; 627 break; 628 } 629 630 break; 631 632 case PIN_CONFIG_BIAS_PULL_DOWN: { 633 const struct intel_community *community = intel_get_community(pctrl, pin); 634 635 if (!term || value & PADCFG1_TERM_UP) 636 return -EINVAL; 637 638 switch (term) { 639 case PADCFG1_TERM_833: 640 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 641 return -EINVAL; 642 *arg = 833; 643 break; 644 case PADCFG1_TERM_1K: 645 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 646 return -EINVAL; 647 *arg = 1000; 648 break; 649 case PADCFG1_TERM_4K: 650 *arg = 4000; 651 break; 652 case PADCFG1_TERM_5K: 653 *arg = 5000; 654 break; 655 case PADCFG1_TERM_20K: 656 *arg = 20000; 657 break; 658 } 659 660 break; 661 } 662 663 default: 664 return -EINVAL; 665 } 666 667 return 0; 668 } 669 670 static int intel_config_get_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin, 671 enum pin_config_param param, u32 *arg) 672 { 673 void __iomem *padcfg0; 674 u32 value; 675 676 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 677 678 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) 679 value = readl(padcfg0); 680 681 if (__intel_gpio_get_direction(value) != PAD_CONNECT_NONE) 682 return -EINVAL; 683 684 return 0; 685 } 686 687 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin, 688 enum pin_config_param param, u32 *arg) 689 { 690 void __iomem *padcfg2; 691 unsigned long v; 692 u32 value2; 693 694 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 695 if (!padcfg2) 696 return -ENOTSUPP; 697 698 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) 699 value2 = readl(padcfg2); 700 701 if (!(value2 & PADCFG2_DEBEN)) 702 return -EINVAL; 703 704 v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; 705 *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC; 706 707 return 0; 708 } 709 710 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 711 unsigned long *config) 712 { 713 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 714 enum pin_config_param param = pinconf_to_config_param(*config); 715 u32 arg = 0; 716 int ret; 717 718 if (!intel_pad_owned_by_host(pctrl, pin)) 719 return -ENOTSUPP; 720 721 switch (param) { 722 case PIN_CONFIG_BIAS_DISABLE: 723 case PIN_CONFIG_BIAS_PULL_UP: 724 case PIN_CONFIG_BIAS_PULL_DOWN: 725 ret = intel_config_get_pull(pctrl, pin, param, &arg); 726 if (ret) 727 return ret; 728 break; 729 730 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 731 ret = intel_config_get_high_impedance(pctrl, pin, param, &arg); 732 if (ret) 733 return ret; 734 break; 735 736 case PIN_CONFIG_INPUT_DEBOUNCE: 737 ret = intel_config_get_debounce(pctrl, pin, param, &arg); 738 if (ret) 739 return ret; 740 break; 741 742 default: 743 return -ENOTSUPP; 744 } 745 746 *config = pinconf_to_config_packed(param, arg); 747 return 0; 748 } 749 750 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 751 unsigned long config) 752 { 753 unsigned int param = pinconf_to_config_param(config); 754 unsigned int arg = pinconf_to_config_argument(config); 755 u32 term = 0, up = 0, value; 756 void __iomem *padcfg1; 757 758 switch (param) { 759 case PIN_CONFIG_BIAS_DISABLE: 760 break; 761 762 case PIN_CONFIG_BIAS_PULL_UP: 763 switch (arg) { 764 case 20000: 765 term = PADCFG1_TERM_20K; 766 break; 767 case 1: /* Set default strength value in case none is given */ 768 case 5000: 769 term = PADCFG1_TERM_5K; 770 break; 771 case 4000: 772 term = PADCFG1_TERM_4K; 773 break; 774 case 1000: 775 term = PADCFG1_TERM_1K; 776 break; 777 case 833: 778 term = PADCFG1_TERM_833; 779 break; 780 default: 781 return -EINVAL; 782 } 783 784 up = PADCFG1_TERM_UP; 785 break; 786 787 case PIN_CONFIG_BIAS_PULL_DOWN: { 788 const struct intel_community *community = intel_get_community(pctrl, pin); 789 790 switch (arg) { 791 case 20000: 792 term = PADCFG1_TERM_20K; 793 break; 794 case 1: /* Set default strength value in case none is given */ 795 case 5000: 796 term = PADCFG1_TERM_5K; 797 break; 798 case 4000: 799 term = PADCFG1_TERM_4K; 800 break; 801 case 1000: 802 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 803 return -EINVAL; 804 term = PADCFG1_TERM_1K; 805 break; 806 case 833: 807 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 808 return -EINVAL; 809 term = PADCFG1_TERM_833; 810 break; 811 default: 812 return -EINVAL; 813 } 814 815 break; 816 } 817 818 default: 819 return -EINVAL; 820 } 821 822 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 823 824 guard(raw_spinlock_irqsave)(&pctrl->lock); 825 826 value = readl(padcfg1); 827 value = (value & ~PADCFG1_TERM_MASK) | (term << PADCFG1_TERM_SHIFT); 828 value = (value & ~PADCFG1_TERM_UP) | up; 829 writel(value, padcfg1); 830 831 return 0; 832 } 833 834 static void intel_gpio_set_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin) 835 { 836 void __iomem *padcfg0; 837 u32 value; 838 839 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 840 841 guard(raw_spinlock_irqsave)(&pctrl->lock); 842 843 value = readl(padcfg0); 844 value = __intel_gpio_set_direction(value, false, false); 845 writel(value, padcfg0); 846 } 847 848 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, 849 unsigned int pin, unsigned int debounce) 850 { 851 void __iomem *padcfg0, *padcfg2; 852 u32 value0, value2; 853 unsigned long v; 854 855 if (debounce) { 856 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC); 857 if (v < 3 || v > 15) 858 return -EINVAL; 859 } else { 860 v = 0; 861 } 862 863 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 864 if (!padcfg2) 865 return -ENOTSUPP; 866 867 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 868 869 guard(raw_spinlock_irqsave)(&pctrl->lock); 870 871 value0 = readl(padcfg0); 872 value2 = readl(padcfg2); 873 874 value2 = (value2 & ~PADCFG2_DEBOUNCE_MASK) | (v << PADCFG2_DEBOUNCE_SHIFT); 875 if (v) { 876 /* Enable glitch filter and debouncer */ 877 value0 |= PADCFG0_PREGFRXSEL; 878 value2 |= PADCFG2_DEBEN; 879 } else { 880 /* Disable glitch filter and debouncer */ 881 value0 &= ~PADCFG0_PREGFRXSEL; 882 value2 &= ~PADCFG2_DEBEN; 883 } 884 885 writel(value0, padcfg0); 886 writel(value2, padcfg2); 887 888 return 0; 889 } 890 891 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 892 unsigned long *configs, unsigned int nconfigs) 893 { 894 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 895 int i, ret; 896 897 if (!intel_pad_usable(pctrl, pin)) 898 return -ENOTSUPP; 899 900 for (i = 0; i < nconfigs; i++) { 901 switch (pinconf_to_config_param(configs[i])) { 902 case PIN_CONFIG_BIAS_DISABLE: 903 case PIN_CONFIG_BIAS_PULL_UP: 904 case PIN_CONFIG_BIAS_PULL_DOWN: 905 ret = intel_config_set_pull(pctrl, pin, configs[i]); 906 if (ret) 907 return ret; 908 break; 909 910 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 911 intel_gpio_set_high_impedance(pctrl, pin); 912 break; 913 914 case PIN_CONFIG_INPUT_DEBOUNCE: 915 ret = intel_config_set_debounce(pctrl, pin, 916 pinconf_to_config_argument(configs[i])); 917 if (ret) 918 return ret; 919 break; 920 921 default: 922 return -ENOTSUPP; 923 } 924 } 925 926 return 0; 927 } 928 929 static const struct pinconf_ops intel_pinconf_ops = { 930 .is_generic = true, 931 .pin_config_get = intel_config_get, 932 .pin_config_set = intel_config_set, 933 }; 934 935 static const struct pinctrl_desc intel_pinctrl_desc = { 936 .pctlops = &intel_pinctrl_ops, 937 .pmxops = &intel_pinmux_ops, 938 .confops = &intel_pinconf_ops, 939 .owner = THIS_MODULE, 940 }; 941 942 /** 943 * intel_gpio_to_pin() - Translate from GPIO offset to pin number 944 * @pctrl: Pinctrl structure 945 * @offset: GPIO offset from gpiolib 946 * @community: Community is filled here if not %NULL 947 * @padgrp: Pad group is filled here if not %NULL 948 * 949 * When coming through gpiolib irqchip, the GPIO offset is not 950 * automatically translated to pinctrl pin number. This function can be 951 * used to find out the corresponding pinctrl pin. 952 * 953 * Return: a pin number and pointers to the community and pad group, which 954 * the pin belongs to, or negative error code if translation can't be done. 955 */ 956 static int intel_gpio_to_pin(const struct intel_pinctrl *pctrl, unsigned int offset, 957 const struct intel_community **community, 958 const struct intel_padgroup **padgrp) 959 { 960 const struct intel_community *comm; 961 const struct intel_padgroup *grp; 962 963 for_each_intel_gpio_group(pctrl, comm, grp) { 964 if (offset >= grp->gpio_base && offset < grp->gpio_base + grp->size) { 965 if (community) 966 *community = comm; 967 if (padgrp) 968 *padgrp = grp; 969 970 return grp->base + offset - grp->gpio_base; 971 } 972 } 973 974 return -EINVAL; 975 } 976 977 /** 978 * intel_pin_to_gpio() - Translate from pin number to GPIO offset 979 * @pctrl: Pinctrl structure 980 * @pin: pin number 981 * 982 * Translate the pin number of pinctrl to GPIO offset 983 * 984 * Return: a GPIO offset, or negative error code if translation can't be done. 985 */ 986 static int intel_pin_to_gpio(const struct intel_pinctrl *pctrl, int pin) 987 { 988 const struct intel_community *community; 989 const struct intel_padgroup *padgrp; 990 991 community = intel_get_community(pctrl, pin); 992 if (!community) 993 return -EINVAL; 994 995 padgrp = intel_community_get_padgroup(community, pin); 996 if (!padgrp) 997 return -EINVAL; 998 999 return pin - padgrp->base + padgrp->gpio_base; 1000 } 1001 1002 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) 1003 { 1004 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1005 void __iomem *reg; 1006 u32 padcfg0; 1007 int pin; 1008 1009 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 1010 if (pin < 0) 1011 return -EINVAL; 1012 1013 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1014 if (!reg) 1015 return -EINVAL; 1016 1017 padcfg0 = readl(reg); 1018 if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT) 1019 return !!(padcfg0 & PADCFG0_GPIOTXSTATE); 1020 1021 return !!(padcfg0 & PADCFG0_GPIORXSTATE); 1022 } 1023 1024 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, 1025 int value) 1026 { 1027 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1028 void __iomem *reg; 1029 u32 padcfg0; 1030 int pin; 1031 1032 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 1033 if (pin < 0) 1034 return; 1035 1036 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1037 if (!reg) 1038 return; 1039 1040 guard(raw_spinlock_irqsave)(&pctrl->lock); 1041 1042 padcfg0 = readl(reg); 1043 if (value) 1044 padcfg0 |= PADCFG0_GPIOTXSTATE; 1045 else 1046 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 1047 writel(padcfg0, reg); 1048 } 1049 1050 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1051 { 1052 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1053 void __iomem *reg; 1054 u32 padcfg0; 1055 int pin; 1056 1057 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 1058 if (pin < 0) 1059 return -EINVAL; 1060 1061 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1062 if (!reg) 1063 return -EINVAL; 1064 1065 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) 1066 padcfg0 = readl(reg); 1067 1068 if (padcfg0 & PADCFG0_PMODE_MASK) 1069 return -EINVAL; 1070 1071 if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT) 1072 return GPIO_LINE_DIRECTION_OUT; 1073 1074 return GPIO_LINE_DIRECTION_IN; 1075 } 1076 1077 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1078 { 1079 return pinctrl_gpio_direction_input(chip, offset); 1080 } 1081 1082 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 1083 int value) 1084 { 1085 intel_gpio_set(chip, offset, value); 1086 return pinctrl_gpio_direction_output(chip, offset); 1087 } 1088 1089 static const struct gpio_chip intel_gpio_chip = { 1090 .owner = THIS_MODULE, 1091 .request = gpiochip_generic_request, 1092 .free = gpiochip_generic_free, 1093 .get_direction = intel_gpio_get_direction, 1094 .direction_input = intel_gpio_direction_input, 1095 .direction_output = intel_gpio_direction_output, 1096 .get = intel_gpio_get, 1097 .set = intel_gpio_set, 1098 .set_config = gpiochip_generic_config, 1099 }; 1100 1101 static void intel_gpio_irq_ack(struct irq_data *d) 1102 { 1103 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1104 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1105 const struct intel_community *community; 1106 const struct intel_padgroup *padgrp; 1107 int pin; 1108 1109 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 1110 if (pin >= 0) { 1111 unsigned int gpp, gpp_offset; 1112 void __iomem *is; 1113 1114 gpp = padgrp->reg_num; 1115 gpp_offset = padgroup_offset(padgrp, pin); 1116 1117 is = community->regs + community->is_offset + gpp * 4; 1118 1119 guard(raw_spinlock)(&pctrl->lock); 1120 1121 writel(BIT(gpp_offset), is); 1122 } 1123 } 1124 1125 static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) 1126 { 1127 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1128 const struct intel_community *community; 1129 const struct intel_padgroup *padgrp; 1130 int pin; 1131 1132 pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp); 1133 if (pin >= 0) { 1134 unsigned int gpp, gpp_offset; 1135 void __iomem *reg, *is; 1136 u32 value; 1137 1138 gpp = padgrp->reg_num; 1139 gpp_offset = padgroup_offset(padgrp, pin); 1140 1141 reg = community->regs + community->ie_offset + gpp * 4; 1142 is = community->regs + community->is_offset + gpp * 4; 1143 1144 guard(raw_spinlock_irqsave)(&pctrl->lock); 1145 1146 /* Clear interrupt status first to avoid unexpected interrupt */ 1147 writel(BIT(gpp_offset), is); 1148 1149 value = readl(reg); 1150 if (mask) 1151 value &= ~BIT(gpp_offset); 1152 else 1153 value |= BIT(gpp_offset); 1154 writel(value, reg); 1155 } 1156 } 1157 1158 static void intel_gpio_irq_mask(struct irq_data *d) 1159 { 1160 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1161 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1162 1163 intel_gpio_irq_mask_unmask(gc, hwirq, true); 1164 gpiochip_disable_irq(gc, hwirq); 1165 } 1166 1167 static void intel_gpio_irq_unmask(struct irq_data *d) 1168 { 1169 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1170 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1171 1172 gpiochip_enable_irq(gc, hwirq); 1173 intel_gpio_irq_mask_unmask(gc, hwirq, false); 1174 } 1175 1176 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) 1177 { 1178 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1179 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1180 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1181 u32 rxevcfg, rxinv, value; 1182 void __iomem *reg; 1183 1184 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1185 if (!reg) 1186 return -EINVAL; 1187 1188 /* 1189 * If the pin is in ACPI mode it is still usable as a GPIO but it 1190 * cannot be used as IRQ because GPI_IS status bit will not be 1191 * updated by the host controller hardware. 1192 */ 1193 if (intel_pad_acpi_mode(pctrl, pin)) { 1194 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 1195 return -EPERM; 1196 } 1197 1198 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 1199 rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH; 1200 } else if (type & IRQ_TYPE_EDGE_FALLING) { 1201 rxevcfg = PADCFG0_RXEVCFG_EDGE; 1202 } else if (type & IRQ_TYPE_EDGE_RISING) { 1203 rxevcfg = PADCFG0_RXEVCFG_EDGE; 1204 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1205 rxevcfg = PADCFG0_RXEVCFG_LEVEL; 1206 } else { 1207 rxevcfg = PADCFG0_RXEVCFG_DISABLED; 1208 } 1209 1210 if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) 1211 rxinv = PADCFG0_RXINV; 1212 else 1213 rxinv = 0; 1214 1215 guard(raw_spinlock_irqsave)(&pctrl->lock); 1216 1217 intel_gpio_set_gpio_mode(reg); 1218 1219 value = readl(reg); 1220 1221 value = (value & ~PADCFG0_RXEVCFG_MASK) | rxevcfg; 1222 value = (value & ~PADCFG0_RXINV) | rxinv; 1223 1224 writel(value, reg); 1225 1226 if (type & IRQ_TYPE_EDGE_BOTH) 1227 irq_set_handler_locked(d, handle_edge_irq); 1228 else if (type & IRQ_TYPE_LEVEL_MASK) 1229 irq_set_handler_locked(d, handle_level_irq); 1230 1231 return 0; 1232 } 1233 1234 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 1235 { 1236 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1237 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1238 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1239 1240 if (on) 1241 enable_irq_wake(pctrl->irq); 1242 else 1243 disable_irq_wake(pctrl->irq); 1244 1245 dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin); 1246 return 0; 1247 } 1248 1249 static const struct irq_chip intel_gpio_irq_chip = { 1250 .name = "intel-gpio", 1251 .irq_ack = intel_gpio_irq_ack, 1252 .irq_mask = intel_gpio_irq_mask, 1253 .irq_unmask = intel_gpio_irq_unmask, 1254 .irq_set_type = intel_gpio_irq_type, 1255 .irq_set_wake = intel_gpio_irq_wake, 1256 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 1257 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1258 }; 1259 1260 static irqreturn_t intel_gpio_irq(int irq, void *data) 1261 { 1262 const struct intel_community *community; 1263 const struct intel_padgroup *padgrp; 1264 struct intel_pinctrl *pctrl = data; 1265 int ret = 0; 1266 1267 /* Need to check all communities for pending interrupts */ 1268 for_each_intel_pad_group(pctrl, community, padgrp) { 1269 struct gpio_chip *gc = &pctrl->chip; 1270 unsigned long pending, enabled; 1271 unsigned int gpp, gpp_offset; 1272 void __iomem *reg, *is; 1273 1274 gpp = padgrp->reg_num; 1275 1276 reg = community->regs + community->ie_offset + gpp * 4; 1277 is = community->regs + community->is_offset + gpp * 4; 1278 1279 scoped_guard(raw_spinlock, &pctrl->lock) { 1280 pending = readl(is); 1281 enabled = readl(reg); 1282 } 1283 1284 /* Only interrupts that are enabled */ 1285 pending &= enabled; 1286 1287 for_each_set_bit(gpp_offset, &pending, padgrp->size) 1288 generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset); 1289 1290 ret += pending ? 1 : 0; 1291 } 1292 1293 return IRQ_RETVAL(ret); 1294 } 1295 1296 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1297 { 1298 const struct intel_community *community; 1299 1300 for_each_intel_pin_community(pctrl, community) { 1301 void __iomem *reg, *is; 1302 unsigned int gpp; 1303 1304 for (gpp = 0; gpp < community->ngpps; gpp++) { 1305 reg = community->regs + community->ie_offset + gpp * 4; 1306 is = community->regs + community->is_offset + gpp * 4; 1307 1308 /* Mask and clear all interrupts */ 1309 writel(0, reg); 1310 writel(0xffff, is); 1311 } 1312 } 1313 } 1314 1315 static int intel_gpio_irq_init_hw(struct gpio_chip *gc) 1316 { 1317 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1318 1319 /* 1320 * Make sure the interrupt lines are in a proper state before 1321 * further configuration. 1322 */ 1323 intel_gpio_irq_init(pctrl); 1324 1325 return 0; 1326 } 1327 1328 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) 1329 { 1330 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1331 const struct intel_community *community; 1332 const struct intel_padgroup *grp; 1333 int ret; 1334 1335 for_each_intel_gpio_group(pctrl, community, grp) { 1336 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1337 grp->gpio_base, grp->base, 1338 grp->size); 1339 if (ret) { 1340 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1341 return ret; 1342 } 1343 } 1344 1345 return 0; 1346 } 1347 1348 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1349 { 1350 const struct intel_community *community; 1351 const struct intel_padgroup *grp; 1352 unsigned int ngpio = 0; 1353 1354 for_each_intel_gpio_group(pctrl, community, grp) { 1355 if (grp->gpio_base + grp->size > ngpio) 1356 ngpio = grp->gpio_base + grp->size; 1357 } 1358 1359 return ngpio; 1360 } 1361 1362 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1363 { 1364 int ret; 1365 struct gpio_irq_chip *girq; 1366 1367 pctrl->chip = intel_gpio_chip; 1368 1369 /* Setup GPIO chip */ 1370 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); 1371 pctrl->chip.label = dev_name(pctrl->dev); 1372 pctrl->chip.parent = pctrl->dev; 1373 pctrl->chip.base = -1; 1374 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; 1375 pctrl->irq = irq; 1376 1377 /* 1378 * On some platforms several GPIO controllers share the same interrupt 1379 * line. 1380 */ 1381 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1382 IRQF_SHARED | IRQF_NO_THREAD, 1383 dev_name(pctrl->dev), pctrl); 1384 if (ret) { 1385 dev_err(pctrl->dev, "failed to request interrupt\n"); 1386 return ret; 1387 } 1388 1389 /* Setup IRQ chip */ 1390 girq = &pctrl->chip.irq; 1391 gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip); 1392 /* This will let us handle the IRQ in the driver */ 1393 girq->parent_handler = NULL; 1394 girq->num_parents = 0; 1395 girq->default_type = IRQ_TYPE_NONE; 1396 girq->handler = handle_bad_irq; 1397 girq->init_hw = intel_gpio_irq_init_hw; 1398 1399 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1400 if (ret) { 1401 dev_err(pctrl->dev, "failed to register gpiochip\n"); 1402 return ret; 1403 } 1404 1405 return 0; 1406 } 1407 1408 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl, 1409 struct intel_community *community) 1410 { 1411 struct intel_padgroup *gpps; 1412 unsigned int padown_num = 0; 1413 size_t i, ngpps = community->ngpps; 1414 1415 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1416 if (!gpps) 1417 return -ENOMEM; 1418 1419 for (i = 0; i < ngpps; i++) { 1420 gpps[i] = community->gpps[i]; 1421 1422 if (gpps[i].size > INTEL_PINCTRL_MAX_GPP_SIZE) 1423 return -EINVAL; 1424 1425 /* Special treatment for GPIO base */ 1426 switch (gpps[i].gpio_base) { 1427 case INTEL_GPIO_BASE_MATCH: 1428 gpps[i].gpio_base = gpps[i].base; 1429 break; 1430 case INTEL_GPIO_BASE_ZERO: 1431 gpps[i].gpio_base = 0; 1432 break; 1433 case INTEL_GPIO_BASE_NOMAP: 1434 break; 1435 default: 1436 break; 1437 } 1438 1439 gpps[i].padown_num = padown_num; 1440 padown_num += DIV_ROUND_UP(gpps[i].size * 4, INTEL_PINCTRL_MAX_GPP_SIZE); 1441 } 1442 1443 community->gpps = gpps; 1444 1445 return 0; 1446 } 1447 1448 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl, 1449 struct intel_community *community) 1450 { 1451 struct intel_padgroup *gpps; 1452 unsigned int npins = community->npins; 1453 unsigned int padown_num = 0; 1454 size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size); 1455 1456 if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE) 1457 return -EINVAL; 1458 1459 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1460 if (!gpps) 1461 return -ENOMEM; 1462 1463 for (i = 0; i < ngpps; i++) { 1464 unsigned int gpp_size = community->gpp_size; 1465 1466 gpps[i].reg_num = i; 1467 gpps[i].base = community->pin_base + i * gpp_size; 1468 gpps[i].size = min(gpp_size, npins); 1469 npins -= gpps[i].size; 1470 1471 gpps[i].gpio_base = gpps[i].base; 1472 gpps[i].padown_num = padown_num; 1473 1474 padown_num += community->gpp_num_padown_regs; 1475 } 1476 1477 community->ngpps = ngpps; 1478 community->gpps = gpps; 1479 1480 return 0; 1481 } 1482 1483 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 1484 { 1485 #ifdef CONFIG_PM_SLEEP 1486 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 1487 struct intel_community_context *communities; 1488 struct intel_pad_context *pads; 1489 int i; 1490 1491 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 1492 if (!pads) 1493 return -ENOMEM; 1494 1495 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 1496 sizeof(*communities), GFP_KERNEL); 1497 if (!communities) 1498 return -ENOMEM; 1499 1500 1501 for (i = 0; i < pctrl->ncommunities; i++) { 1502 struct intel_community *community = &pctrl->communities[i]; 1503 u32 *intmask, *hostown; 1504 1505 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1506 sizeof(*intmask), GFP_KERNEL); 1507 if (!intmask) 1508 return -ENOMEM; 1509 1510 communities[i].intmask = intmask; 1511 1512 hostown = devm_kcalloc(pctrl->dev, community->ngpps, 1513 sizeof(*hostown), GFP_KERNEL); 1514 if (!hostown) 1515 return -ENOMEM; 1516 1517 communities[i].hostown = hostown; 1518 } 1519 1520 pctrl->context.pads = pads; 1521 pctrl->context.communities = communities; 1522 #endif 1523 1524 return 0; 1525 } 1526 1527 static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, 1528 struct intel_community *community) 1529 { 1530 static const struct pwm_lpss_boardinfo info = { 1531 .clk_rate = 19200000, 1532 .npwm = 1, 1533 .base_unit_bits = 22, 1534 .bypass = true, 1535 }; 1536 struct pwm_chip *chip; 1537 1538 if (!(community->features & PINCTRL_FEATURE_PWM)) 1539 return 0; 1540 1541 if (!IS_REACHABLE(CONFIG_PWM_LPSS)) 1542 return 0; 1543 1544 chip = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); 1545 return PTR_ERR_OR_ZERO(chip); 1546 } 1547 1548 int intel_pinctrl_probe(struct platform_device *pdev, 1549 const struct intel_pinctrl_soc_data *soc_data) 1550 { 1551 struct device *dev = &pdev->dev; 1552 struct intel_pinctrl *pctrl; 1553 int i, ret, irq; 1554 1555 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 1556 if (!pctrl) 1557 return -ENOMEM; 1558 1559 pctrl->dev = dev; 1560 pctrl->soc = soc_data; 1561 raw_spin_lock_init(&pctrl->lock); 1562 1563 /* 1564 * Make a copy of the communities which we can use to hold pointers 1565 * to the registers. 1566 */ 1567 pctrl->ncommunities = pctrl->soc->ncommunities; 1568 pctrl->communities = devm_kcalloc(dev, pctrl->ncommunities, 1569 sizeof(*pctrl->communities), GFP_KERNEL); 1570 if (!pctrl->communities) 1571 return -ENOMEM; 1572 1573 for (i = 0; i < pctrl->ncommunities; i++) { 1574 struct intel_community *community = &pctrl->communities[i]; 1575 void __iomem *regs; 1576 u32 offset; 1577 u32 value; 1578 1579 *community = pctrl->soc->communities[i]; 1580 1581 regs = devm_platform_ioremap_resource(pdev, community->barno); 1582 if (IS_ERR(regs)) 1583 return PTR_ERR(regs); 1584 1585 /* 1586 * Determine community features based on the revision. 1587 * A value of all ones means the device is not present. 1588 */ 1589 value = readl(regs + REVID); 1590 if (value == ~0u) 1591 return -ENODEV; 1592 if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) { 1593 community->features |= PINCTRL_FEATURE_DEBOUNCE; 1594 community->features |= PINCTRL_FEATURE_1K_PD; 1595 } 1596 1597 /* Determine community features based on the capabilities */ 1598 offset = CAPLIST; 1599 do { 1600 value = readl(regs + offset); 1601 switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) { 1602 case CAPLIST_ID_GPIO_HW_INFO: 1603 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO; 1604 break; 1605 case CAPLIST_ID_PWM: 1606 community->features |= PINCTRL_FEATURE_PWM; 1607 break; 1608 case CAPLIST_ID_BLINK: 1609 community->features |= PINCTRL_FEATURE_BLINK; 1610 break; 1611 case CAPLIST_ID_EXP: 1612 community->features |= PINCTRL_FEATURE_EXP; 1613 break; 1614 default: 1615 break; 1616 } 1617 offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT; 1618 } while (offset); 1619 1620 dev_dbg(dev, "Community%d features: %#08x\n", i, community->features); 1621 1622 /* Read offset of the pad configuration registers */ 1623 offset = readl(regs + PADBAR); 1624 1625 community->regs = regs; 1626 community->pad_regs = regs + offset; 1627 1628 if (community->gpps) 1629 ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community); 1630 else 1631 ret = intel_pinctrl_add_padgroups_by_size(pctrl, community); 1632 if (ret) 1633 return ret; 1634 1635 ret = intel_pinctrl_probe_pwm(pctrl, community); 1636 if (ret) 1637 return ret; 1638 } 1639 1640 irq = platform_get_irq(pdev, 0); 1641 if (irq < 0) 1642 return irq; 1643 1644 ret = intel_pinctrl_pm_init(pctrl); 1645 if (ret) 1646 return ret; 1647 1648 pctrl->pctldesc = intel_pinctrl_desc; 1649 pctrl->pctldesc.name = dev_name(dev); 1650 pctrl->pctldesc.pins = pctrl->soc->pins; 1651 pctrl->pctldesc.npins = pctrl->soc->npins; 1652 1653 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); 1654 if (IS_ERR(pctrl->pctldev)) { 1655 dev_err(dev, "failed to register pinctrl driver\n"); 1656 return PTR_ERR(pctrl->pctldev); 1657 } 1658 1659 ret = intel_gpio_probe(pctrl, irq); 1660 if (ret) 1661 return ret; 1662 1663 platform_set_drvdata(pdev, pctrl); 1664 1665 return 0; 1666 } 1667 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe, PINCTRL_INTEL); 1668 1669 int intel_pinctrl_probe_by_hid(struct platform_device *pdev) 1670 { 1671 const struct intel_pinctrl_soc_data *data; 1672 1673 data = device_get_match_data(&pdev->dev); 1674 if (!data) 1675 return -ENODATA; 1676 1677 return intel_pinctrl_probe(pdev, data); 1678 } 1679 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_hid, PINCTRL_INTEL); 1680 1681 int intel_pinctrl_probe_by_uid(struct platform_device *pdev) 1682 { 1683 const struct intel_pinctrl_soc_data *data; 1684 1685 data = intel_pinctrl_get_soc_data(pdev); 1686 if (IS_ERR(data)) 1687 return PTR_ERR(data); 1688 1689 return intel_pinctrl_probe(pdev, data); 1690 } 1691 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, PINCTRL_INTEL); 1692 1693 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) 1694 { 1695 const struct intel_pinctrl_soc_data * const *table; 1696 const struct intel_pinctrl_soc_data *data; 1697 struct device *dev = &pdev->dev; 1698 1699 table = device_get_match_data(dev); 1700 if (table) { 1701 struct acpi_device *adev = ACPI_COMPANION(dev); 1702 unsigned int i; 1703 1704 for (i = 0; table[i]; i++) { 1705 if (acpi_dev_uid_match(adev, table[i]->uid)) 1706 break; 1707 } 1708 data = table[i]; 1709 } else { 1710 const struct platform_device_id *id; 1711 1712 id = platform_get_device_id(pdev); 1713 if (!id) 1714 return ERR_PTR(-ENODEV); 1715 1716 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data; 1717 data = table[pdev->id]; 1718 } 1719 1720 return data ?: ERR_PTR(-ENODATA); 1721 } 1722 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, PINCTRL_INTEL); 1723 1724 static bool __intel_gpio_is_direct_irq(u32 value) 1725 { 1726 return (value & PADCFG0_GPIROUTIOXAPIC) && 1727 (__intel_gpio_get_direction(value) == PAD_CONNECT_INPUT) && 1728 (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO); 1729 } 1730 1731 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) 1732 { 1733 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1734 u32 value; 1735 1736 if (!pd || !intel_pad_usable(pctrl, pin)) 1737 return false; 1738 1739 /* 1740 * Only restore the pin if it is actually in use by the kernel (or 1741 * by userspace). It is possible that some pins are used by the 1742 * BIOS during resume and those are not always locked down so leave 1743 * them alone. 1744 */ 1745 if (pd->mux_owner || pd->gpio_owner || 1746 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) 1747 return true; 1748 1749 /* 1750 * The firmware on some systems may configure GPIO pins to be 1751 * an interrupt source in so called "direct IRQ" mode. In such 1752 * cases the GPIO controller driver has no idea if those pins 1753 * are being used or not. At the same time, there is a known bug 1754 * in the firmwares that don't restore the pin settings correctly 1755 * after suspend, i.e. by an unknown reason the Rx value becomes 1756 * inverted. 1757 * 1758 * Hence, let's save and restore the pins that are configured 1759 * as GPIOs in the input mode with GPIROUTIOXAPIC bit set. 1760 * 1761 * See https://bugzilla.kernel.org/show_bug.cgi?id=214749. 1762 */ 1763 value = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 1764 if (__intel_gpio_is_direct_irq(value)) 1765 return true; 1766 1767 return false; 1768 } 1769 1770 static int intel_pinctrl_suspend_noirq(struct device *dev) 1771 { 1772 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1773 struct intel_community_context *communities; 1774 struct intel_pad_context *pads; 1775 int i; 1776 1777 pads = pctrl->context.pads; 1778 for (i = 0; i < pctrl->soc->npins; i++) { 1779 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1780 void __iomem *padcfg; 1781 u32 val; 1782 1783 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1784 continue; 1785 1786 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1787 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1788 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1789 pads[i].padcfg1 = val; 1790 1791 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1792 if (padcfg) 1793 pads[i].padcfg2 = readl(padcfg); 1794 } 1795 1796 communities = pctrl->context.communities; 1797 for (i = 0; i < pctrl->ncommunities; i++) { 1798 struct intel_community *community = &pctrl->communities[i]; 1799 void __iomem *base; 1800 unsigned int gpp; 1801 1802 base = community->regs + community->ie_offset; 1803 for (gpp = 0; gpp < community->ngpps; gpp++) 1804 communities[i].intmask[gpp] = readl(base + gpp * 4); 1805 1806 base = community->regs + community->hostown_offset; 1807 for (gpp = 0; gpp < community->ngpps; gpp++) 1808 communities[i].hostown[gpp] = readl(base + gpp * 4); 1809 } 1810 1811 return 0; 1812 } 1813 1814 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value) 1815 { 1816 u32 curr, updated; 1817 1818 curr = readl(reg); 1819 1820 updated = (curr & ~mask) | (value & mask); 1821 if (curr == updated) 1822 return false; 1823 1824 writel(updated, reg); 1825 return true; 1826 } 1827 1828 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, 1829 void __iomem *base, unsigned int gpp, u32 saved) 1830 { 1831 const struct intel_community *community = &pctrl->communities[c]; 1832 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1833 struct device *dev = pctrl->dev; 1834 const char *dummy; 1835 u32 requested = 0; 1836 unsigned int i; 1837 1838 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1839 return; 1840 1841 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy) 1842 requested |= BIT(i); 1843 1844 if (!intel_gpio_update_reg(base + gpp * 4, requested, saved)) 1845 return; 1846 1847 dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1848 } 1849 1850 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, 1851 void __iomem *base, unsigned int gpp, u32 saved) 1852 { 1853 struct device *dev = pctrl->dev; 1854 1855 if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved)) 1856 return; 1857 1858 dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1859 } 1860 1861 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, 1862 unsigned int reg, u32 saved) 1863 { 1864 u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0; 1865 unsigned int n = reg / sizeof(u32); 1866 struct device *dev = pctrl->dev; 1867 void __iomem *padcfg; 1868 1869 padcfg = intel_get_padcfg(pctrl, pin, reg); 1870 if (!padcfg) 1871 return; 1872 1873 if (!intel_gpio_update_reg(padcfg, ~mask, saved)) 1874 return; 1875 1876 dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg)); 1877 } 1878 1879 static int intel_pinctrl_resume_noirq(struct device *dev) 1880 { 1881 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1882 const struct intel_community_context *communities; 1883 const struct intel_pad_context *pads; 1884 int i; 1885 1886 /* Mask all interrupts */ 1887 intel_gpio_irq_init(pctrl); 1888 1889 pads = pctrl->context.pads; 1890 for (i = 0; i < pctrl->soc->npins; i++) { 1891 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1892 1893 if (!(intel_pinctrl_should_save(pctrl, desc->number) || 1894 /* 1895 * If the firmware mangled the register contents too much, 1896 * check the saved value for the Direct IRQ mode. 1897 */ 1898 __intel_gpio_is_direct_irq(pads[i].padcfg0))) 1899 continue; 1900 1901 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); 1902 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); 1903 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); 1904 } 1905 1906 communities = pctrl->context.communities; 1907 for (i = 0; i < pctrl->ncommunities; i++) { 1908 struct intel_community *community = &pctrl->communities[i]; 1909 void __iomem *base; 1910 unsigned int gpp; 1911 1912 base = community->regs + community->ie_offset; 1913 for (gpp = 0; gpp < community->ngpps; gpp++) 1914 intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]); 1915 1916 base = community->regs + community->hostown_offset; 1917 for (gpp = 0; gpp < community->ngpps; gpp++) 1918 intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]); 1919 } 1920 1921 return 0; 1922 } 1923 1924 EXPORT_NS_GPL_DEV_SLEEP_PM_OPS(intel_pinctrl_pm_ops, PINCTRL_INTEL) = { 1925 NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, intel_pinctrl_resume_noirq) 1926 }; 1927 1928 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1929 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1930 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1931 MODULE_LICENSE("GPL v2"); 1932