1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel pinctrl/GPIO core driver. 4 * 5 * Copyright (C) 2015 Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/cleanup.h> 12 #include <linux/export.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/interrupt.h> 15 #include <linux/log2.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/property.h> 19 #include <linux/seq_file.h> 20 #include <linux/string_helpers.h> 21 #include <linux/time.h> 22 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinmux.h> 28 29 #include <linux/platform_data/x86/pwm-lpss.h> 30 31 #include "../core.h" 32 #include "pinctrl-intel.h" 33 34 /* Offset from regs */ 35 #define REVID 0x000 36 #define REVID_SHIFT 16 37 #define REVID_MASK GENMASK(31, 16) 38 39 #define CAPLIST 0x004 40 #define CAPLIST_ID_SHIFT 16 41 #define CAPLIST_ID_MASK GENMASK(23, 16) 42 #define CAPLIST_ID_GPIO_HW_INFO 1 43 #define CAPLIST_ID_PWM 2 44 #define CAPLIST_ID_BLINK 3 45 #define CAPLIST_ID_EXP 4 46 #define CAPLIST_NEXT_SHIFT 0 47 #define CAPLIST_NEXT_MASK GENMASK(15, 0) 48 49 #define PADBAR 0x00c 50 51 #define PADOWN_BITS 4 52 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 53 #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) 54 #define PADOWN_GPP(p) ((p) / 8) 55 56 /* Offset from pad_regs */ 57 #define PADCFG0 0x000 58 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25) 59 #define PADCFG0_RXEVCFG_LEVEL (0 << 25) 60 #define PADCFG0_RXEVCFG_EDGE (1 << 25) 61 #define PADCFG0_RXEVCFG_DISABLED (2 << 25) 62 #define PADCFG0_RXEVCFG_EDGE_BOTH (3 << 25) 63 #define PADCFG0_PREGFRXSEL BIT(24) 64 #define PADCFG0_RXINV BIT(23) 65 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 66 #define PADCFG0_GPIROUTSCI BIT(19) 67 #define PADCFG0_GPIROUTSMI BIT(18) 68 #define PADCFG0_GPIROUTNMI BIT(17) 69 #define PADCFG0_PMODE_SHIFT 10 70 #define PADCFG0_PMODE_MASK GENMASK(13, 10) 71 #define PADCFG0_PMODE_GPIO 0 72 #define PADCFG0_GPIODIS_SHIFT 8 73 #define PADCFG0_GPIODIS_MASK GENMASK(9, 8) 74 #define PADCFG0_GPIODIS_NONE 0 75 #define PADCFG0_GPIODIS_OUTPUT 1 76 #define PADCFG0_GPIODIS_INPUT 2 77 #define PADCFG0_GPIODIS_FULL 3 78 #define PADCFG0_GPIORXDIS BIT(9) 79 #define PADCFG0_GPIOTXDIS BIT(8) 80 #define PADCFG0_GPIORXSTATE BIT(1) 81 #define PADCFG0_GPIOTXSTATE BIT(0) 82 83 #define PADCFG1 0x004 84 #define PADCFG1_TERM_UP BIT(13) 85 #define PADCFG1_TERM_SHIFT 10 86 #define PADCFG1_TERM_MASK GENMASK(12, 10) 87 /* 88 * Bit 0 Bit 1 Bit 2 Value, Ohms 89 * 90 * 0 0 0 - 91 * 0 0 1 20000 92 * 0 1 0 5000 93 * 0 1 1 ~4000 94 * 1 0 0 1000 (if supported) 95 * 1 0 1 ~952 (if supported) 96 * 1 1 0 ~833 (if supported) 97 * 1 1 1 ~800 (if supported) 98 */ 99 #define PADCFG1_TERM_20K BIT(2) 100 #define PADCFG1_TERM_5K BIT(1) 101 #define PADCFG1_TERM_4K (BIT(2) | BIT(1)) 102 #define PADCFG1_TERM_1K BIT(0) 103 #define PADCFG1_TERM_952 (BIT(2) | BIT(0)) 104 #define PADCFG1_TERM_833 (BIT(1) | BIT(0)) 105 #define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0)) 106 107 #define PADCFG2 0x008 108 #define PADCFG2_DEBOUNCE_SHIFT 1 109 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) 110 #define PADCFG2_DEBEN BIT(0) 111 112 #define DEBOUNCE_PERIOD_NSEC 31250 113 114 struct intel_pad_context { 115 u32 padcfg0; 116 u32 padcfg1; 117 u32 padcfg2; 118 }; 119 120 struct intel_community_context { 121 u32 *intmask; 122 u32 *hostown; 123 }; 124 125 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 126 #define padgroup_offset(g, p) ((p) - (g)->base) 127 128 #define for_each_intel_pin_community(pctrl, community) \ 129 for (unsigned int __ci = 0; \ 130 __ci < pctrl->ncommunities && (community = &pctrl->communities[__ci]); \ 131 __ci++) \ 132 133 #define for_each_intel_community_pad_group(community, grp) \ 134 for (unsigned int __gi = 0; \ 135 __gi < community->ngpps && (grp = &community->gpps[__gi]); \ 136 __gi++) \ 137 138 #define for_each_intel_pad_group(pctrl, community, grp) \ 139 for_each_intel_pin_community(pctrl, community) \ 140 for_each_intel_community_pad_group(community, grp) 141 142 #define for_each_intel_gpio_group(pctrl, community, grp) \ 143 for_each_intel_pad_group(pctrl, community, grp) \ 144 if (grp->gpio_base == INTEL_GPIO_BASE_NOMAP) {} else 145 146 const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl, 147 unsigned int pin) 148 { 149 const struct intel_community *community; 150 151 for_each_intel_pin_community(pctrl, community) { 152 if (pin >= community->pin_base && 153 pin < community->pin_base + community->npins) 154 return community; 155 } 156 157 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 158 return NULL; 159 } 160 EXPORT_SYMBOL_NS_GPL(intel_get_community, "PINCTRL_INTEL"); 161 162 static const struct intel_padgroup * 163 intel_community_get_padgroup(const struct intel_community *community, 164 unsigned int pin) 165 { 166 const struct intel_padgroup *padgrp; 167 168 for_each_intel_community_pad_group(community, padgrp) { 169 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) 170 return padgrp; 171 } 172 173 return NULL; 174 } 175 176 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, 177 unsigned int pin, unsigned int reg) 178 { 179 const struct intel_community *community; 180 unsigned int padno; 181 size_t nregs; 182 183 community = intel_get_community(pctrl, pin); 184 if (!community) 185 return NULL; 186 187 padno = pin_to_padno(community, pin); 188 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; 189 190 if (reg >= nregs * 4) 191 return NULL; 192 193 return community->pad_regs + reg + padno * nregs * 4; 194 } 195 196 static bool intel_pad_owned_by_host(const struct intel_pinctrl *pctrl, unsigned int pin) 197 { 198 const struct intel_community *community; 199 const struct intel_padgroup *padgrp; 200 unsigned int gpp, offset, gpp_offset; 201 void __iomem *padown; 202 203 community = intel_get_community(pctrl, pin); 204 if (!community) 205 return false; 206 207 /* If padown_offset is not provided, assume host ownership */ 208 padown = community->regs + community->padown_offset; 209 if (padown == community->regs) 210 return true; 211 212 /* New HW generations have extended PAD_OWN registers */ 213 if (community->features & PINCTRL_FEATURE_3BIT_PAD_OWN) 214 return !(readl(padown + pin_to_padno(community, pin) * 4) & 7); 215 216 padgrp = intel_community_get_padgroup(community, pin); 217 if (!padgrp) 218 return false; 219 220 gpp_offset = padgroup_offset(padgrp, pin); 221 gpp = PADOWN_GPP(gpp_offset); 222 offset = padgrp->padown_num * 4 + gpp * 4; 223 224 return !(readl(padown + offset) & PADOWN_MASK(gpp_offset)); 225 } 226 227 static bool intel_pad_acpi_mode(const struct intel_pinctrl *pctrl, unsigned int pin) 228 { 229 const struct intel_community *community; 230 const struct intel_padgroup *padgrp; 231 unsigned int offset, gpp_offset; 232 void __iomem *hostown; 233 234 community = intel_get_community(pctrl, pin); 235 if (!community) 236 return true; 237 if (!community->hostown_offset) 238 return false; 239 240 padgrp = intel_community_get_padgroup(community, pin); 241 if (!padgrp) 242 return true; 243 244 gpp_offset = padgroup_offset(padgrp, pin); 245 offset = community->hostown_offset + padgrp->reg_num * 4; 246 hostown = community->regs + offset; 247 248 return !(readl(hostown) & BIT(gpp_offset)); 249 } 250 251 /** 252 * enum - Locking variants of the pad configuration 253 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers 254 * @PAD_LOCKED: pad configuration registers, except TX state, are locked 255 * @PAD_LOCKED_TX: pad configuration TX state is locked 256 * @PAD_LOCKED_FULL: pad configuration registers are locked completely 257 * 258 * Locking is considered as read-only mode for corresponding registers and 259 * their respective fields. That said, TX state bit is locked separately from 260 * the main locking scheme. 261 */ 262 enum { 263 PAD_UNLOCKED = 0, 264 PAD_LOCKED = 1, 265 PAD_LOCKED_TX = 2, 266 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX, 267 }; 268 269 static int intel_pad_locked(const struct intel_pinctrl *pctrl, unsigned int pin) 270 { 271 const struct intel_community *community; 272 const struct intel_padgroup *padgrp; 273 unsigned int offset, gpp_offset; 274 u32 value; 275 int ret = PAD_UNLOCKED; 276 277 community = intel_get_community(pctrl, pin); 278 if (!community) 279 return PAD_LOCKED_FULL; 280 if (!community->padcfglock_offset) 281 return PAD_UNLOCKED; 282 283 padgrp = intel_community_get_padgroup(community, pin); 284 if (!padgrp) 285 return PAD_LOCKED_FULL; 286 287 gpp_offset = padgroup_offset(padgrp, pin); 288 289 /* 290 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 291 * the pad is considered unlocked. Any other case means that it is 292 * either fully or partially locked. 293 */ 294 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; 295 value = readl(community->regs + offset); 296 if (value & BIT(gpp_offset)) 297 ret |= PAD_LOCKED; 298 299 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; 300 value = readl(community->regs + offset); 301 if (value & BIT(gpp_offset)) 302 ret |= PAD_LOCKED_TX; 303 304 return ret; 305 } 306 307 static bool intel_pad_is_unlocked(const struct intel_pinctrl *pctrl, unsigned int pin) 308 { 309 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED; 310 } 311 312 static bool intel_pad_usable(const struct intel_pinctrl *pctrl, unsigned int pin) 313 { 314 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); 315 } 316 317 int intel_get_groups_count(struct pinctrl_dev *pctldev) 318 { 319 const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 320 321 return pctrl->soc->ngroups; 322 } 323 EXPORT_SYMBOL_NS_GPL(intel_get_groups_count, "PINCTRL_INTEL"); 324 325 const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group) 326 { 327 const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 328 329 return pctrl->soc->groups[group].grp.name; 330 } 331 EXPORT_SYMBOL_NS_GPL(intel_get_group_name, "PINCTRL_INTEL"); 332 333 int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 334 const unsigned int **pins, unsigned int *npins) 335 { 336 const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 337 338 *pins = pctrl->soc->groups[group].grp.pins; 339 *npins = pctrl->soc->groups[group].grp.npins; 340 return 0; 341 } 342 EXPORT_SYMBOL_NS_GPL(intel_get_group_pins, "PINCTRL_INTEL"); 343 344 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 345 unsigned int pin) 346 { 347 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 348 void __iomem *padcfg; 349 u32 cfg0, cfg1, mode; 350 int locked; 351 bool acpi; 352 353 if (!intel_pad_owned_by_host(pctrl, pin)) { 354 seq_puts(s, "not available"); 355 return; 356 } 357 358 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 359 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 360 361 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 362 if (mode == PADCFG0_PMODE_GPIO) 363 seq_puts(s, "GPIO "); 364 else 365 seq_printf(s, "mode %d ", mode); 366 367 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 368 369 /* Dump the additional PADCFG registers if available */ 370 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); 371 if (padcfg) 372 seq_printf(s, " 0x%08x", readl(padcfg)); 373 374 locked = intel_pad_locked(pctrl, pin); 375 acpi = intel_pad_acpi_mode(pctrl, pin); 376 377 if (locked || acpi) { 378 seq_puts(s, " ["); 379 if (locked) 380 seq_puts(s, "LOCKED"); 381 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) 382 seq_puts(s, " tx"); 383 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) 384 seq_puts(s, " full"); 385 386 if (locked && acpi) 387 seq_puts(s, ", "); 388 389 if (acpi) 390 seq_puts(s, "ACPI"); 391 seq_puts(s, "]"); 392 } 393 } 394 395 static const struct pinctrl_ops intel_pinctrl_ops = { 396 .get_groups_count = intel_get_groups_count, 397 .get_group_name = intel_get_group_name, 398 .get_group_pins = intel_get_group_pins, 399 .pin_dbg_show = intel_pin_dbg_show, 400 }; 401 402 int intel_get_functions_count(struct pinctrl_dev *pctldev) 403 { 404 const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 405 406 return pctrl->soc->nfunctions; 407 } 408 EXPORT_SYMBOL_NS_GPL(intel_get_functions_count, "PINCTRL_INTEL"); 409 410 const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function) 411 { 412 const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 413 414 return pctrl->soc->functions[function].func.name; 415 } 416 EXPORT_SYMBOL_NS_GPL(intel_get_function_name, "PINCTRL_INTEL"); 417 418 int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function, 419 const char * const **groups, unsigned int * const ngroups) 420 { 421 const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 422 423 *groups = pctrl->soc->functions[function].func.groups; 424 *ngroups = pctrl->soc->functions[function].func.ngroups; 425 return 0; 426 } 427 EXPORT_SYMBOL_NS_GPL(intel_get_function_groups, "PINCTRL_INTEL"); 428 429 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, 430 unsigned int function, unsigned int group) 431 { 432 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 433 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 434 int i; 435 436 guard(raw_spinlock_irqsave)(&pctrl->lock); 437 438 /* 439 * All pins in the groups needs to be accessible and writable 440 * before we can enable the mux for this group. 441 */ 442 for (i = 0; i < grp->grp.npins; i++) { 443 if (!intel_pad_usable(pctrl, grp->grp.pins[i])) 444 return -EBUSY; 445 } 446 447 /* Now enable the mux setting for each pin in the group */ 448 for (i = 0; i < grp->grp.npins; i++) { 449 void __iomem *padcfg0; 450 u32 value, pmode; 451 452 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0); 453 454 value = readl(padcfg0); 455 value &= ~PADCFG0_PMODE_MASK; 456 457 if (grp->modes) 458 pmode = grp->modes[i]; 459 else 460 pmode = grp->mode; 461 462 value |= pmode << PADCFG0_PMODE_SHIFT; 463 writel(value, padcfg0); 464 } 465 466 return 0; 467 } 468 469 /** 470 * enum - Possible pad physical connections 471 * @PAD_CONNECT_NONE: pad is fully disconnected 472 * @PAD_CONNECT_INPUT: pad is in input only mode 473 * @PAD_CONNECT_OUTPUT: pad is in output only mode 474 * @PAD_CONNECT_FULL: pad is fully connected 475 */ 476 enum { 477 PAD_CONNECT_NONE = 0, 478 PAD_CONNECT_INPUT = 1, 479 PAD_CONNECT_OUTPUT = 2, 480 PAD_CONNECT_FULL = PAD_CONNECT_INPUT | PAD_CONNECT_OUTPUT, 481 }; 482 483 static int __intel_gpio_get_direction(u32 value) 484 { 485 switch ((value & PADCFG0_GPIODIS_MASK) >> PADCFG0_GPIODIS_SHIFT) { 486 case PADCFG0_GPIODIS_FULL: 487 return PAD_CONNECT_NONE; 488 case PADCFG0_GPIODIS_OUTPUT: 489 return PAD_CONNECT_INPUT; 490 case PADCFG0_GPIODIS_INPUT: 491 return PAD_CONNECT_OUTPUT; 492 case PADCFG0_GPIODIS_NONE: 493 return PAD_CONNECT_FULL; 494 default: 495 return -ENOTSUPP; 496 }; 497 } 498 499 static u32 __intel_gpio_set_direction(u32 value, bool input, bool output) 500 { 501 if (input) 502 value &= ~PADCFG0_GPIORXDIS; 503 else 504 value |= PADCFG0_GPIORXDIS; 505 506 if (output) 507 value &= ~PADCFG0_GPIOTXDIS; 508 else 509 value |= PADCFG0_GPIOTXDIS; 510 511 return value; 512 } 513 514 static int __intel_gpio_get_gpio_mode(u32 value) 515 { 516 return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 517 } 518 519 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) 520 { 521 return __intel_gpio_get_gpio_mode(readl(padcfg0)); 522 } 523 524 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) 525 { 526 u32 value; 527 528 value = readl(padcfg0); 529 530 /* Put the pad into GPIO mode */ 531 value &= ~PADCFG0_PMODE_MASK; 532 value |= PADCFG0_PMODE_GPIO; 533 534 /* Disable TX buffer and enable RX (this will be input) */ 535 value = __intel_gpio_set_direction(value, true, false); 536 537 /* Disable SCI/SMI/NMI generation */ 538 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 539 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 540 541 writel(value, padcfg0); 542 } 543 544 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 545 struct pinctrl_gpio_range *range, 546 unsigned int pin) 547 { 548 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 549 void __iomem *padcfg0; 550 551 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 552 553 guard(raw_spinlock_irqsave)(&pctrl->lock); 554 555 if (!intel_pad_owned_by_host(pctrl, pin)) 556 return -EBUSY; 557 558 if (!intel_pad_is_unlocked(pctrl, pin)) 559 return 0; 560 561 /* 562 * If pin is already configured in GPIO mode, we assume that 563 * firmware provides correct settings. In such case we avoid 564 * potential glitches on the pin. Otherwise, for the pin in 565 * alternative mode, consumer has to supply respective flags. 566 */ 567 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) 568 return 0; 569 570 intel_gpio_set_gpio_mode(padcfg0); 571 572 return 0; 573 } 574 575 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 576 struct pinctrl_gpio_range *range, 577 unsigned int pin, bool input) 578 { 579 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 580 void __iomem *padcfg0; 581 u32 value; 582 583 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 584 585 guard(raw_spinlock_irqsave)(&pctrl->lock); 586 587 value = readl(padcfg0); 588 if (input) 589 value = __intel_gpio_set_direction(value, true, false); 590 else 591 value = __intel_gpio_set_direction(value, false, true); 592 writel(value, padcfg0); 593 594 return 0; 595 } 596 597 static const struct pinmux_ops intel_pinmux_ops = { 598 .get_functions_count = intel_get_functions_count, 599 .get_function_name = intel_get_function_name, 600 .get_function_groups = intel_get_function_groups, 601 .set_mux = intel_pinmux_set_mux, 602 .gpio_request_enable = intel_gpio_request_enable, 603 .gpio_set_direction = intel_gpio_set_direction, 604 }; 605 606 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin, 607 enum pin_config_param param, u32 *arg) 608 { 609 void __iomem *padcfg1; 610 u32 value, term; 611 612 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 613 614 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) 615 value = readl(padcfg1); 616 617 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 618 619 switch (param) { 620 case PIN_CONFIG_BIAS_DISABLE: 621 if (term) 622 return -EINVAL; 623 break; 624 625 case PIN_CONFIG_BIAS_PULL_UP: 626 if (!term || !(value & PADCFG1_TERM_UP)) 627 return -EINVAL; 628 629 switch (term) { 630 case PADCFG1_TERM_833: 631 *arg = 833; 632 break; 633 case PADCFG1_TERM_1K: 634 *arg = 1000; 635 break; 636 case PADCFG1_TERM_4K: 637 *arg = 4000; 638 break; 639 case PADCFG1_TERM_5K: 640 *arg = 5000; 641 break; 642 case PADCFG1_TERM_20K: 643 *arg = 20000; 644 break; 645 } 646 647 break; 648 649 case PIN_CONFIG_BIAS_PULL_DOWN: { 650 const struct intel_community *community = intel_get_community(pctrl, pin); 651 652 if (!term || value & PADCFG1_TERM_UP) 653 return -EINVAL; 654 655 switch (term) { 656 case PADCFG1_TERM_833: 657 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 658 return -EINVAL; 659 *arg = 833; 660 break; 661 case PADCFG1_TERM_1K: 662 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 663 return -EINVAL; 664 *arg = 1000; 665 break; 666 case PADCFG1_TERM_4K: 667 *arg = 4000; 668 break; 669 case PADCFG1_TERM_5K: 670 *arg = 5000; 671 break; 672 case PADCFG1_TERM_20K: 673 *arg = 20000; 674 break; 675 } 676 677 break; 678 } 679 680 default: 681 return -EINVAL; 682 } 683 684 return 0; 685 } 686 687 static int intel_config_get_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin, 688 enum pin_config_param param, u32 *arg) 689 { 690 void __iomem *padcfg0; 691 u32 value; 692 693 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 694 695 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) 696 value = readl(padcfg0); 697 698 if (__intel_gpio_get_direction(value) != PAD_CONNECT_NONE) 699 return -EINVAL; 700 701 return 0; 702 } 703 704 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin, 705 enum pin_config_param param, u32 *arg) 706 { 707 void __iomem *padcfg2; 708 unsigned long v; 709 u32 value2; 710 711 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 712 if (!padcfg2) 713 return -ENOTSUPP; 714 715 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) 716 value2 = readl(padcfg2); 717 718 if (!(value2 & PADCFG2_DEBEN)) 719 return -EINVAL; 720 721 v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; 722 *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC; 723 724 return 0; 725 } 726 727 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 728 unsigned long *config) 729 { 730 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 731 enum pin_config_param param = pinconf_to_config_param(*config); 732 u32 arg = 0; 733 int ret; 734 735 if (!intel_pad_owned_by_host(pctrl, pin)) 736 return -ENOTSUPP; 737 738 switch (param) { 739 case PIN_CONFIG_BIAS_DISABLE: 740 case PIN_CONFIG_BIAS_PULL_UP: 741 case PIN_CONFIG_BIAS_PULL_DOWN: 742 ret = intel_config_get_pull(pctrl, pin, param, &arg); 743 if (ret) 744 return ret; 745 break; 746 747 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 748 ret = intel_config_get_high_impedance(pctrl, pin, param, &arg); 749 if (ret) 750 return ret; 751 break; 752 753 case PIN_CONFIG_INPUT_DEBOUNCE: 754 ret = intel_config_get_debounce(pctrl, pin, param, &arg); 755 if (ret) 756 return ret; 757 break; 758 759 default: 760 return -ENOTSUPP; 761 } 762 763 *config = pinconf_to_config_packed(param, arg); 764 return 0; 765 } 766 767 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 768 unsigned long config) 769 { 770 unsigned int param = pinconf_to_config_param(config); 771 unsigned int arg = pinconf_to_config_argument(config); 772 u32 term = 0, up = 0, value; 773 void __iomem *padcfg1; 774 775 switch (param) { 776 case PIN_CONFIG_BIAS_DISABLE: 777 break; 778 779 case PIN_CONFIG_BIAS_PULL_UP: 780 switch (arg) { 781 case 20000: 782 term = PADCFG1_TERM_20K; 783 break; 784 case 1: /* Set default strength value in case none is given */ 785 case 5000: 786 term = PADCFG1_TERM_5K; 787 break; 788 case 4000: 789 term = PADCFG1_TERM_4K; 790 break; 791 case 1000: 792 term = PADCFG1_TERM_1K; 793 break; 794 case 833: 795 term = PADCFG1_TERM_833; 796 break; 797 default: 798 return -EINVAL; 799 } 800 801 up = PADCFG1_TERM_UP; 802 break; 803 804 case PIN_CONFIG_BIAS_PULL_DOWN: { 805 const struct intel_community *community = intel_get_community(pctrl, pin); 806 807 switch (arg) { 808 case 20000: 809 term = PADCFG1_TERM_20K; 810 break; 811 case 1: /* Set default strength value in case none is given */ 812 case 5000: 813 term = PADCFG1_TERM_5K; 814 break; 815 case 4000: 816 term = PADCFG1_TERM_4K; 817 break; 818 case 1000: 819 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 820 return -EINVAL; 821 term = PADCFG1_TERM_1K; 822 break; 823 case 833: 824 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 825 return -EINVAL; 826 term = PADCFG1_TERM_833; 827 break; 828 default: 829 return -EINVAL; 830 } 831 832 break; 833 } 834 835 default: 836 return -EINVAL; 837 } 838 839 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 840 841 guard(raw_spinlock_irqsave)(&pctrl->lock); 842 843 value = readl(padcfg1); 844 value = (value & ~PADCFG1_TERM_MASK) | (term << PADCFG1_TERM_SHIFT); 845 value = (value & ~PADCFG1_TERM_UP) | up; 846 writel(value, padcfg1); 847 848 return 0; 849 } 850 851 static void intel_gpio_set_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin) 852 { 853 void __iomem *padcfg0; 854 u32 value; 855 856 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 857 858 guard(raw_spinlock_irqsave)(&pctrl->lock); 859 860 value = readl(padcfg0); 861 value = __intel_gpio_set_direction(value, false, false); 862 writel(value, padcfg0); 863 } 864 865 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, 866 unsigned int pin, unsigned int debounce) 867 { 868 void __iomem *padcfg0, *padcfg2; 869 u32 value0, value2; 870 unsigned long v; 871 872 if (debounce) { 873 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC); 874 if (v < 3 || v > 15) 875 return -EINVAL; 876 } else { 877 v = 0; 878 } 879 880 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 881 if (!padcfg2) 882 return -ENOTSUPP; 883 884 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 885 886 guard(raw_spinlock_irqsave)(&pctrl->lock); 887 888 value0 = readl(padcfg0); 889 value2 = readl(padcfg2); 890 891 value2 = (value2 & ~PADCFG2_DEBOUNCE_MASK) | (v << PADCFG2_DEBOUNCE_SHIFT); 892 if (v) { 893 /* Enable glitch filter and debouncer */ 894 value0 |= PADCFG0_PREGFRXSEL; 895 value2 |= PADCFG2_DEBEN; 896 } else { 897 /* Disable glitch filter and debouncer */ 898 value0 &= ~PADCFG0_PREGFRXSEL; 899 value2 &= ~PADCFG2_DEBEN; 900 } 901 902 writel(value0, padcfg0); 903 writel(value2, padcfg2); 904 905 return 0; 906 } 907 908 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 909 unsigned long *configs, unsigned int nconfigs) 910 { 911 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 912 int i, ret; 913 914 if (!intel_pad_usable(pctrl, pin)) 915 return -ENOTSUPP; 916 917 for (i = 0; i < nconfigs; i++) { 918 switch (pinconf_to_config_param(configs[i])) { 919 case PIN_CONFIG_BIAS_DISABLE: 920 case PIN_CONFIG_BIAS_PULL_UP: 921 case PIN_CONFIG_BIAS_PULL_DOWN: 922 ret = intel_config_set_pull(pctrl, pin, configs[i]); 923 if (ret) 924 return ret; 925 break; 926 927 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 928 intel_gpio_set_high_impedance(pctrl, pin); 929 break; 930 931 case PIN_CONFIG_INPUT_DEBOUNCE: 932 ret = intel_config_set_debounce(pctrl, pin, 933 pinconf_to_config_argument(configs[i])); 934 if (ret) 935 return ret; 936 break; 937 938 default: 939 return -ENOTSUPP; 940 } 941 } 942 943 return 0; 944 } 945 946 static const struct pinconf_ops intel_pinconf_ops = { 947 .is_generic = true, 948 .pin_config_get = intel_config_get, 949 .pin_config_set = intel_config_set, 950 }; 951 952 static const struct pinctrl_desc intel_pinctrl_desc = { 953 .pctlops = &intel_pinctrl_ops, 954 .pmxops = &intel_pinmux_ops, 955 .confops = &intel_pinconf_ops, 956 .owner = THIS_MODULE, 957 }; 958 959 /** 960 * intel_gpio_to_pin() - Translate from GPIO offset to pin number 961 * @pctrl: Pinctrl structure 962 * @offset: GPIO offset from gpiolib 963 * @community: Community is filled here if not %NULL 964 * @padgrp: Pad group is filled here if not %NULL 965 * 966 * When coming through gpiolib irqchip, the GPIO offset is not 967 * automatically translated to pinctrl pin number. This function can be 968 * used to find out the corresponding pinctrl pin. 969 * 970 * Return: a pin number and pointers to the community and pad group, which 971 * the pin belongs to, or negative error code if translation can't be done. 972 */ 973 static int intel_gpio_to_pin(const struct intel_pinctrl *pctrl, unsigned int offset, 974 const struct intel_community **community, 975 const struct intel_padgroup **padgrp) 976 { 977 const struct intel_community *comm; 978 const struct intel_padgroup *grp; 979 980 for_each_intel_gpio_group(pctrl, comm, grp) { 981 if (offset >= grp->gpio_base && offset < grp->gpio_base + grp->size) { 982 if (community) 983 *community = comm; 984 if (padgrp) 985 *padgrp = grp; 986 987 return grp->base + offset - grp->gpio_base; 988 } 989 } 990 991 return -EINVAL; 992 } 993 994 /** 995 * intel_pin_to_gpio() - Translate from pin number to GPIO offset 996 * @pctrl: Pinctrl structure 997 * @pin: pin number 998 * 999 * Translate the pin number of pinctrl to GPIO offset 1000 * 1001 * Return: a GPIO offset, or negative error code if translation can't be done. 1002 */ 1003 static int intel_pin_to_gpio(const struct intel_pinctrl *pctrl, int pin) 1004 { 1005 const struct intel_community *community; 1006 const struct intel_padgroup *padgrp; 1007 1008 community = intel_get_community(pctrl, pin); 1009 if (!community) 1010 return -EINVAL; 1011 1012 padgrp = intel_community_get_padgroup(community, pin); 1013 if (!padgrp) 1014 return -EINVAL; 1015 1016 return pin - padgrp->base + padgrp->gpio_base; 1017 } 1018 1019 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) 1020 { 1021 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1022 void __iomem *reg; 1023 u32 padcfg0; 1024 int pin; 1025 1026 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 1027 if (pin < 0) 1028 return -EINVAL; 1029 1030 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1031 if (!reg) 1032 return -EINVAL; 1033 1034 padcfg0 = readl(reg); 1035 if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT) 1036 return !!(padcfg0 & PADCFG0_GPIOTXSTATE); 1037 1038 return !!(padcfg0 & PADCFG0_GPIORXSTATE); 1039 } 1040 1041 static int intel_gpio_set(struct gpio_chip *chip, unsigned int offset, 1042 int value) 1043 { 1044 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1045 void __iomem *reg; 1046 u32 padcfg0; 1047 int pin; 1048 1049 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 1050 if (pin < 0) 1051 return -EINVAL; 1052 1053 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1054 if (!reg) 1055 return -EINVAL; 1056 1057 guard(raw_spinlock_irqsave)(&pctrl->lock); 1058 1059 padcfg0 = readl(reg); 1060 if (value) 1061 padcfg0 |= PADCFG0_GPIOTXSTATE; 1062 else 1063 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 1064 writel(padcfg0, reg); 1065 1066 return 0; 1067 } 1068 1069 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1070 { 1071 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1072 void __iomem *reg; 1073 u32 padcfg0; 1074 int pin; 1075 1076 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 1077 if (pin < 0) 1078 return -EINVAL; 1079 1080 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1081 if (!reg) 1082 return -EINVAL; 1083 1084 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) 1085 padcfg0 = readl(reg); 1086 1087 if (padcfg0 & PADCFG0_PMODE_MASK) 1088 return -EINVAL; 1089 1090 if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT) 1091 return GPIO_LINE_DIRECTION_OUT; 1092 1093 return GPIO_LINE_DIRECTION_IN; 1094 } 1095 1096 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1097 { 1098 return pinctrl_gpio_direction_input(chip, offset); 1099 } 1100 1101 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 1102 int value) 1103 { 1104 int ret; 1105 1106 ret = intel_gpio_set(chip, offset, value); 1107 if (ret) 1108 return ret; 1109 1110 return pinctrl_gpio_direction_output(chip, offset); 1111 } 1112 1113 static const struct gpio_chip intel_gpio_chip = { 1114 .owner = THIS_MODULE, 1115 .request = gpiochip_generic_request, 1116 .free = gpiochip_generic_free, 1117 .get_direction = intel_gpio_get_direction, 1118 .direction_input = intel_gpio_direction_input, 1119 .direction_output = intel_gpio_direction_output, 1120 .get = intel_gpio_get, 1121 .set = intel_gpio_set, 1122 .set_config = gpiochip_generic_config, 1123 }; 1124 1125 static void intel_gpio_irq_ack(struct irq_data *d) 1126 { 1127 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1128 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1129 const struct intel_community *community; 1130 const struct intel_padgroup *padgrp; 1131 int pin; 1132 1133 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 1134 if (pin >= 0) { 1135 unsigned int gpp, gpp_offset; 1136 void __iomem *is; 1137 1138 gpp = padgrp->reg_num; 1139 gpp_offset = padgroup_offset(padgrp, pin); 1140 1141 is = community->regs + community->is_offset + gpp * 4; 1142 1143 guard(raw_spinlock)(&pctrl->lock); 1144 1145 writel(BIT(gpp_offset), is); 1146 } 1147 } 1148 1149 static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) 1150 { 1151 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1152 const struct intel_community *community; 1153 const struct intel_padgroup *padgrp; 1154 int pin; 1155 1156 pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp); 1157 if (pin >= 0) { 1158 unsigned int gpp, gpp_offset; 1159 void __iomem *reg, *is; 1160 u32 value; 1161 1162 gpp = padgrp->reg_num; 1163 gpp_offset = padgroup_offset(padgrp, pin); 1164 1165 reg = community->regs + community->ie_offset + gpp * 4; 1166 is = community->regs + community->is_offset + gpp * 4; 1167 1168 guard(raw_spinlock_irqsave)(&pctrl->lock); 1169 1170 /* Clear interrupt status first to avoid unexpected interrupt */ 1171 writel(BIT(gpp_offset), is); 1172 1173 value = readl(reg); 1174 if (mask) 1175 value &= ~BIT(gpp_offset); 1176 else 1177 value |= BIT(gpp_offset); 1178 writel(value, reg); 1179 } 1180 } 1181 1182 static void intel_gpio_irq_mask(struct irq_data *d) 1183 { 1184 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1185 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1186 1187 intel_gpio_irq_mask_unmask(gc, hwirq, true); 1188 gpiochip_disable_irq(gc, hwirq); 1189 } 1190 1191 static void intel_gpio_irq_unmask(struct irq_data *d) 1192 { 1193 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1194 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1195 1196 gpiochip_enable_irq(gc, hwirq); 1197 intel_gpio_irq_mask_unmask(gc, hwirq, false); 1198 } 1199 1200 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) 1201 { 1202 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1203 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1204 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1205 u32 rxevcfg, rxinv, value; 1206 void __iomem *reg; 1207 1208 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1209 if (!reg) 1210 return -EINVAL; 1211 1212 /* 1213 * If the pin is in ACPI mode it is still usable as a GPIO but it 1214 * cannot be used as IRQ because GPI_IS status bit will not be 1215 * updated by the host controller hardware. 1216 */ 1217 if (intel_pad_acpi_mode(pctrl, pin)) { 1218 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 1219 return -EPERM; 1220 } 1221 1222 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 1223 rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH; 1224 } else if (type & IRQ_TYPE_EDGE_FALLING) { 1225 rxevcfg = PADCFG0_RXEVCFG_EDGE; 1226 } else if (type & IRQ_TYPE_EDGE_RISING) { 1227 rxevcfg = PADCFG0_RXEVCFG_EDGE; 1228 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1229 rxevcfg = PADCFG0_RXEVCFG_LEVEL; 1230 } else { 1231 rxevcfg = PADCFG0_RXEVCFG_DISABLED; 1232 } 1233 1234 if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) 1235 rxinv = PADCFG0_RXINV; 1236 else 1237 rxinv = 0; 1238 1239 guard(raw_spinlock_irqsave)(&pctrl->lock); 1240 1241 intel_gpio_set_gpio_mode(reg); 1242 1243 value = readl(reg); 1244 1245 value = (value & ~PADCFG0_RXEVCFG_MASK) | rxevcfg; 1246 value = (value & ~PADCFG0_RXINV) | rxinv; 1247 1248 writel(value, reg); 1249 1250 if (type & IRQ_TYPE_EDGE_BOTH) 1251 irq_set_handler_locked(d, handle_edge_irq); 1252 else if (type & IRQ_TYPE_LEVEL_MASK) 1253 irq_set_handler_locked(d, handle_level_irq); 1254 1255 return 0; 1256 } 1257 1258 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 1259 { 1260 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1261 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1262 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1263 1264 if (on) 1265 enable_irq_wake(pctrl->irq); 1266 else 1267 disable_irq_wake(pctrl->irq); 1268 1269 dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin); 1270 return 0; 1271 } 1272 1273 static const struct irq_chip intel_gpio_irq_chip = { 1274 .name = "intel-gpio", 1275 .irq_ack = intel_gpio_irq_ack, 1276 .irq_mask = intel_gpio_irq_mask, 1277 .irq_unmask = intel_gpio_irq_unmask, 1278 .irq_set_type = intel_gpio_irq_type, 1279 .irq_set_wake = intel_gpio_irq_wake, 1280 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 1281 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1282 }; 1283 1284 static irqreturn_t intel_gpio_irq(int irq, void *data) 1285 { 1286 const struct intel_community *community; 1287 const struct intel_padgroup *padgrp; 1288 struct intel_pinctrl *pctrl = data; 1289 int ret = 0; 1290 1291 /* Need to check all communities for pending interrupts */ 1292 for_each_intel_pad_group(pctrl, community, padgrp) { 1293 struct gpio_chip *gc = &pctrl->chip; 1294 unsigned long pending, enabled; 1295 unsigned int gpp, gpp_offset; 1296 void __iomem *reg, *is; 1297 1298 gpp = padgrp->reg_num; 1299 1300 reg = community->regs + community->ie_offset + gpp * 4; 1301 is = community->regs + community->is_offset + gpp * 4; 1302 1303 scoped_guard(raw_spinlock, &pctrl->lock) { 1304 pending = readl(is); 1305 enabled = readl(reg); 1306 } 1307 1308 /* Only interrupts that are enabled */ 1309 pending &= enabled; 1310 1311 for_each_set_bit(gpp_offset, &pending, padgrp->size) 1312 generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset); 1313 1314 ret += pending ? 1 : 0; 1315 } 1316 1317 return IRQ_RETVAL(ret); 1318 } 1319 1320 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1321 { 1322 const struct intel_community *community; 1323 1324 for_each_intel_pin_community(pctrl, community) { 1325 void __iomem *reg, *is; 1326 unsigned int gpp; 1327 1328 for (gpp = 0; gpp < community->ngpps; gpp++) { 1329 reg = community->regs + community->ie_offset + gpp * 4; 1330 is = community->regs + community->is_offset + gpp * 4; 1331 1332 /* Mask and clear all interrupts */ 1333 writel(0, reg); 1334 writel(0xffff, is); 1335 } 1336 } 1337 } 1338 1339 static int intel_gpio_irq_init_hw(struct gpio_chip *gc) 1340 { 1341 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1342 1343 /* 1344 * Make sure the interrupt lines are in a proper state before 1345 * further configuration. 1346 */ 1347 intel_gpio_irq_init(pctrl); 1348 1349 return 0; 1350 } 1351 1352 /** 1353 * intel_gpio_add_pin_ranges - add GPIO pin ranges for all groups in all communities 1354 * @gc: GPIO chip structure 1355 * 1356 * This function iterates over all communities and all groups and adds the respective 1357 * GPIO pin ranges, so the GPIO library will correctly map a GPIO offset to a pin number. 1358 * 1359 * Return: 0, or negative error code if range can't be added. 1360 */ 1361 int intel_gpio_add_pin_ranges(struct gpio_chip *gc) 1362 { 1363 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1364 const struct intel_community *community; 1365 const struct intel_padgroup *grp; 1366 int ret; 1367 1368 for_each_intel_gpio_group(pctrl, community, grp) { 1369 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1370 grp->gpio_base, grp->base, 1371 grp->size); 1372 if (ret) 1373 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO pin range\n"); 1374 } 1375 1376 return 0; 1377 } 1378 EXPORT_SYMBOL_NS_GPL(intel_gpio_add_pin_ranges, "PINCTRL_INTEL"); 1379 1380 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1381 { 1382 const struct intel_community *community; 1383 const struct intel_padgroup *grp; 1384 unsigned int ngpio = 0; 1385 1386 for_each_intel_gpio_group(pctrl, community, grp) { 1387 if (grp->gpio_base + grp->size > ngpio) 1388 ngpio = grp->gpio_base + grp->size; 1389 } 1390 1391 return ngpio; 1392 } 1393 1394 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1395 { 1396 int ret; 1397 struct gpio_irq_chip *girq; 1398 1399 pctrl->chip = intel_gpio_chip; 1400 1401 /* Setup GPIO chip */ 1402 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); 1403 pctrl->chip.label = dev_name(pctrl->dev); 1404 pctrl->chip.parent = pctrl->dev; 1405 pctrl->chip.base = -1; 1406 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; 1407 pctrl->irq = irq; 1408 1409 /* 1410 * On some platforms several GPIO controllers share the same interrupt 1411 * line. 1412 */ 1413 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1414 IRQF_SHARED | IRQF_NO_THREAD, 1415 dev_name(pctrl->dev), pctrl); 1416 if (ret) 1417 return dev_err_probe(pctrl->dev, ret, "failed to request interrupt\n"); 1418 1419 /* Setup IRQ chip */ 1420 girq = &pctrl->chip.irq; 1421 gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip); 1422 /* This will let us handle the IRQ in the driver */ 1423 girq->parent_handler = NULL; 1424 girq->num_parents = 0; 1425 girq->default_type = IRQ_TYPE_NONE; 1426 girq->handler = handle_bad_irq; 1427 girq->init_hw = intel_gpio_irq_init_hw; 1428 1429 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1430 if (ret) 1431 return dev_err_probe(pctrl->dev, ret, "failed to register gpiochip\n"); 1432 1433 return 0; 1434 } 1435 1436 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl, 1437 struct intel_community *community) 1438 { 1439 struct intel_padgroup *gpps; 1440 unsigned int padown_num = 0; 1441 size_t i, ngpps = community->ngpps; 1442 1443 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1444 if (!gpps) 1445 return -ENOMEM; 1446 1447 for (i = 0; i < ngpps; i++) { 1448 gpps[i] = community->gpps[i]; 1449 1450 if (gpps[i].size > INTEL_PINCTRL_MAX_GPP_SIZE) 1451 return -EINVAL; 1452 1453 /* Special treatment for GPIO base */ 1454 switch (gpps[i].gpio_base) { 1455 case INTEL_GPIO_BASE_MATCH: 1456 gpps[i].gpio_base = gpps[i].base; 1457 break; 1458 case INTEL_GPIO_BASE_ZERO: 1459 gpps[i].gpio_base = 0; 1460 break; 1461 case INTEL_GPIO_BASE_NOMAP: 1462 break; 1463 default: 1464 break; 1465 } 1466 1467 gpps[i].padown_num = padown_num; 1468 padown_num += DIV_ROUND_UP(gpps[i].size * 4, INTEL_PINCTRL_MAX_GPP_SIZE); 1469 } 1470 1471 community->gpps = gpps; 1472 1473 return 0; 1474 } 1475 1476 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl, 1477 struct intel_community *community) 1478 { 1479 struct intel_padgroup *gpps; 1480 unsigned int npins = community->npins; 1481 unsigned int padown_num = 0; 1482 size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size); 1483 1484 if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE) 1485 return -EINVAL; 1486 1487 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1488 if (!gpps) 1489 return -ENOMEM; 1490 1491 for (i = 0; i < ngpps; i++) { 1492 unsigned int gpp_size = community->gpp_size; 1493 1494 gpps[i].reg_num = i; 1495 gpps[i].base = community->pin_base + i * gpp_size; 1496 gpps[i].size = min(gpp_size, npins); 1497 npins -= gpps[i].size; 1498 1499 gpps[i].gpio_base = gpps[i].base; 1500 gpps[i].padown_num = padown_num; 1501 1502 padown_num += community->gpp_num_padown_regs; 1503 } 1504 1505 community->ngpps = ngpps; 1506 community->gpps = gpps; 1507 1508 return 0; 1509 } 1510 1511 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 1512 { 1513 #ifdef CONFIG_PM_SLEEP 1514 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 1515 struct intel_community_context *communities; 1516 struct intel_pad_context *pads; 1517 int i; 1518 1519 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 1520 if (!pads) 1521 return -ENOMEM; 1522 1523 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 1524 sizeof(*communities), GFP_KERNEL); 1525 if (!communities) 1526 return -ENOMEM; 1527 1528 1529 for (i = 0; i < pctrl->ncommunities; i++) { 1530 struct intel_community *community = &pctrl->communities[i]; 1531 u32 *intmask, *hostown; 1532 1533 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1534 sizeof(*intmask), GFP_KERNEL); 1535 if (!intmask) 1536 return -ENOMEM; 1537 1538 communities[i].intmask = intmask; 1539 1540 hostown = devm_kcalloc(pctrl->dev, community->ngpps, 1541 sizeof(*hostown), GFP_KERNEL); 1542 if (!hostown) 1543 return -ENOMEM; 1544 1545 communities[i].hostown = hostown; 1546 } 1547 1548 pctrl->context.pads = pads; 1549 pctrl->context.communities = communities; 1550 #endif 1551 1552 return 0; 1553 } 1554 1555 static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, 1556 struct intel_community *community, 1557 unsigned short capability_offset) 1558 { 1559 void __iomem *base = community->regs + capability_offset + 4; 1560 static const struct pwm_lpss_boardinfo info = { 1561 .clk_rate = 19200000, 1562 .npwm = 1, 1563 .base_unit_bits = 22, 1564 }; 1565 struct pwm_chip *chip; 1566 1567 if (!(community->features & PINCTRL_FEATURE_PWM)) 1568 return 0; 1569 1570 if (!IS_REACHABLE(CONFIG_PWM_LPSS)) 1571 return 0; 1572 1573 chip = devm_pwm_lpss_probe(pctrl->dev, base, &info); 1574 return PTR_ERR_OR_ZERO(chip); 1575 } 1576 1577 int intel_pinctrl_probe(struct platform_device *pdev, 1578 const struct intel_pinctrl_soc_data *soc_data) 1579 { 1580 struct device *dev = &pdev->dev; 1581 struct intel_pinctrl *pctrl; 1582 int i, ret, irq; 1583 1584 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 1585 if (!pctrl) 1586 return -ENOMEM; 1587 1588 pctrl->dev = dev; 1589 pctrl->soc = soc_data; 1590 raw_spin_lock_init(&pctrl->lock); 1591 1592 /* 1593 * Make a copy of the communities which we can use to hold pointers 1594 * to the registers. 1595 */ 1596 pctrl->ncommunities = pctrl->soc->ncommunities; 1597 pctrl->communities = devm_kmemdup_array(dev, pctrl->soc->communities, pctrl->ncommunities, 1598 sizeof(*pctrl->soc->communities), GFP_KERNEL); 1599 if (!pctrl->communities) 1600 return -ENOMEM; 1601 1602 for (i = 0; i < pctrl->ncommunities; i++) { 1603 struct intel_community *community = &pctrl->communities[i]; 1604 unsigned short capability_offset[6]; 1605 void __iomem *regs; 1606 u32 revision; 1607 u32 offset; 1608 u32 value; 1609 1610 regs = devm_platform_ioremap_resource(pdev, community->barno); 1611 if (IS_ERR(regs)) 1612 return PTR_ERR(regs); 1613 1614 /* 1615 * Determine community features based on the revision. 1616 * A value of all ones means the device is not present. 1617 */ 1618 value = readl(regs + REVID); 1619 if (value == ~0u) 1620 return -ENODEV; 1621 1622 revision = (value & REVID_MASK) >> REVID_SHIFT; 1623 if (revision >= 0x092) { 1624 community->features |= PINCTRL_FEATURE_DEBOUNCE; 1625 community->features |= PINCTRL_FEATURE_1K_PD; 1626 } 1627 if (revision >= 0x110) 1628 community->features |= PINCTRL_FEATURE_3BIT_PAD_OWN; 1629 1630 /* Determine community features based on the capabilities */ 1631 offset = CAPLIST; 1632 do { 1633 value = readl(regs + offset); 1634 switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) { 1635 case CAPLIST_ID_GPIO_HW_INFO: 1636 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO; 1637 capability_offset[CAPLIST_ID_GPIO_HW_INFO] = offset; 1638 break; 1639 case CAPLIST_ID_PWM: 1640 community->features |= PINCTRL_FEATURE_PWM; 1641 capability_offset[CAPLIST_ID_PWM] = offset; 1642 break; 1643 case CAPLIST_ID_BLINK: 1644 community->features |= PINCTRL_FEATURE_BLINK; 1645 capability_offset[CAPLIST_ID_BLINK] = offset; 1646 break; 1647 case CAPLIST_ID_EXP: 1648 community->features |= PINCTRL_FEATURE_EXP; 1649 capability_offset[CAPLIST_ID_EXP] = offset; 1650 break; 1651 default: 1652 break; 1653 } 1654 offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT; 1655 } while (offset); 1656 1657 dev_dbg(dev, "Community%d features: %#08x\n", i, community->features); 1658 1659 /* Read offset of the pad configuration registers */ 1660 offset = readl(regs + PADBAR); 1661 1662 community->regs = regs; 1663 community->pad_regs = regs + offset; 1664 1665 if (community->gpps) 1666 ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community); 1667 else 1668 ret = intel_pinctrl_add_padgroups_by_size(pctrl, community); 1669 if (ret) 1670 return ret; 1671 1672 ret = intel_pinctrl_probe_pwm(pctrl, community, capability_offset[CAPLIST_ID_PWM]); 1673 if (ret) 1674 return ret; 1675 } 1676 1677 irq = platform_get_irq(pdev, 0); 1678 if (irq < 0) 1679 return irq; 1680 1681 ret = intel_pinctrl_pm_init(pctrl); 1682 if (ret) 1683 return ret; 1684 1685 pctrl->pctldesc = intel_pinctrl_desc; 1686 pctrl->pctldesc.name = dev_name(dev); 1687 pctrl->pctldesc.pins = pctrl->soc->pins; 1688 pctrl->pctldesc.npins = pctrl->soc->npins; 1689 1690 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); 1691 if (IS_ERR(pctrl->pctldev)) 1692 return PTR_ERR(pctrl->pctldev); 1693 1694 ret = intel_gpio_probe(pctrl, irq); 1695 if (ret) 1696 return ret; 1697 1698 platform_set_drvdata(pdev, pctrl); 1699 1700 return 0; 1701 } 1702 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe, "PINCTRL_INTEL"); 1703 1704 int intel_pinctrl_probe_by_hid(struct platform_device *pdev) 1705 { 1706 const struct intel_pinctrl_soc_data *data; 1707 1708 data = device_get_match_data(&pdev->dev); 1709 if (!data) 1710 return -ENODATA; 1711 1712 return intel_pinctrl_probe(pdev, data); 1713 } 1714 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_hid, "PINCTRL_INTEL"); 1715 1716 int intel_pinctrl_probe_by_uid(struct platform_device *pdev) 1717 { 1718 const struct intel_pinctrl_soc_data *data; 1719 1720 data = intel_pinctrl_get_soc_data(pdev); 1721 if (IS_ERR(data)) 1722 return PTR_ERR(data); 1723 1724 return intel_pinctrl_probe(pdev, data); 1725 } 1726 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, "PINCTRL_INTEL"); 1727 1728 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) 1729 { 1730 const struct intel_pinctrl_soc_data * const *table; 1731 const struct intel_pinctrl_soc_data *data; 1732 struct device *dev = &pdev->dev; 1733 1734 table = device_get_match_data(dev); 1735 if (table) { 1736 struct acpi_device *adev = ACPI_COMPANION(dev); 1737 unsigned int i; 1738 1739 for (i = 0; table[i]; i++) { 1740 if (acpi_dev_uid_match(adev, table[i]->uid)) 1741 break; 1742 } 1743 data = table[i]; 1744 } else { 1745 const struct platform_device_id *id; 1746 1747 id = platform_get_device_id(pdev); 1748 if (!id) 1749 return ERR_PTR(-ENODEV); 1750 1751 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data; 1752 data = table[pdev->id]; 1753 } 1754 1755 return data ?: ERR_PTR(-ENODATA); 1756 } 1757 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, "PINCTRL_INTEL"); 1758 1759 static bool __intel_gpio_is_direct_irq(u32 value) 1760 { 1761 return (value & PADCFG0_GPIROUTIOXAPIC) && 1762 (__intel_gpio_get_direction(value) == PAD_CONNECT_INPUT) && 1763 (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO); 1764 } 1765 1766 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) 1767 { 1768 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1769 u32 value; 1770 1771 if (!pd || !intel_pad_usable(pctrl, pin)) 1772 return false; 1773 1774 /* 1775 * Only restore the pin if it is actually in use by the kernel (or 1776 * by userspace). It is possible that some pins are used by the 1777 * BIOS during resume and those are not always locked down so leave 1778 * them alone. 1779 */ 1780 if (pd->mux_owner || pd->gpio_owner || 1781 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) 1782 return true; 1783 1784 /* 1785 * The firmware on some systems may configure GPIO pins to be 1786 * an interrupt source in so called "direct IRQ" mode. In such 1787 * cases the GPIO controller driver has no idea if those pins 1788 * are being used or not. At the same time, there is a known bug 1789 * in the firmwares that don't restore the pin settings correctly 1790 * after suspend, i.e. by an unknown reason the Rx value becomes 1791 * inverted. 1792 * 1793 * Hence, let's save and restore the pins that are configured 1794 * as GPIOs in the input mode with GPIROUTIOXAPIC bit set. 1795 * 1796 * See https://bugzilla.kernel.org/show_bug.cgi?id=214749. 1797 */ 1798 value = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 1799 if (__intel_gpio_is_direct_irq(value)) 1800 return true; 1801 1802 return false; 1803 } 1804 1805 static int intel_pinctrl_suspend_noirq(struct device *dev) 1806 { 1807 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1808 struct intel_community_context *communities; 1809 struct intel_pad_context *pads; 1810 int i; 1811 1812 pads = pctrl->context.pads; 1813 for (i = 0; i < pctrl->soc->npins; i++) { 1814 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1815 void __iomem *padcfg; 1816 u32 val; 1817 1818 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1819 continue; 1820 1821 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1822 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1823 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1824 pads[i].padcfg1 = val; 1825 1826 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1827 if (padcfg) 1828 pads[i].padcfg2 = readl(padcfg); 1829 } 1830 1831 communities = pctrl->context.communities; 1832 for (i = 0; i < pctrl->ncommunities; i++) { 1833 struct intel_community *community = &pctrl->communities[i]; 1834 void __iomem *base; 1835 unsigned int gpp; 1836 1837 base = community->regs + community->ie_offset; 1838 for (gpp = 0; gpp < community->ngpps; gpp++) 1839 communities[i].intmask[gpp] = readl(base + gpp * 4); 1840 1841 base = community->regs + community->hostown_offset; 1842 for (gpp = 0; gpp < community->ngpps; gpp++) 1843 communities[i].hostown[gpp] = readl(base + gpp * 4); 1844 } 1845 1846 return 0; 1847 } 1848 1849 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value) 1850 { 1851 u32 curr, updated; 1852 1853 curr = readl(reg); 1854 1855 updated = (curr & ~mask) | (value & mask); 1856 if (curr == updated) 1857 return false; 1858 1859 writel(updated, reg); 1860 return true; 1861 } 1862 1863 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, 1864 void __iomem *base, unsigned int gpp, u32 saved) 1865 { 1866 const struct intel_community *community = &pctrl->communities[c]; 1867 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1868 struct device *dev = pctrl->dev; 1869 const char *dummy; 1870 u32 requested = 0; 1871 unsigned int i; 1872 1873 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1874 return; 1875 1876 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy) 1877 requested |= BIT(i); 1878 1879 if (!intel_gpio_update_reg(base + gpp * 4, requested, saved)) 1880 return; 1881 1882 dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1883 } 1884 1885 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, 1886 void __iomem *base, unsigned int gpp, u32 saved) 1887 { 1888 struct device *dev = pctrl->dev; 1889 1890 if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved)) 1891 return; 1892 1893 dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1894 } 1895 1896 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, 1897 unsigned int reg, u32 saved) 1898 { 1899 u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0; 1900 unsigned int n = reg / sizeof(u32); 1901 struct device *dev = pctrl->dev; 1902 void __iomem *padcfg; 1903 1904 padcfg = intel_get_padcfg(pctrl, pin, reg); 1905 if (!padcfg) 1906 return; 1907 1908 if (!intel_gpio_update_reg(padcfg, ~mask, saved)) 1909 return; 1910 1911 dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg)); 1912 } 1913 1914 static int intel_pinctrl_resume_noirq(struct device *dev) 1915 { 1916 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1917 const struct intel_community_context *communities; 1918 const struct intel_pad_context *pads; 1919 int i; 1920 1921 /* Mask all interrupts */ 1922 intel_gpio_irq_init(pctrl); 1923 1924 pads = pctrl->context.pads; 1925 for (i = 0; i < pctrl->soc->npins; i++) { 1926 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1927 1928 if (!(intel_pinctrl_should_save(pctrl, desc->number) || 1929 /* 1930 * If the firmware mangled the register contents too much, 1931 * check the saved value for the Direct IRQ mode. 1932 */ 1933 __intel_gpio_is_direct_irq(pads[i].padcfg0))) 1934 continue; 1935 1936 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); 1937 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); 1938 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); 1939 } 1940 1941 communities = pctrl->context.communities; 1942 for (i = 0; i < pctrl->ncommunities; i++) { 1943 struct intel_community *community = &pctrl->communities[i]; 1944 void __iomem *base; 1945 unsigned int gpp; 1946 1947 base = community->regs + community->ie_offset; 1948 for (gpp = 0; gpp < community->ngpps; gpp++) 1949 intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]); 1950 1951 base = community->regs + community->hostown_offset; 1952 for (gpp = 0; gpp < community->ngpps; gpp++) 1953 intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]); 1954 } 1955 1956 return 0; 1957 } 1958 1959 EXPORT_NS_GPL_DEV_SLEEP_PM_OPS(intel_pinctrl_pm_ops, PINCTRL_INTEL) = { 1960 NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, intel_pinctrl_resume_noirq) 1961 }; 1962 1963 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1964 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1965 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1966 MODULE_LICENSE("GPL v2"); 1967 MODULE_IMPORT_NS("PWM_LPSS"); 1968