1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel pinctrl/GPIO core driver. 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/interrupt.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/log2.h> 14 #include <linux/platform_device.h> 15 #include <linux/pinctrl/pinctrl.h> 16 #include <linux/pinctrl/pinmux.h> 17 #include <linux/pinctrl/pinconf.h> 18 #include <linux/pinctrl/pinconf-generic.h> 19 20 #include "../core.h" 21 #include "pinctrl-intel.h" 22 23 /* Offset from regs */ 24 #define REVID 0x000 25 #define REVID_SHIFT 16 26 #define REVID_MASK GENMASK(31, 16) 27 28 #define PADBAR 0x00c 29 #define GPI_IS 0x100 30 31 #define PADOWN_BITS 4 32 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 33 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p)) 34 #define PADOWN_GPP(p) ((p) / 8) 35 36 /* Offset from pad_regs */ 37 #define PADCFG0 0x000 38 #define PADCFG0_RXEVCFG_SHIFT 25 39 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT) 40 #define PADCFG0_RXEVCFG_LEVEL 0 41 #define PADCFG0_RXEVCFG_EDGE 1 42 #define PADCFG0_RXEVCFG_DISABLED 2 43 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 44 #define PADCFG0_PREGFRXSEL BIT(24) 45 #define PADCFG0_RXINV BIT(23) 46 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 47 #define PADCFG0_GPIROUTSCI BIT(19) 48 #define PADCFG0_GPIROUTSMI BIT(18) 49 #define PADCFG0_GPIROUTNMI BIT(17) 50 #define PADCFG0_PMODE_SHIFT 10 51 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT) 52 #define PADCFG0_GPIORXDIS BIT(9) 53 #define PADCFG0_GPIOTXDIS BIT(8) 54 #define PADCFG0_GPIORXSTATE BIT(1) 55 #define PADCFG0_GPIOTXSTATE BIT(0) 56 57 #define PADCFG1 0x004 58 #define PADCFG1_TERM_UP BIT(13) 59 #define PADCFG1_TERM_SHIFT 10 60 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT) 61 #define PADCFG1_TERM_20K 4 62 #define PADCFG1_TERM_2K 3 63 #define PADCFG1_TERM_5K 2 64 #define PADCFG1_TERM_1K 1 65 66 #define PADCFG2 0x008 67 #define PADCFG2_DEBEN BIT(0) 68 #define PADCFG2_DEBOUNCE_SHIFT 1 69 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) 70 71 #define DEBOUNCE_PERIOD 31250 /* ns */ 72 73 struct intel_pad_context { 74 u32 padcfg0; 75 u32 padcfg1; 76 u32 padcfg2; 77 }; 78 79 struct intel_community_context { 80 u32 *intmask; 81 }; 82 83 struct intel_pinctrl_context { 84 struct intel_pad_context *pads; 85 struct intel_community_context *communities; 86 }; 87 88 /** 89 * struct intel_pinctrl - Intel pinctrl private structure 90 * @dev: Pointer to the device structure 91 * @lock: Lock to serialize register access 92 * @pctldesc: Pin controller description 93 * @pctldev: Pointer to the pin controller device 94 * @chip: GPIO chip in this pin controller 95 * @soc: SoC/PCH specific pin configuration data 96 * @communities: All communities in this pin controller 97 * @ncommunities: Number of communities in this pin controller 98 * @context: Configuration saved over system sleep 99 * @irq: pinctrl/GPIO chip irq number 100 */ 101 struct intel_pinctrl { 102 struct device *dev; 103 raw_spinlock_t lock; 104 struct pinctrl_desc pctldesc; 105 struct pinctrl_dev *pctldev; 106 struct gpio_chip chip; 107 const struct intel_pinctrl_soc_data *soc; 108 struct intel_community *communities; 109 size_t ncommunities; 110 struct intel_pinctrl_context context; 111 int irq; 112 }; 113 114 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 115 #define padgroup_offset(g, p) ((p) - (g)->base) 116 117 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 118 unsigned pin) 119 { 120 struct intel_community *community; 121 int i; 122 123 for (i = 0; i < pctrl->ncommunities; i++) { 124 community = &pctrl->communities[i]; 125 if (pin >= community->pin_base && 126 pin < community->pin_base + community->npins) 127 return community; 128 } 129 130 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 131 return NULL; 132 } 133 134 static const struct intel_padgroup * 135 intel_community_get_padgroup(const struct intel_community *community, 136 unsigned pin) 137 { 138 int i; 139 140 for (i = 0; i < community->ngpps; i++) { 141 const struct intel_padgroup *padgrp = &community->gpps[i]; 142 143 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) 144 return padgrp; 145 } 146 147 return NULL; 148 } 149 150 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, 151 unsigned reg) 152 { 153 const struct intel_community *community; 154 unsigned padno; 155 size_t nregs; 156 157 community = intel_get_community(pctrl, pin); 158 if (!community) 159 return NULL; 160 161 padno = pin_to_padno(community, pin); 162 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; 163 164 if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE)) 165 return NULL; 166 167 return community->pad_regs + reg + padno * nregs * 4; 168 } 169 170 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) 171 { 172 const struct intel_community *community; 173 const struct intel_padgroup *padgrp; 174 unsigned gpp, offset, gpp_offset; 175 void __iomem *padown; 176 177 community = intel_get_community(pctrl, pin); 178 if (!community) 179 return false; 180 if (!community->padown_offset) 181 return true; 182 183 padgrp = intel_community_get_padgroup(community, pin); 184 if (!padgrp) 185 return false; 186 187 gpp_offset = padgroup_offset(padgrp, pin); 188 gpp = PADOWN_GPP(gpp_offset); 189 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; 190 padown = community->regs + offset; 191 192 return !(readl(padown) & PADOWN_MASK(gpp_offset)); 193 } 194 195 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) 196 { 197 const struct intel_community *community; 198 const struct intel_padgroup *padgrp; 199 unsigned offset, gpp_offset; 200 void __iomem *hostown; 201 202 community = intel_get_community(pctrl, pin); 203 if (!community) 204 return true; 205 if (!community->hostown_offset) 206 return false; 207 208 padgrp = intel_community_get_padgroup(community, pin); 209 if (!padgrp) 210 return true; 211 212 gpp_offset = padgroup_offset(padgrp, pin); 213 offset = community->hostown_offset + padgrp->reg_num * 4; 214 hostown = community->regs + offset; 215 216 return !(readl(hostown) & BIT(gpp_offset)); 217 } 218 219 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) 220 { 221 struct intel_community *community; 222 const struct intel_padgroup *padgrp; 223 unsigned offset, gpp_offset; 224 u32 value; 225 226 community = intel_get_community(pctrl, pin); 227 if (!community) 228 return true; 229 if (!community->padcfglock_offset) 230 return false; 231 232 padgrp = intel_community_get_padgroup(community, pin); 233 if (!padgrp) 234 return true; 235 236 gpp_offset = padgroup_offset(padgrp, pin); 237 238 /* 239 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 240 * the pad is considered unlocked. Any other case means that it is 241 * either fully or partially locked and we don't touch it. 242 */ 243 offset = community->padcfglock_offset + padgrp->reg_num * 8; 244 value = readl(community->regs + offset); 245 if (value & BIT(gpp_offset)) 246 return true; 247 248 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; 249 value = readl(community->regs + offset); 250 if (value & BIT(gpp_offset)) 251 return true; 252 253 return false; 254 } 255 256 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) 257 { 258 return intel_pad_owned_by_host(pctrl, pin) && 259 !intel_pad_locked(pctrl, pin); 260 } 261 262 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 263 { 264 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 265 266 return pctrl->soc->ngroups; 267 } 268 269 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 270 unsigned group) 271 { 272 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 273 274 return pctrl->soc->groups[group].name; 275 } 276 277 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 278 const unsigned **pins, unsigned *npins) 279 { 280 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 281 282 *pins = pctrl->soc->groups[group].pins; 283 *npins = pctrl->soc->groups[group].npins; 284 return 0; 285 } 286 287 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 288 unsigned pin) 289 { 290 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 291 void __iomem *padcfg; 292 u32 cfg0, cfg1, mode; 293 bool locked, acpi; 294 295 if (!intel_pad_owned_by_host(pctrl, pin)) { 296 seq_puts(s, "not available"); 297 return; 298 } 299 300 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 301 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 302 303 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 304 if (!mode) 305 seq_puts(s, "GPIO "); 306 else 307 seq_printf(s, "mode %d ", mode); 308 309 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 310 311 /* Dump the additional PADCFG registers if available */ 312 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); 313 if (padcfg) 314 seq_printf(s, " 0x%08x", readl(padcfg)); 315 316 locked = intel_pad_locked(pctrl, pin); 317 acpi = intel_pad_acpi_mode(pctrl, pin); 318 319 if (locked || acpi) { 320 seq_puts(s, " ["); 321 if (locked) { 322 seq_puts(s, "LOCKED"); 323 if (acpi) 324 seq_puts(s, ", "); 325 } 326 if (acpi) 327 seq_puts(s, "ACPI"); 328 seq_puts(s, "]"); 329 } 330 } 331 332 static const struct pinctrl_ops intel_pinctrl_ops = { 333 .get_groups_count = intel_get_groups_count, 334 .get_group_name = intel_get_group_name, 335 .get_group_pins = intel_get_group_pins, 336 .pin_dbg_show = intel_pin_dbg_show, 337 }; 338 339 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 340 { 341 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 342 343 return pctrl->soc->nfunctions; 344 } 345 346 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 347 unsigned function) 348 { 349 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 350 351 return pctrl->soc->functions[function].name; 352 } 353 354 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 355 unsigned function, 356 const char * const **groups, 357 unsigned * const ngroups) 358 { 359 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 360 361 *groups = pctrl->soc->functions[function].groups; 362 *ngroups = pctrl->soc->functions[function].ngroups; 363 return 0; 364 } 365 366 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 367 unsigned group) 368 { 369 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 370 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 371 unsigned long flags; 372 int i; 373 374 raw_spin_lock_irqsave(&pctrl->lock, flags); 375 376 /* 377 * All pins in the groups needs to be accessible and writable 378 * before we can enable the mux for this group. 379 */ 380 for (i = 0; i < grp->npins; i++) { 381 if (!intel_pad_usable(pctrl, grp->pins[i])) { 382 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 383 return -EBUSY; 384 } 385 } 386 387 /* Now enable the mux setting for each pin in the group */ 388 for (i = 0; i < grp->npins; i++) { 389 void __iomem *padcfg0; 390 u32 value; 391 392 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); 393 value = readl(padcfg0); 394 395 value &= ~PADCFG0_PMODE_MASK; 396 397 if (grp->modes) 398 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; 399 else 400 value |= grp->mode << PADCFG0_PMODE_SHIFT; 401 402 writel(value, padcfg0); 403 } 404 405 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 406 407 return 0; 408 } 409 410 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) 411 { 412 u32 value; 413 414 value = readl(padcfg0); 415 if (input) { 416 value &= ~PADCFG0_GPIORXDIS; 417 value |= PADCFG0_GPIOTXDIS; 418 } else { 419 value &= ~PADCFG0_GPIOTXDIS; 420 value |= PADCFG0_GPIORXDIS; 421 } 422 writel(value, padcfg0); 423 } 424 425 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) 426 { 427 u32 value; 428 429 /* Put the pad into GPIO mode */ 430 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; 431 /* Disable SCI/SMI/NMI generation */ 432 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 433 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 434 writel(value, padcfg0); 435 } 436 437 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 438 struct pinctrl_gpio_range *range, 439 unsigned pin) 440 { 441 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 442 void __iomem *padcfg0; 443 unsigned long flags; 444 445 raw_spin_lock_irqsave(&pctrl->lock, flags); 446 447 if (!intel_pad_usable(pctrl, pin)) { 448 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 449 return -EBUSY; 450 } 451 452 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 453 intel_gpio_set_gpio_mode(padcfg0); 454 /* Disable TX buffer and enable RX (this will be input) */ 455 __intel_gpio_set_direction(padcfg0, true); 456 457 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 458 459 return 0; 460 } 461 462 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 463 struct pinctrl_gpio_range *range, 464 unsigned pin, bool input) 465 { 466 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 467 void __iomem *padcfg0; 468 unsigned long flags; 469 470 raw_spin_lock_irqsave(&pctrl->lock, flags); 471 472 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 473 __intel_gpio_set_direction(padcfg0, input); 474 475 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 476 477 return 0; 478 } 479 480 static const struct pinmux_ops intel_pinmux_ops = { 481 .get_functions_count = intel_get_functions_count, 482 .get_function_name = intel_get_function_name, 483 .get_function_groups = intel_get_function_groups, 484 .set_mux = intel_pinmux_set_mux, 485 .gpio_request_enable = intel_gpio_request_enable, 486 .gpio_set_direction = intel_gpio_set_direction, 487 }; 488 489 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, 490 unsigned long *config) 491 { 492 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 493 enum pin_config_param param = pinconf_to_config_param(*config); 494 const struct intel_community *community; 495 u32 value, term; 496 u32 arg = 0; 497 498 if (!intel_pad_owned_by_host(pctrl, pin)) 499 return -ENOTSUPP; 500 501 community = intel_get_community(pctrl, pin); 502 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 503 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 504 505 switch (param) { 506 case PIN_CONFIG_BIAS_DISABLE: 507 if (term) 508 return -EINVAL; 509 break; 510 511 case PIN_CONFIG_BIAS_PULL_UP: 512 if (!term || !(value & PADCFG1_TERM_UP)) 513 return -EINVAL; 514 515 switch (term) { 516 case PADCFG1_TERM_1K: 517 arg = 1000; 518 break; 519 case PADCFG1_TERM_2K: 520 arg = 2000; 521 break; 522 case PADCFG1_TERM_5K: 523 arg = 5000; 524 break; 525 case PADCFG1_TERM_20K: 526 arg = 20000; 527 break; 528 } 529 530 break; 531 532 case PIN_CONFIG_BIAS_PULL_DOWN: 533 if (!term || value & PADCFG1_TERM_UP) 534 return -EINVAL; 535 536 switch (term) { 537 case PADCFG1_TERM_1K: 538 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 539 return -EINVAL; 540 arg = 1000; 541 break; 542 case PADCFG1_TERM_5K: 543 arg = 5000; 544 break; 545 case PADCFG1_TERM_20K: 546 arg = 20000; 547 break; 548 } 549 550 break; 551 552 case PIN_CONFIG_INPUT_DEBOUNCE: { 553 void __iomem *padcfg2; 554 u32 v; 555 556 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 557 if (!padcfg2) 558 return -ENOTSUPP; 559 560 v = readl(padcfg2); 561 if (!(v & PADCFG2_DEBEN)) 562 return -EINVAL; 563 564 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; 565 arg = BIT(v) * DEBOUNCE_PERIOD / 1000; 566 567 break; 568 } 569 570 default: 571 return -ENOTSUPP; 572 } 573 574 *config = pinconf_to_config_packed(param, arg); 575 return 0; 576 } 577 578 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, 579 unsigned long config) 580 { 581 unsigned param = pinconf_to_config_param(config); 582 unsigned arg = pinconf_to_config_argument(config); 583 const struct intel_community *community; 584 void __iomem *padcfg1; 585 unsigned long flags; 586 int ret = 0; 587 u32 value; 588 589 raw_spin_lock_irqsave(&pctrl->lock, flags); 590 591 community = intel_get_community(pctrl, pin); 592 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 593 value = readl(padcfg1); 594 595 switch (param) { 596 case PIN_CONFIG_BIAS_DISABLE: 597 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 598 break; 599 600 case PIN_CONFIG_BIAS_PULL_UP: 601 value &= ~PADCFG1_TERM_MASK; 602 603 value |= PADCFG1_TERM_UP; 604 605 switch (arg) { 606 case 20000: 607 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 608 break; 609 case 5000: 610 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 611 break; 612 case 2000: 613 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; 614 break; 615 case 1000: 616 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 617 break; 618 default: 619 ret = -EINVAL; 620 } 621 622 break; 623 624 case PIN_CONFIG_BIAS_PULL_DOWN: 625 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); 626 627 switch (arg) { 628 case 20000: 629 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 630 break; 631 case 5000: 632 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 633 break; 634 case 1000: 635 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 636 ret = -EINVAL; 637 break; 638 } 639 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 640 break; 641 default: 642 ret = -EINVAL; 643 } 644 645 break; 646 } 647 648 if (!ret) 649 writel(value, padcfg1); 650 651 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 652 653 return ret; 654 } 655 656 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin, 657 unsigned debounce) 658 { 659 void __iomem *padcfg0, *padcfg2; 660 unsigned long flags; 661 u32 value0, value2; 662 int ret = 0; 663 664 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 665 if (!padcfg2) 666 return -ENOTSUPP; 667 668 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 669 670 raw_spin_lock_irqsave(&pctrl->lock, flags); 671 672 value0 = readl(padcfg0); 673 value2 = readl(padcfg2); 674 675 /* Disable glitch filter and debouncer */ 676 value0 &= ~PADCFG0_PREGFRXSEL; 677 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); 678 679 if (debounce) { 680 unsigned long v; 681 682 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD); 683 if (v < 3 || v > 15) { 684 ret = -EINVAL; 685 goto exit_unlock; 686 } else { 687 /* Enable glitch filter and debouncer */ 688 value0 |= PADCFG0_PREGFRXSEL; 689 value2 |= v << PADCFG2_DEBOUNCE_SHIFT; 690 value2 |= PADCFG2_DEBEN; 691 } 692 } 693 694 writel(value0, padcfg0); 695 writel(value2, padcfg2); 696 697 exit_unlock: 698 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 699 700 return ret; 701 } 702 703 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, 704 unsigned long *configs, unsigned nconfigs) 705 { 706 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 707 int i, ret; 708 709 if (!intel_pad_usable(pctrl, pin)) 710 return -ENOTSUPP; 711 712 for (i = 0; i < nconfigs; i++) { 713 switch (pinconf_to_config_param(configs[i])) { 714 case PIN_CONFIG_BIAS_DISABLE: 715 case PIN_CONFIG_BIAS_PULL_UP: 716 case PIN_CONFIG_BIAS_PULL_DOWN: 717 ret = intel_config_set_pull(pctrl, pin, configs[i]); 718 if (ret) 719 return ret; 720 break; 721 722 case PIN_CONFIG_INPUT_DEBOUNCE: 723 ret = intel_config_set_debounce(pctrl, pin, 724 pinconf_to_config_argument(configs[i])); 725 if (ret) 726 return ret; 727 break; 728 729 default: 730 return -ENOTSUPP; 731 } 732 } 733 734 return 0; 735 } 736 737 static const struct pinconf_ops intel_pinconf_ops = { 738 .is_generic = true, 739 .pin_config_get = intel_config_get, 740 .pin_config_set = intel_config_set, 741 }; 742 743 static const struct pinctrl_desc intel_pinctrl_desc = { 744 .pctlops = &intel_pinctrl_ops, 745 .pmxops = &intel_pinmux_ops, 746 .confops = &intel_pinconf_ops, 747 .owner = THIS_MODULE, 748 }; 749 750 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) 751 { 752 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 753 void __iomem *reg; 754 u32 padcfg0; 755 756 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 757 if (!reg) 758 return -EINVAL; 759 760 padcfg0 = readl(reg); 761 if (!(padcfg0 & PADCFG0_GPIOTXDIS)) 762 return !!(padcfg0 & PADCFG0_GPIOTXSTATE); 763 764 return !!(padcfg0 & PADCFG0_GPIORXSTATE); 765 } 766 767 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 768 { 769 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 770 unsigned long flags; 771 void __iomem *reg; 772 u32 padcfg0; 773 774 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 775 if (!reg) 776 return; 777 778 raw_spin_lock_irqsave(&pctrl->lock, flags); 779 padcfg0 = readl(reg); 780 if (value) 781 padcfg0 |= PADCFG0_GPIOTXSTATE; 782 else 783 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 784 writel(padcfg0, reg); 785 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 786 } 787 788 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 789 { 790 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 791 void __iomem *reg; 792 u32 padcfg0; 793 794 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 795 if (!reg) 796 return -EINVAL; 797 798 padcfg0 = readl(reg); 799 800 if (padcfg0 & PADCFG0_PMODE_MASK) 801 return -EINVAL; 802 803 return !!(padcfg0 & PADCFG0_GPIOTXDIS); 804 } 805 806 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 807 { 808 return pinctrl_gpio_direction_input(chip->base + offset); 809 } 810 811 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 812 int value) 813 { 814 intel_gpio_set(chip, offset, value); 815 return pinctrl_gpio_direction_output(chip->base + offset); 816 } 817 818 static const struct gpio_chip intel_gpio_chip = { 819 .owner = THIS_MODULE, 820 .request = gpiochip_generic_request, 821 .free = gpiochip_generic_free, 822 .get_direction = intel_gpio_get_direction, 823 .direction_input = intel_gpio_direction_input, 824 .direction_output = intel_gpio_direction_output, 825 .get = intel_gpio_get, 826 .set = intel_gpio_set, 827 .set_config = gpiochip_generic_config, 828 }; 829 830 /** 831 * intel_gpio_to_pin() - Translate from GPIO offset to pin number 832 * @pctrl: Pinctrl structure 833 * @offset: GPIO offset from gpiolib 834 * @commmunity: Community is filled here if not %NULL 835 * @padgrp: Pad group is filled here if not %NULL 836 * 837 * When coming through gpiolib irqchip, the GPIO offset is not 838 * automatically translated to pinctrl pin number. This function can be 839 * used to find out the corresponding pinctrl pin. 840 */ 841 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset, 842 const struct intel_community **community, 843 const struct intel_padgroup **padgrp) 844 { 845 int i; 846 847 for (i = 0; i < pctrl->ncommunities; i++) { 848 const struct intel_community *comm = &pctrl->communities[i]; 849 int j; 850 851 for (j = 0; j < comm->ngpps; j++) { 852 const struct intel_padgroup *pgrp = &comm->gpps[j]; 853 854 if (pgrp->gpio_base < 0) 855 continue; 856 857 if (offset >= pgrp->gpio_base && 858 offset < pgrp->gpio_base + pgrp->size) { 859 int pin; 860 861 pin = pgrp->base + offset - pgrp->gpio_base; 862 if (community) 863 *community = comm; 864 if (padgrp) 865 *padgrp = pgrp; 866 867 return pin; 868 } 869 } 870 } 871 872 return -EINVAL; 873 } 874 875 static int intel_gpio_irq_reqres(struct irq_data *d) 876 { 877 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 878 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 879 int pin; 880 881 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 882 if (pin >= 0) { 883 if (gpiochip_lock_as_irq(gc, pin)) { 884 dev_err(pctrl->dev, "unable to lock HW IRQ %d for IRQ\n", 885 pin); 886 return -EINVAL; 887 } 888 } 889 return 0; 890 } 891 892 static void intel_gpio_irq_relres(struct irq_data *d) 893 { 894 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 895 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 896 int pin; 897 898 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 899 if (pin >= 0) 900 gpiochip_unlock_as_irq(gc, pin); 901 } 902 903 static void intel_gpio_irq_ack(struct irq_data *d) 904 { 905 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 906 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 907 const struct intel_community *community; 908 const struct intel_padgroup *padgrp; 909 int pin; 910 911 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 912 if (pin >= 0) { 913 unsigned gpp, gpp_offset, is_offset; 914 915 gpp = padgrp->reg_num; 916 gpp_offset = padgroup_offset(padgrp, pin); 917 is_offset = community->is_offset + gpp * 4; 918 919 raw_spin_lock(&pctrl->lock); 920 writel(BIT(gpp_offset), community->regs + is_offset); 921 raw_spin_unlock(&pctrl->lock); 922 } 923 } 924 925 static void intel_gpio_irq_enable(struct irq_data *d) 926 { 927 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 928 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 929 const struct intel_community *community; 930 const struct intel_padgroup *padgrp; 931 int pin; 932 933 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 934 if (pin >= 0) { 935 unsigned gpp, gpp_offset, is_offset; 936 unsigned long flags; 937 u32 value; 938 939 gpp = padgrp->reg_num; 940 gpp_offset = padgroup_offset(padgrp, pin); 941 is_offset = community->is_offset + gpp * 4; 942 943 raw_spin_lock_irqsave(&pctrl->lock, flags); 944 /* Clear interrupt status first to avoid unexpected interrupt */ 945 writel(BIT(gpp_offset), community->regs + is_offset); 946 947 value = readl(community->regs + community->ie_offset + gpp * 4); 948 value |= BIT(gpp_offset); 949 writel(value, community->regs + community->ie_offset + gpp * 4); 950 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 951 } 952 } 953 954 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 955 { 956 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 957 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 958 const struct intel_community *community; 959 const struct intel_padgroup *padgrp; 960 int pin; 961 962 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 963 if (pin >= 0) { 964 unsigned gpp, gpp_offset; 965 unsigned long flags; 966 void __iomem *reg; 967 u32 value; 968 969 gpp = padgrp->reg_num; 970 gpp_offset = padgroup_offset(padgrp, pin); 971 972 reg = community->regs + community->ie_offset + gpp * 4; 973 974 raw_spin_lock_irqsave(&pctrl->lock, flags); 975 value = readl(reg); 976 if (mask) 977 value &= ~BIT(gpp_offset); 978 else 979 value |= BIT(gpp_offset); 980 writel(value, reg); 981 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 982 } 983 } 984 985 static void intel_gpio_irq_mask(struct irq_data *d) 986 { 987 intel_gpio_irq_mask_unmask(d, true); 988 } 989 990 static void intel_gpio_irq_unmask(struct irq_data *d) 991 { 992 intel_gpio_irq_mask_unmask(d, false); 993 } 994 995 static int intel_gpio_irq_type(struct irq_data *d, unsigned type) 996 { 997 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 998 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 999 unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1000 unsigned long flags; 1001 void __iomem *reg; 1002 u32 value; 1003 1004 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1005 if (!reg) 1006 return -EINVAL; 1007 1008 /* 1009 * If the pin is in ACPI mode it is still usable as a GPIO but it 1010 * cannot be used as IRQ because GPI_IS status bit will not be 1011 * updated by the host controller hardware. 1012 */ 1013 if (intel_pad_acpi_mode(pctrl, pin)) { 1014 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 1015 return -EPERM; 1016 } 1017 1018 raw_spin_lock_irqsave(&pctrl->lock, flags); 1019 1020 intel_gpio_set_gpio_mode(reg); 1021 1022 value = readl(reg); 1023 1024 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 1025 1026 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 1027 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 1028 } else if (type & IRQ_TYPE_EDGE_FALLING) { 1029 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1030 value |= PADCFG0_RXINV; 1031 } else if (type & IRQ_TYPE_EDGE_RISING) { 1032 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1033 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1034 if (type & IRQ_TYPE_LEVEL_LOW) 1035 value |= PADCFG0_RXINV; 1036 } else { 1037 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 1038 } 1039 1040 writel(value, reg); 1041 1042 if (type & IRQ_TYPE_EDGE_BOTH) 1043 irq_set_handler_locked(d, handle_edge_irq); 1044 else if (type & IRQ_TYPE_LEVEL_MASK) 1045 irq_set_handler_locked(d, handle_level_irq); 1046 1047 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1048 1049 return 0; 1050 } 1051 1052 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 1053 { 1054 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1055 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1056 unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1057 1058 if (on) 1059 enable_irq_wake(pctrl->irq); 1060 else 1061 disable_irq_wake(pctrl->irq); 1062 1063 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); 1064 return 0; 1065 } 1066 1067 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 1068 const struct intel_community *community) 1069 { 1070 struct gpio_chip *gc = &pctrl->chip; 1071 irqreturn_t ret = IRQ_NONE; 1072 int gpp; 1073 1074 for (gpp = 0; gpp < community->ngpps; gpp++) { 1075 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1076 unsigned long pending, enabled, gpp_offset; 1077 1078 pending = readl(community->regs + community->is_offset + 1079 padgrp->reg_num * 4); 1080 enabled = readl(community->regs + community->ie_offset + 1081 padgrp->reg_num * 4); 1082 1083 /* Only interrupts that are enabled */ 1084 pending &= enabled; 1085 1086 for_each_set_bit(gpp_offset, &pending, padgrp->size) { 1087 unsigned irq; 1088 1089 irq = irq_find_mapping(gc->irq.domain, 1090 padgrp->gpio_base + gpp_offset); 1091 generic_handle_irq(irq); 1092 1093 ret |= IRQ_HANDLED; 1094 } 1095 } 1096 1097 return ret; 1098 } 1099 1100 static irqreturn_t intel_gpio_irq(int irq, void *data) 1101 { 1102 const struct intel_community *community; 1103 struct intel_pinctrl *pctrl = data; 1104 irqreturn_t ret = IRQ_NONE; 1105 int i; 1106 1107 /* Need to check all communities for pending interrupts */ 1108 for (i = 0; i < pctrl->ncommunities; i++) { 1109 community = &pctrl->communities[i]; 1110 ret |= intel_gpio_community_irq_handler(pctrl, community); 1111 } 1112 1113 return ret; 1114 } 1115 1116 static struct irq_chip intel_gpio_irqchip = { 1117 .name = "intel-gpio", 1118 .irq_request_resources = intel_gpio_irq_reqres, 1119 .irq_release_resources = intel_gpio_irq_relres, 1120 .irq_enable = intel_gpio_irq_enable, 1121 .irq_ack = intel_gpio_irq_ack, 1122 .irq_mask = intel_gpio_irq_mask, 1123 .irq_unmask = intel_gpio_irq_unmask, 1124 .irq_set_type = intel_gpio_irq_type, 1125 .irq_set_wake = intel_gpio_irq_wake, 1126 .flags = IRQCHIP_MASK_ON_SUSPEND, 1127 }; 1128 1129 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl, 1130 const struct intel_community *community) 1131 { 1132 int ret = 0, i; 1133 1134 for (i = 0; i < community->ngpps; i++) { 1135 const struct intel_padgroup *gpp = &community->gpps[i]; 1136 1137 if (gpp->gpio_base < 0) 1138 continue; 1139 1140 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1141 gpp->gpio_base, gpp->base, 1142 gpp->size); 1143 if (ret) 1144 return ret; 1145 } 1146 1147 return ret; 1148 } 1149 1150 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1151 { 1152 const struct intel_community *community; 1153 unsigned ngpio = 0; 1154 int i, j; 1155 1156 for (i = 0; i < pctrl->ncommunities; i++) { 1157 community = &pctrl->communities[i]; 1158 for (j = 0; j < community->ngpps; j++) { 1159 const struct intel_padgroup *gpp = &community->gpps[j]; 1160 1161 if (gpp->gpio_base < 0) 1162 continue; 1163 1164 if (gpp->gpio_base + gpp->size > ngpio) 1165 ngpio = gpp->gpio_base + gpp->size; 1166 } 1167 } 1168 1169 return ngpio; 1170 } 1171 1172 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1173 { 1174 int ret, i; 1175 1176 pctrl->chip = intel_gpio_chip; 1177 1178 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); 1179 pctrl->chip.label = dev_name(pctrl->dev); 1180 pctrl->chip.parent = pctrl->dev; 1181 pctrl->chip.base = -1; 1182 pctrl->irq = irq; 1183 1184 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1185 if (ret) { 1186 dev_err(pctrl->dev, "failed to register gpiochip\n"); 1187 return ret; 1188 } 1189 1190 for (i = 0; i < pctrl->ncommunities; i++) { 1191 struct intel_community *community = &pctrl->communities[i]; 1192 1193 ret = intel_gpio_add_pin_ranges(pctrl, community); 1194 if (ret) { 1195 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1196 return ret; 1197 } 1198 } 1199 1200 /* 1201 * We need to request the interrupt here (instead of providing chip 1202 * to the irq directly) because on some platforms several GPIO 1203 * controllers share the same interrupt line. 1204 */ 1205 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1206 IRQF_SHARED | IRQF_NO_THREAD, 1207 dev_name(pctrl->dev), pctrl); 1208 if (ret) { 1209 dev_err(pctrl->dev, "failed to request interrupt\n"); 1210 return ret; 1211 } 1212 1213 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, 1214 handle_bad_irq, IRQ_TYPE_NONE); 1215 if (ret) { 1216 dev_err(pctrl->dev, "failed to add irqchip\n"); 1217 return ret; 1218 } 1219 1220 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, 1221 NULL); 1222 return 0; 1223 } 1224 1225 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, 1226 struct intel_community *community) 1227 { 1228 struct intel_padgroup *gpps; 1229 unsigned npins = community->npins; 1230 unsigned padown_num = 0; 1231 size_t ngpps, i; 1232 1233 if (community->gpps) 1234 ngpps = community->ngpps; 1235 else 1236 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size); 1237 1238 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1239 if (!gpps) 1240 return -ENOMEM; 1241 1242 for (i = 0; i < ngpps; i++) { 1243 if (community->gpps) { 1244 gpps[i] = community->gpps[i]; 1245 } else { 1246 unsigned gpp_size = community->gpp_size; 1247 1248 gpps[i].reg_num = i; 1249 gpps[i].base = community->pin_base + i * gpp_size; 1250 gpps[i].size = min(gpp_size, npins); 1251 npins -= gpps[i].size; 1252 } 1253 1254 if (gpps[i].size > 32) 1255 return -EINVAL; 1256 1257 if (!gpps[i].gpio_base) 1258 gpps[i].gpio_base = gpps[i].base; 1259 1260 gpps[i].padown_num = padown_num; 1261 1262 /* 1263 * In older hardware the number of padown registers per 1264 * group is fixed regardless of the group size. 1265 */ 1266 if (community->gpp_num_padown_regs) 1267 padown_num += community->gpp_num_padown_regs; 1268 else 1269 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); 1270 } 1271 1272 community->ngpps = ngpps; 1273 community->gpps = gpps; 1274 1275 return 0; 1276 } 1277 1278 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 1279 { 1280 #ifdef CONFIG_PM_SLEEP 1281 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 1282 struct intel_community_context *communities; 1283 struct intel_pad_context *pads; 1284 int i; 1285 1286 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 1287 if (!pads) 1288 return -ENOMEM; 1289 1290 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 1291 sizeof(*communities), GFP_KERNEL); 1292 if (!communities) 1293 return -ENOMEM; 1294 1295 1296 for (i = 0; i < pctrl->ncommunities; i++) { 1297 struct intel_community *community = &pctrl->communities[i]; 1298 u32 *intmask; 1299 1300 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1301 sizeof(*intmask), GFP_KERNEL); 1302 if (!intmask) 1303 return -ENOMEM; 1304 1305 communities[i].intmask = intmask; 1306 } 1307 1308 pctrl->context.pads = pads; 1309 pctrl->context.communities = communities; 1310 #endif 1311 1312 return 0; 1313 } 1314 1315 int intel_pinctrl_probe(struct platform_device *pdev, 1316 const struct intel_pinctrl_soc_data *soc_data) 1317 { 1318 struct intel_pinctrl *pctrl; 1319 int i, ret, irq; 1320 1321 if (!soc_data) 1322 return -EINVAL; 1323 1324 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1325 if (!pctrl) 1326 return -ENOMEM; 1327 1328 pctrl->dev = &pdev->dev; 1329 pctrl->soc = soc_data; 1330 raw_spin_lock_init(&pctrl->lock); 1331 1332 /* 1333 * Make a copy of the communities which we can use to hold pointers 1334 * to the registers. 1335 */ 1336 pctrl->ncommunities = pctrl->soc->ncommunities; 1337 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, 1338 sizeof(*pctrl->communities), GFP_KERNEL); 1339 if (!pctrl->communities) 1340 return -ENOMEM; 1341 1342 for (i = 0; i < pctrl->ncommunities; i++) { 1343 struct intel_community *community = &pctrl->communities[i]; 1344 struct resource *res; 1345 void __iomem *regs; 1346 u32 padbar; 1347 1348 *community = pctrl->soc->communities[i]; 1349 1350 res = platform_get_resource(pdev, IORESOURCE_MEM, 1351 community->barno); 1352 regs = devm_ioremap_resource(&pdev->dev, res); 1353 if (IS_ERR(regs)) 1354 return PTR_ERR(regs); 1355 1356 /* 1357 * Determine community features based on the revision if 1358 * not specified already. 1359 */ 1360 if (!community->features) { 1361 u32 rev; 1362 1363 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT; 1364 if (rev >= 0x94) { 1365 community->features |= PINCTRL_FEATURE_DEBOUNCE; 1366 community->features |= PINCTRL_FEATURE_1K_PD; 1367 } 1368 } 1369 1370 /* Read offset of the pad configuration registers */ 1371 padbar = readl(regs + PADBAR); 1372 1373 community->regs = regs; 1374 community->pad_regs = regs + padbar; 1375 1376 if (!community->is_offset) 1377 community->is_offset = GPI_IS; 1378 1379 ret = intel_pinctrl_add_padgroups(pctrl, community); 1380 if (ret) 1381 return ret; 1382 } 1383 1384 irq = platform_get_irq(pdev, 0); 1385 if (irq < 0) { 1386 dev_err(&pdev->dev, "failed to get interrupt number\n"); 1387 return irq; 1388 } 1389 1390 ret = intel_pinctrl_pm_init(pctrl); 1391 if (ret) 1392 return ret; 1393 1394 pctrl->pctldesc = intel_pinctrl_desc; 1395 pctrl->pctldesc.name = dev_name(&pdev->dev); 1396 pctrl->pctldesc.pins = pctrl->soc->pins; 1397 pctrl->pctldesc.npins = pctrl->soc->npins; 1398 1399 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1400 pctrl); 1401 if (IS_ERR(pctrl->pctldev)) { 1402 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1403 return PTR_ERR(pctrl->pctldev); 1404 } 1405 1406 ret = intel_gpio_probe(pctrl, irq); 1407 if (ret) 1408 return ret; 1409 1410 platform_set_drvdata(pdev, pctrl); 1411 1412 return 0; 1413 } 1414 EXPORT_SYMBOL_GPL(intel_pinctrl_probe); 1415 1416 #ifdef CONFIG_PM_SLEEP 1417 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin) 1418 { 1419 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1420 1421 if (!pd || !intel_pad_usable(pctrl, pin)) 1422 return false; 1423 1424 /* 1425 * Only restore the pin if it is actually in use by the kernel (or 1426 * by userspace). It is possible that some pins are used by the 1427 * BIOS during resume and those are not always locked down so leave 1428 * them alone. 1429 */ 1430 if (pd->mux_owner || pd->gpio_owner || 1431 gpiochip_line_is_irq(&pctrl->chip, pin)) 1432 return true; 1433 1434 return false; 1435 } 1436 1437 int intel_pinctrl_suspend(struct device *dev) 1438 { 1439 struct platform_device *pdev = to_platform_device(dev); 1440 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1441 struct intel_community_context *communities; 1442 struct intel_pad_context *pads; 1443 int i; 1444 1445 pads = pctrl->context.pads; 1446 for (i = 0; i < pctrl->soc->npins; i++) { 1447 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1448 void __iomem *padcfg; 1449 u32 val; 1450 1451 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1452 continue; 1453 1454 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1455 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1456 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1457 pads[i].padcfg1 = val; 1458 1459 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1460 if (padcfg) 1461 pads[i].padcfg2 = readl(padcfg); 1462 } 1463 1464 communities = pctrl->context.communities; 1465 for (i = 0; i < pctrl->ncommunities; i++) { 1466 struct intel_community *community = &pctrl->communities[i]; 1467 void __iomem *base; 1468 unsigned gpp; 1469 1470 base = community->regs + community->ie_offset; 1471 for (gpp = 0; gpp < community->ngpps; gpp++) 1472 communities[i].intmask[gpp] = readl(base + gpp * 4); 1473 } 1474 1475 return 0; 1476 } 1477 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); 1478 1479 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1480 { 1481 size_t i; 1482 1483 for (i = 0; i < pctrl->ncommunities; i++) { 1484 const struct intel_community *community; 1485 void __iomem *base; 1486 unsigned gpp; 1487 1488 community = &pctrl->communities[i]; 1489 base = community->regs; 1490 1491 for (gpp = 0; gpp < community->ngpps; gpp++) { 1492 /* Mask and clear all interrupts */ 1493 writel(0, base + community->ie_offset + gpp * 4); 1494 writel(0xffff, base + community->is_offset + gpp * 4); 1495 } 1496 } 1497 } 1498 1499 int intel_pinctrl_resume(struct device *dev) 1500 { 1501 struct platform_device *pdev = to_platform_device(dev); 1502 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1503 const struct intel_community_context *communities; 1504 const struct intel_pad_context *pads; 1505 int i; 1506 1507 /* Mask all interrupts */ 1508 intel_gpio_irq_init(pctrl); 1509 1510 pads = pctrl->context.pads; 1511 for (i = 0; i < pctrl->soc->npins; i++) { 1512 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1513 void __iomem *padcfg; 1514 u32 val; 1515 1516 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1517 continue; 1518 1519 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); 1520 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; 1521 if (val != pads[i].padcfg0) { 1522 writel(pads[i].padcfg0, padcfg); 1523 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", 1524 desc->number, readl(padcfg)); 1525 } 1526 1527 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); 1528 val = readl(padcfg); 1529 if (val != pads[i].padcfg1) { 1530 writel(pads[i].padcfg1, padcfg); 1531 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", 1532 desc->number, readl(padcfg)); 1533 } 1534 1535 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1536 if (padcfg) { 1537 val = readl(padcfg); 1538 if (val != pads[i].padcfg2) { 1539 writel(pads[i].padcfg2, padcfg); 1540 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n", 1541 desc->number, readl(padcfg)); 1542 } 1543 } 1544 } 1545 1546 communities = pctrl->context.communities; 1547 for (i = 0; i < pctrl->ncommunities; i++) { 1548 struct intel_community *community = &pctrl->communities[i]; 1549 void __iomem *base; 1550 unsigned gpp; 1551 1552 base = community->regs + community->ie_offset; 1553 for (gpp = 0; gpp < community->ngpps; gpp++) { 1554 writel(communities[i].intmask[gpp], base + gpp * 4); 1555 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, 1556 readl(base + gpp * 4)); 1557 } 1558 } 1559 1560 return 0; 1561 } 1562 EXPORT_SYMBOL_GPL(intel_pinctrl_resume); 1563 #endif 1564 1565 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1566 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1567 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1568 MODULE_LICENSE("GPL v2"); 1569