1 /* 2 * Intel pinctrl/GPIO core driver. 3 * 4 * Copyright (C) 2015, Intel Corporation 5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 6 * Mika Westerberg <mika.westerberg@linux.intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/interrupt.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/log2.h> 17 #include <linux/platform_device.h> 18 #include <linux/pinctrl/pinctrl.h> 19 #include <linux/pinctrl/pinmux.h> 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 23 #include "../core.h" 24 #include "pinctrl-intel.h" 25 26 /* Offset from regs */ 27 #define REVID 0x000 28 #define REVID_SHIFT 16 29 #define REVID_MASK GENMASK(31, 16) 30 31 #define PADBAR 0x00c 32 #define GPI_IS 0x100 33 34 #define PADOWN_BITS 4 35 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 36 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p)) 37 #define PADOWN_GPP(p) ((p) / 8) 38 39 /* Offset from pad_regs */ 40 #define PADCFG0 0x000 41 #define PADCFG0_RXEVCFG_SHIFT 25 42 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT) 43 #define PADCFG0_RXEVCFG_LEVEL 0 44 #define PADCFG0_RXEVCFG_EDGE 1 45 #define PADCFG0_RXEVCFG_DISABLED 2 46 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 47 #define PADCFG0_PREGFRXSEL BIT(24) 48 #define PADCFG0_RXINV BIT(23) 49 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 50 #define PADCFG0_GPIROUTSCI BIT(19) 51 #define PADCFG0_GPIROUTSMI BIT(18) 52 #define PADCFG0_GPIROUTNMI BIT(17) 53 #define PADCFG0_PMODE_SHIFT 10 54 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT) 55 #define PADCFG0_GPIORXDIS BIT(9) 56 #define PADCFG0_GPIOTXDIS BIT(8) 57 #define PADCFG0_GPIORXSTATE BIT(1) 58 #define PADCFG0_GPIOTXSTATE BIT(0) 59 60 #define PADCFG1 0x004 61 #define PADCFG1_TERM_UP BIT(13) 62 #define PADCFG1_TERM_SHIFT 10 63 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT) 64 #define PADCFG1_TERM_20K 4 65 #define PADCFG1_TERM_2K 3 66 #define PADCFG1_TERM_5K 2 67 #define PADCFG1_TERM_1K 1 68 69 #define PADCFG2 0x008 70 #define PADCFG2_DEBEN BIT(0) 71 #define PADCFG2_DEBOUNCE_SHIFT 1 72 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) 73 74 #define DEBOUNCE_PERIOD 31250 /* ns */ 75 76 struct intel_pad_context { 77 u32 padcfg0; 78 u32 padcfg1; 79 u32 padcfg2; 80 }; 81 82 struct intel_community_context { 83 u32 *intmask; 84 }; 85 86 struct intel_pinctrl_context { 87 struct intel_pad_context *pads; 88 struct intel_community_context *communities; 89 }; 90 91 /** 92 * struct intel_pinctrl - Intel pinctrl private structure 93 * @dev: Pointer to the device structure 94 * @lock: Lock to serialize register access 95 * @pctldesc: Pin controller description 96 * @pctldev: Pointer to the pin controller device 97 * @chip: GPIO chip in this pin controller 98 * @soc: SoC/PCH specific pin configuration data 99 * @communities: All communities in this pin controller 100 * @ncommunities: Number of communities in this pin controller 101 * @context: Configuration saved over system sleep 102 * @irq: pinctrl/GPIO chip irq number 103 */ 104 struct intel_pinctrl { 105 struct device *dev; 106 raw_spinlock_t lock; 107 struct pinctrl_desc pctldesc; 108 struct pinctrl_dev *pctldev; 109 struct gpio_chip chip; 110 const struct intel_pinctrl_soc_data *soc; 111 struct intel_community *communities; 112 size_t ncommunities; 113 struct intel_pinctrl_context context; 114 int irq; 115 }; 116 117 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 118 #define padgroup_offset(g, p) ((p) - (g)->base) 119 120 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 121 unsigned pin) 122 { 123 struct intel_community *community; 124 int i; 125 126 for (i = 0; i < pctrl->ncommunities; i++) { 127 community = &pctrl->communities[i]; 128 if (pin >= community->pin_base && 129 pin < community->pin_base + community->npins) 130 return community; 131 } 132 133 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 134 return NULL; 135 } 136 137 static const struct intel_padgroup * 138 intel_community_get_padgroup(const struct intel_community *community, 139 unsigned pin) 140 { 141 int i; 142 143 for (i = 0; i < community->ngpps; i++) { 144 const struct intel_padgroup *padgrp = &community->gpps[i]; 145 146 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) 147 return padgrp; 148 } 149 150 return NULL; 151 } 152 153 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, 154 unsigned reg) 155 { 156 const struct intel_community *community; 157 unsigned padno; 158 size_t nregs; 159 160 community = intel_get_community(pctrl, pin); 161 if (!community) 162 return NULL; 163 164 padno = pin_to_padno(community, pin); 165 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; 166 167 if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE)) 168 return NULL; 169 170 return community->pad_regs + reg + padno * nregs * 4; 171 } 172 173 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) 174 { 175 const struct intel_community *community; 176 const struct intel_padgroup *padgrp; 177 unsigned gpp, offset, gpp_offset; 178 void __iomem *padown; 179 180 community = intel_get_community(pctrl, pin); 181 if (!community) 182 return false; 183 if (!community->padown_offset) 184 return true; 185 186 padgrp = intel_community_get_padgroup(community, pin); 187 if (!padgrp) 188 return false; 189 190 gpp_offset = padgroup_offset(padgrp, pin); 191 gpp = PADOWN_GPP(gpp_offset); 192 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; 193 padown = community->regs + offset; 194 195 return !(readl(padown) & PADOWN_MASK(gpp_offset)); 196 } 197 198 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) 199 { 200 const struct intel_community *community; 201 const struct intel_padgroup *padgrp; 202 unsigned offset, gpp_offset; 203 void __iomem *hostown; 204 205 community = intel_get_community(pctrl, pin); 206 if (!community) 207 return true; 208 if (!community->hostown_offset) 209 return false; 210 211 padgrp = intel_community_get_padgroup(community, pin); 212 if (!padgrp) 213 return true; 214 215 gpp_offset = padgroup_offset(padgrp, pin); 216 offset = community->hostown_offset + padgrp->reg_num * 4; 217 hostown = community->regs + offset; 218 219 return !(readl(hostown) & BIT(gpp_offset)); 220 } 221 222 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) 223 { 224 struct intel_community *community; 225 const struct intel_padgroup *padgrp; 226 unsigned offset, gpp_offset; 227 u32 value; 228 229 community = intel_get_community(pctrl, pin); 230 if (!community) 231 return true; 232 if (!community->padcfglock_offset) 233 return false; 234 235 padgrp = intel_community_get_padgroup(community, pin); 236 if (!padgrp) 237 return true; 238 239 gpp_offset = padgroup_offset(padgrp, pin); 240 241 /* 242 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 243 * the pad is considered unlocked. Any other case means that it is 244 * either fully or partially locked and we don't touch it. 245 */ 246 offset = community->padcfglock_offset + padgrp->reg_num * 8; 247 value = readl(community->regs + offset); 248 if (value & BIT(gpp_offset)) 249 return true; 250 251 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; 252 value = readl(community->regs + offset); 253 if (value & BIT(gpp_offset)) 254 return true; 255 256 return false; 257 } 258 259 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) 260 { 261 return intel_pad_owned_by_host(pctrl, pin) && 262 !intel_pad_locked(pctrl, pin); 263 } 264 265 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 266 { 267 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 268 269 return pctrl->soc->ngroups; 270 } 271 272 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 273 unsigned group) 274 { 275 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 276 277 return pctrl->soc->groups[group].name; 278 } 279 280 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 281 const unsigned **pins, unsigned *npins) 282 { 283 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 284 285 *pins = pctrl->soc->groups[group].pins; 286 *npins = pctrl->soc->groups[group].npins; 287 return 0; 288 } 289 290 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 291 unsigned pin) 292 { 293 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 294 void __iomem *padcfg; 295 u32 cfg0, cfg1, mode; 296 bool locked, acpi; 297 298 if (!intel_pad_owned_by_host(pctrl, pin)) { 299 seq_puts(s, "not available"); 300 return; 301 } 302 303 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 304 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 305 306 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 307 if (!mode) 308 seq_puts(s, "GPIO "); 309 else 310 seq_printf(s, "mode %d ", mode); 311 312 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 313 314 /* Dump the additional PADCFG registers if available */ 315 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); 316 if (padcfg) 317 seq_printf(s, " 0x%08x", readl(padcfg)); 318 319 locked = intel_pad_locked(pctrl, pin); 320 acpi = intel_pad_acpi_mode(pctrl, pin); 321 322 if (locked || acpi) { 323 seq_puts(s, " ["); 324 if (locked) { 325 seq_puts(s, "LOCKED"); 326 if (acpi) 327 seq_puts(s, ", "); 328 } 329 if (acpi) 330 seq_puts(s, "ACPI"); 331 seq_puts(s, "]"); 332 } 333 } 334 335 static const struct pinctrl_ops intel_pinctrl_ops = { 336 .get_groups_count = intel_get_groups_count, 337 .get_group_name = intel_get_group_name, 338 .get_group_pins = intel_get_group_pins, 339 .pin_dbg_show = intel_pin_dbg_show, 340 }; 341 342 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 343 { 344 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 345 346 return pctrl->soc->nfunctions; 347 } 348 349 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 350 unsigned function) 351 { 352 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 353 354 return pctrl->soc->functions[function].name; 355 } 356 357 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 358 unsigned function, 359 const char * const **groups, 360 unsigned * const ngroups) 361 { 362 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 363 364 *groups = pctrl->soc->functions[function].groups; 365 *ngroups = pctrl->soc->functions[function].ngroups; 366 return 0; 367 } 368 369 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 370 unsigned group) 371 { 372 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 373 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 374 unsigned long flags; 375 int i; 376 377 raw_spin_lock_irqsave(&pctrl->lock, flags); 378 379 /* 380 * All pins in the groups needs to be accessible and writable 381 * before we can enable the mux for this group. 382 */ 383 for (i = 0; i < grp->npins; i++) { 384 if (!intel_pad_usable(pctrl, grp->pins[i])) { 385 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 386 return -EBUSY; 387 } 388 } 389 390 /* Now enable the mux setting for each pin in the group */ 391 for (i = 0; i < grp->npins; i++) { 392 void __iomem *padcfg0; 393 u32 value; 394 395 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); 396 value = readl(padcfg0); 397 398 value &= ~PADCFG0_PMODE_MASK; 399 400 if (grp->modes) 401 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; 402 else 403 value |= grp->mode << PADCFG0_PMODE_SHIFT; 404 405 writel(value, padcfg0); 406 } 407 408 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 409 410 return 0; 411 } 412 413 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) 414 { 415 u32 value; 416 417 value = readl(padcfg0); 418 if (input) { 419 value &= ~PADCFG0_GPIORXDIS; 420 value |= PADCFG0_GPIOTXDIS; 421 } else { 422 value &= ~PADCFG0_GPIOTXDIS; 423 value |= PADCFG0_GPIORXDIS; 424 } 425 writel(value, padcfg0); 426 } 427 428 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 429 struct pinctrl_gpio_range *range, 430 unsigned pin) 431 { 432 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 433 void __iomem *padcfg0; 434 unsigned long flags; 435 u32 value; 436 437 raw_spin_lock_irqsave(&pctrl->lock, flags); 438 439 if (!intel_pad_usable(pctrl, pin)) { 440 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 441 return -EBUSY; 442 } 443 444 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 445 /* Put the pad into GPIO mode */ 446 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; 447 /* Disable SCI/SMI/NMI generation */ 448 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 449 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 450 writel(value, padcfg0); 451 452 /* Disable TX buffer and enable RX (this will be input) */ 453 __intel_gpio_set_direction(padcfg0, true); 454 455 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 456 457 return 0; 458 } 459 460 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 461 struct pinctrl_gpio_range *range, 462 unsigned pin, bool input) 463 { 464 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 465 void __iomem *padcfg0; 466 unsigned long flags; 467 468 raw_spin_lock_irqsave(&pctrl->lock, flags); 469 470 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 471 __intel_gpio_set_direction(padcfg0, input); 472 473 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 474 475 return 0; 476 } 477 478 static const struct pinmux_ops intel_pinmux_ops = { 479 .get_functions_count = intel_get_functions_count, 480 .get_function_name = intel_get_function_name, 481 .get_function_groups = intel_get_function_groups, 482 .set_mux = intel_pinmux_set_mux, 483 .gpio_request_enable = intel_gpio_request_enable, 484 .gpio_set_direction = intel_gpio_set_direction, 485 }; 486 487 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, 488 unsigned long *config) 489 { 490 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 491 enum pin_config_param param = pinconf_to_config_param(*config); 492 const struct intel_community *community; 493 u32 value, term; 494 u32 arg = 0; 495 496 if (!intel_pad_owned_by_host(pctrl, pin)) 497 return -ENOTSUPP; 498 499 community = intel_get_community(pctrl, pin); 500 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 501 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 502 503 switch (param) { 504 case PIN_CONFIG_BIAS_DISABLE: 505 if (term) 506 return -EINVAL; 507 break; 508 509 case PIN_CONFIG_BIAS_PULL_UP: 510 if (!term || !(value & PADCFG1_TERM_UP)) 511 return -EINVAL; 512 513 switch (term) { 514 case PADCFG1_TERM_1K: 515 arg = 1000; 516 break; 517 case PADCFG1_TERM_2K: 518 arg = 2000; 519 break; 520 case PADCFG1_TERM_5K: 521 arg = 5000; 522 break; 523 case PADCFG1_TERM_20K: 524 arg = 20000; 525 break; 526 } 527 528 break; 529 530 case PIN_CONFIG_BIAS_PULL_DOWN: 531 if (!term || value & PADCFG1_TERM_UP) 532 return -EINVAL; 533 534 switch (term) { 535 case PADCFG1_TERM_1K: 536 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 537 return -EINVAL; 538 arg = 1000; 539 break; 540 case PADCFG1_TERM_5K: 541 arg = 5000; 542 break; 543 case PADCFG1_TERM_20K: 544 arg = 20000; 545 break; 546 } 547 548 break; 549 550 case PIN_CONFIG_INPUT_DEBOUNCE: { 551 void __iomem *padcfg2; 552 u32 v; 553 554 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 555 if (!padcfg2) 556 return -ENOTSUPP; 557 558 v = readl(padcfg2); 559 if (!(v & PADCFG2_DEBEN)) 560 return -EINVAL; 561 562 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; 563 arg = BIT(v) * DEBOUNCE_PERIOD / 1000; 564 565 break; 566 } 567 568 default: 569 return -ENOTSUPP; 570 } 571 572 *config = pinconf_to_config_packed(param, arg); 573 return 0; 574 } 575 576 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, 577 unsigned long config) 578 { 579 unsigned param = pinconf_to_config_param(config); 580 unsigned arg = pinconf_to_config_argument(config); 581 const struct intel_community *community; 582 void __iomem *padcfg1; 583 unsigned long flags; 584 int ret = 0; 585 u32 value; 586 587 raw_spin_lock_irqsave(&pctrl->lock, flags); 588 589 community = intel_get_community(pctrl, pin); 590 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 591 value = readl(padcfg1); 592 593 switch (param) { 594 case PIN_CONFIG_BIAS_DISABLE: 595 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 596 break; 597 598 case PIN_CONFIG_BIAS_PULL_UP: 599 value &= ~PADCFG1_TERM_MASK; 600 601 value |= PADCFG1_TERM_UP; 602 603 switch (arg) { 604 case 20000: 605 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 606 break; 607 case 5000: 608 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 609 break; 610 case 2000: 611 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; 612 break; 613 case 1000: 614 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 615 break; 616 default: 617 ret = -EINVAL; 618 } 619 620 break; 621 622 case PIN_CONFIG_BIAS_PULL_DOWN: 623 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); 624 625 switch (arg) { 626 case 20000: 627 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 628 break; 629 case 5000: 630 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 631 break; 632 case 1000: 633 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 634 ret = -EINVAL; 635 break; 636 } 637 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 638 break; 639 default: 640 ret = -EINVAL; 641 } 642 643 break; 644 } 645 646 if (!ret) 647 writel(value, padcfg1); 648 649 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 650 651 return ret; 652 } 653 654 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin, 655 unsigned debounce) 656 { 657 void __iomem *padcfg0, *padcfg2; 658 unsigned long flags; 659 u32 value0, value2; 660 int ret = 0; 661 662 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 663 if (!padcfg2) 664 return -ENOTSUPP; 665 666 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 667 668 raw_spin_lock_irqsave(&pctrl->lock, flags); 669 670 value0 = readl(padcfg0); 671 value2 = readl(padcfg2); 672 673 /* Disable glitch filter and debouncer */ 674 value0 &= ~PADCFG0_PREGFRXSEL; 675 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); 676 677 if (debounce) { 678 unsigned long v; 679 680 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD); 681 if (v < 3 || v > 15) { 682 ret = -EINVAL; 683 goto exit_unlock; 684 } else { 685 /* Enable glitch filter and debouncer */ 686 value0 |= PADCFG0_PREGFRXSEL; 687 value2 |= v << PADCFG2_DEBOUNCE_SHIFT; 688 value2 |= PADCFG2_DEBEN; 689 } 690 } 691 692 writel(value0, padcfg0); 693 writel(value2, padcfg2); 694 695 exit_unlock: 696 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 697 698 return ret; 699 } 700 701 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, 702 unsigned long *configs, unsigned nconfigs) 703 { 704 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 705 int i, ret; 706 707 if (!intel_pad_usable(pctrl, pin)) 708 return -ENOTSUPP; 709 710 for (i = 0; i < nconfigs; i++) { 711 switch (pinconf_to_config_param(configs[i])) { 712 case PIN_CONFIG_BIAS_DISABLE: 713 case PIN_CONFIG_BIAS_PULL_UP: 714 case PIN_CONFIG_BIAS_PULL_DOWN: 715 ret = intel_config_set_pull(pctrl, pin, configs[i]); 716 if (ret) 717 return ret; 718 break; 719 720 case PIN_CONFIG_INPUT_DEBOUNCE: 721 ret = intel_config_set_debounce(pctrl, pin, 722 pinconf_to_config_argument(configs[i])); 723 if (ret) 724 return ret; 725 break; 726 727 default: 728 return -ENOTSUPP; 729 } 730 } 731 732 return 0; 733 } 734 735 static const struct pinconf_ops intel_pinconf_ops = { 736 .is_generic = true, 737 .pin_config_get = intel_config_get, 738 .pin_config_set = intel_config_set, 739 }; 740 741 static const struct pinctrl_desc intel_pinctrl_desc = { 742 .pctlops = &intel_pinctrl_ops, 743 .pmxops = &intel_pinmux_ops, 744 .confops = &intel_pinconf_ops, 745 .owner = THIS_MODULE, 746 }; 747 748 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) 749 { 750 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 751 void __iomem *reg; 752 u32 padcfg0; 753 754 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 755 if (!reg) 756 return -EINVAL; 757 758 padcfg0 = readl(reg); 759 if (!(padcfg0 & PADCFG0_GPIOTXDIS)) 760 return !!(padcfg0 & PADCFG0_GPIOTXSTATE); 761 762 return !!(padcfg0 & PADCFG0_GPIORXSTATE); 763 } 764 765 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 766 { 767 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 768 unsigned long flags; 769 void __iomem *reg; 770 u32 padcfg0; 771 772 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 773 if (!reg) 774 return; 775 776 raw_spin_lock_irqsave(&pctrl->lock, flags); 777 padcfg0 = readl(reg); 778 if (value) 779 padcfg0 |= PADCFG0_GPIOTXSTATE; 780 else 781 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 782 writel(padcfg0, reg); 783 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 784 } 785 786 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 787 { 788 return pinctrl_gpio_direction_input(chip->base + offset); 789 } 790 791 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 792 int value) 793 { 794 intel_gpio_set(chip, offset, value); 795 return pinctrl_gpio_direction_output(chip->base + offset); 796 } 797 798 static const struct gpio_chip intel_gpio_chip = { 799 .owner = THIS_MODULE, 800 .request = gpiochip_generic_request, 801 .free = gpiochip_generic_free, 802 .direction_input = intel_gpio_direction_input, 803 .direction_output = intel_gpio_direction_output, 804 .get = intel_gpio_get, 805 .set = intel_gpio_set, 806 .set_config = gpiochip_generic_config, 807 }; 808 809 /** 810 * intel_gpio_to_pin() - Translate from GPIO offset to pin number 811 * @pctrl: Pinctrl structure 812 * @offset: GPIO offset from gpiolib 813 * @commmunity: Community is filled here if not %NULL 814 * @padgrp: Pad group is filled here if not %NULL 815 * 816 * When coming through gpiolib irqchip, the GPIO offset is not 817 * automatically translated to pinctrl pin number. This function can be 818 * used to find out the corresponding pinctrl pin. 819 */ 820 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset, 821 const struct intel_community **community, 822 const struct intel_padgroup **padgrp) 823 { 824 int i; 825 826 for (i = 0; i < pctrl->ncommunities; i++) { 827 const struct intel_community *comm = &pctrl->communities[i]; 828 int j; 829 830 for (j = 0; j < comm->ngpps; j++) { 831 const struct intel_padgroup *pgrp = &comm->gpps[j]; 832 833 if (pgrp->gpio_base < 0) 834 continue; 835 836 if (offset >= pgrp->gpio_base && 837 offset < pgrp->gpio_base + pgrp->size) { 838 int pin; 839 840 pin = pgrp->base + offset - pgrp->gpio_base; 841 if (community) 842 *community = comm; 843 if (padgrp) 844 *padgrp = pgrp; 845 846 return pin; 847 } 848 } 849 } 850 851 return -EINVAL; 852 } 853 854 static void intel_gpio_irq_ack(struct irq_data *d) 855 { 856 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 857 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 858 const struct intel_community *community; 859 const struct intel_padgroup *padgrp; 860 int pin; 861 862 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 863 if (pin >= 0) { 864 unsigned gpp, gpp_offset, is_offset; 865 866 gpp = padgrp->reg_num; 867 gpp_offset = padgroup_offset(padgrp, pin); 868 is_offset = community->is_offset + gpp * 4; 869 870 raw_spin_lock(&pctrl->lock); 871 writel(BIT(gpp_offset), community->regs + is_offset); 872 raw_spin_unlock(&pctrl->lock); 873 } 874 } 875 876 static void intel_gpio_irq_enable(struct irq_data *d) 877 { 878 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 879 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 880 const struct intel_community *community; 881 const struct intel_padgroup *padgrp; 882 int pin; 883 884 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 885 if (pin >= 0) { 886 unsigned gpp, gpp_offset, is_offset; 887 unsigned long flags; 888 u32 value; 889 890 gpp = padgrp->reg_num; 891 gpp_offset = padgroup_offset(padgrp, pin); 892 is_offset = community->is_offset + gpp * 4; 893 894 raw_spin_lock_irqsave(&pctrl->lock, flags); 895 /* Clear interrupt status first to avoid unexpected interrupt */ 896 writel(BIT(gpp_offset), community->regs + is_offset); 897 898 value = readl(community->regs + community->ie_offset + gpp * 4); 899 value |= BIT(gpp_offset); 900 writel(value, community->regs + community->ie_offset + gpp * 4); 901 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 902 } 903 } 904 905 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 906 { 907 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 908 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 909 const struct intel_community *community; 910 const struct intel_padgroup *padgrp; 911 int pin; 912 913 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 914 if (pin >= 0) { 915 unsigned gpp, gpp_offset; 916 unsigned long flags; 917 void __iomem *reg; 918 u32 value; 919 920 gpp = padgrp->reg_num; 921 gpp_offset = padgroup_offset(padgrp, pin); 922 923 reg = community->regs + community->ie_offset + gpp * 4; 924 925 raw_spin_lock_irqsave(&pctrl->lock, flags); 926 value = readl(reg); 927 if (mask) 928 value &= ~BIT(gpp_offset); 929 else 930 value |= BIT(gpp_offset); 931 writel(value, reg); 932 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 933 } 934 } 935 936 static void intel_gpio_irq_mask(struct irq_data *d) 937 { 938 intel_gpio_irq_mask_unmask(d, true); 939 } 940 941 static void intel_gpio_irq_unmask(struct irq_data *d) 942 { 943 intel_gpio_irq_mask_unmask(d, false); 944 } 945 946 static int intel_gpio_irq_type(struct irq_data *d, unsigned type) 947 { 948 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 949 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 950 unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 951 unsigned long flags; 952 void __iomem *reg; 953 u32 value; 954 955 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 956 if (!reg) 957 return -EINVAL; 958 959 /* 960 * If the pin is in ACPI mode it is still usable as a GPIO but it 961 * cannot be used as IRQ because GPI_IS status bit will not be 962 * updated by the host controller hardware. 963 */ 964 if (intel_pad_acpi_mode(pctrl, pin)) { 965 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 966 return -EPERM; 967 } 968 969 raw_spin_lock_irqsave(&pctrl->lock, flags); 970 971 value = readl(reg); 972 973 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 974 975 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 976 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 977 } else if (type & IRQ_TYPE_EDGE_FALLING) { 978 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 979 value |= PADCFG0_RXINV; 980 } else if (type & IRQ_TYPE_EDGE_RISING) { 981 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 982 } else if (type & IRQ_TYPE_LEVEL_MASK) { 983 if (type & IRQ_TYPE_LEVEL_LOW) 984 value |= PADCFG0_RXINV; 985 } else { 986 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 987 } 988 989 writel(value, reg); 990 991 if (type & IRQ_TYPE_EDGE_BOTH) 992 irq_set_handler_locked(d, handle_edge_irq); 993 else if (type & IRQ_TYPE_LEVEL_MASK) 994 irq_set_handler_locked(d, handle_level_irq); 995 996 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 997 998 return 0; 999 } 1000 1001 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 1002 { 1003 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1004 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1005 unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1006 1007 if (on) 1008 enable_irq_wake(pctrl->irq); 1009 else 1010 disable_irq_wake(pctrl->irq); 1011 1012 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); 1013 return 0; 1014 } 1015 1016 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 1017 const struct intel_community *community) 1018 { 1019 struct gpio_chip *gc = &pctrl->chip; 1020 irqreturn_t ret = IRQ_NONE; 1021 int gpp; 1022 1023 for (gpp = 0; gpp < community->ngpps; gpp++) { 1024 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1025 unsigned long pending, enabled, gpp_offset; 1026 1027 pending = readl(community->regs + community->is_offset + 1028 padgrp->reg_num * 4); 1029 enabled = readl(community->regs + community->ie_offset + 1030 padgrp->reg_num * 4); 1031 1032 /* Only interrupts that are enabled */ 1033 pending &= enabled; 1034 1035 for_each_set_bit(gpp_offset, &pending, padgrp->size) { 1036 unsigned irq; 1037 1038 irq = irq_find_mapping(gc->irq.domain, 1039 padgrp->gpio_base + gpp_offset); 1040 generic_handle_irq(irq); 1041 1042 ret |= IRQ_HANDLED; 1043 } 1044 } 1045 1046 return ret; 1047 } 1048 1049 static irqreturn_t intel_gpio_irq(int irq, void *data) 1050 { 1051 const struct intel_community *community; 1052 struct intel_pinctrl *pctrl = data; 1053 irqreturn_t ret = IRQ_NONE; 1054 int i; 1055 1056 /* Need to check all communities for pending interrupts */ 1057 for (i = 0; i < pctrl->ncommunities; i++) { 1058 community = &pctrl->communities[i]; 1059 ret |= intel_gpio_community_irq_handler(pctrl, community); 1060 } 1061 1062 return ret; 1063 } 1064 1065 static struct irq_chip intel_gpio_irqchip = { 1066 .name = "intel-gpio", 1067 .irq_enable = intel_gpio_irq_enable, 1068 .irq_ack = intel_gpio_irq_ack, 1069 .irq_mask = intel_gpio_irq_mask, 1070 .irq_unmask = intel_gpio_irq_unmask, 1071 .irq_set_type = intel_gpio_irq_type, 1072 .irq_set_wake = intel_gpio_irq_wake, 1073 .flags = IRQCHIP_MASK_ON_SUSPEND, 1074 }; 1075 1076 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl, 1077 const struct intel_community *community) 1078 { 1079 int ret, i; 1080 1081 for (i = 0; i < community->ngpps; i++) { 1082 const struct intel_padgroup *gpp = &community->gpps[i]; 1083 1084 if (gpp->gpio_base < 0) 1085 continue; 1086 1087 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1088 gpp->gpio_base, gpp->base, 1089 gpp->size); 1090 if (ret) 1091 return ret; 1092 } 1093 1094 return ret; 1095 } 1096 1097 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1098 { 1099 const struct intel_community *community; 1100 unsigned ngpio = 0; 1101 int i, j; 1102 1103 for (i = 0; i < pctrl->ncommunities; i++) { 1104 community = &pctrl->communities[i]; 1105 for (j = 0; j < community->ngpps; j++) { 1106 const struct intel_padgroup *gpp = &community->gpps[j]; 1107 1108 if (gpp->gpio_base < 0) 1109 continue; 1110 1111 if (gpp->gpio_base + gpp->size > ngpio) 1112 ngpio = gpp->gpio_base + gpp->size; 1113 } 1114 } 1115 1116 return ngpio; 1117 } 1118 1119 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1120 { 1121 int ret, i; 1122 1123 pctrl->chip = intel_gpio_chip; 1124 1125 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); 1126 pctrl->chip.label = dev_name(pctrl->dev); 1127 pctrl->chip.parent = pctrl->dev; 1128 pctrl->chip.base = -1; 1129 pctrl->irq = irq; 1130 1131 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1132 if (ret) { 1133 dev_err(pctrl->dev, "failed to register gpiochip\n"); 1134 return ret; 1135 } 1136 1137 for (i = 0; i < pctrl->ncommunities; i++) { 1138 struct intel_community *community = &pctrl->communities[i]; 1139 1140 ret = intel_gpio_add_pin_ranges(pctrl, community); 1141 if (ret) { 1142 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1143 return ret; 1144 } 1145 } 1146 1147 /* 1148 * We need to request the interrupt here (instead of providing chip 1149 * to the irq directly) because on some platforms several GPIO 1150 * controllers share the same interrupt line. 1151 */ 1152 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1153 IRQF_SHARED | IRQF_NO_THREAD, 1154 dev_name(pctrl->dev), pctrl); 1155 if (ret) { 1156 dev_err(pctrl->dev, "failed to request interrupt\n"); 1157 return ret; 1158 } 1159 1160 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, 1161 handle_bad_irq, IRQ_TYPE_NONE); 1162 if (ret) { 1163 dev_err(pctrl->dev, "failed to add irqchip\n"); 1164 return ret; 1165 } 1166 1167 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, 1168 NULL); 1169 return 0; 1170 } 1171 1172 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, 1173 struct intel_community *community) 1174 { 1175 struct intel_padgroup *gpps; 1176 unsigned npins = community->npins; 1177 unsigned padown_num = 0; 1178 size_t ngpps, i; 1179 1180 if (community->gpps) 1181 ngpps = community->ngpps; 1182 else 1183 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size); 1184 1185 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1186 if (!gpps) 1187 return -ENOMEM; 1188 1189 for (i = 0; i < ngpps; i++) { 1190 if (community->gpps) { 1191 gpps[i] = community->gpps[i]; 1192 } else { 1193 unsigned gpp_size = community->gpp_size; 1194 1195 gpps[i].reg_num = i; 1196 gpps[i].base = community->pin_base + i * gpp_size; 1197 gpps[i].size = min(gpp_size, npins); 1198 npins -= gpps[i].size; 1199 } 1200 1201 if (gpps[i].size > 32) 1202 return -EINVAL; 1203 1204 if (!gpps[i].gpio_base) 1205 gpps[i].gpio_base = gpps[i].base; 1206 1207 gpps[i].padown_num = padown_num; 1208 1209 /* 1210 * In older hardware the number of padown registers per 1211 * group is fixed regardless of the group size. 1212 */ 1213 if (community->gpp_num_padown_regs) 1214 padown_num += community->gpp_num_padown_regs; 1215 else 1216 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); 1217 } 1218 1219 community->ngpps = ngpps; 1220 community->gpps = gpps; 1221 1222 return 0; 1223 } 1224 1225 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 1226 { 1227 #ifdef CONFIG_PM_SLEEP 1228 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 1229 struct intel_community_context *communities; 1230 struct intel_pad_context *pads; 1231 int i; 1232 1233 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 1234 if (!pads) 1235 return -ENOMEM; 1236 1237 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 1238 sizeof(*communities), GFP_KERNEL); 1239 if (!communities) 1240 return -ENOMEM; 1241 1242 1243 for (i = 0; i < pctrl->ncommunities; i++) { 1244 struct intel_community *community = &pctrl->communities[i]; 1245 u32 *intmask; 1246 1247 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1248 sizeof(*intmask), GFP_KERNEL); 1249 if (!intmask) 1250 return -ENOMEM; 1251 1252 communities[i].intmask = intmask; 1253 } 1254 1255 pctrl->context.pads = pads; 1256 pctrl->context.communities = communities; 1257 #endif 1258 1259 return 0; 1260 } 1261 1262 int intel_pinctrl_probe(struct platform_device *pdev, 1263 const struct intel_pinctrl_soc_data *soc_data) 1264 { 1265 struct intel_pinctrl *pctrl; 1266 int i, ret, irq; 1267 1268 if (!soc_data) 1269 return -EINVAL; 1270 1271 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1272 if (!pctrl) 1273 return -ENOMEM; 1274 1275 pctrl->dev = &pdev->dev; 1276 pctrl->soc = soc_data; 1277 raw_spin_lock_init(&pctrl->lock); 1278 1279 /* 1280 * Make a copy of the communities which we can use to hold pointers 1281 * to the registers. 1282 */ 1283 pctrl->ncommunities = pctrl->soc->ncommunities; 1284 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, 1285 sizeof(*pctrl->communities), GFP_KERNEL); 1286 if (!pctrl->communities) 1287 return -ENOMEM; 1288 1289 for (i = 0; i < pctrl->ncommunities; i++) { 1290 struct intel_community *community = &pctrl->communities[i]; 1291 struct resource *res; 1292 void __iomem *regs; 1293 u32 padbar; 1294 1295 *community = pctrl->soc->communities[i]; 1296 1297 res = platform_get_resource(pdev, IORESOURCE_MEM, 1298 community->barno); 1299 regs = devm_ioremap_resource(&pdev->dev, res); 1300 if (IS_ERR(regs)) 1301 return PTR_ERR(regs); 1302 1303 /* 1304 * Determine community features based on the revision if 1305 * not specified already. 1306 */ 1307 if (!community->features) { 1308 u32 rev; 1309 1310 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT; 1311 if (rev >= 0x94) { 1312 community->features |= PINCTRL_FEATURE_DEBOUNCE; 1313 community->features |= PINCTRL_FEATURE_1K_PD; 1314 } 1315 } 1316 1317 /* Read offset of the pad configuration registers */ 1318 padbar = readl(regs + PADBAR); 1319 1320 community->regs = regs; 1321 community->pad_regs = regs + padbar; 1322 1323 if (!community->is_offset) 1324 community->is_offset = GPI_IS; 1325 1326 ret = intel_pinctrl_add_padgroups(pctrl, community); 1327 if (ret) 1328 return ret; 1329 } 1330 1331 irq = platform_get_irq(pdev, 0); 1332 if (irq < 0) { 1333 dev_err(&pdev->dev, "failed to get interrupt number\n"); 1334 return irq; 1335 } 1336 1337 ret = intel_pinctrl_pm_init(pctrl); 1338 if (ret) 1339 return ret; 1340 1341 pctrl->pctldesc = intel_pinctrl_desc; 1342 pctrl->pctldesc.name = dev_name(&pdev->dev); 1343 pctrl->pctldesc.pins = pctrl->soc->pins; 1344 pctrl->pctldesc.npins = pctrl->soc->npins; 1345 1346 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1347 pctrl); 1348 if (IS_ERR(pctrl->pctldev)) { 1349 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1350 return PTR_ERR(pctrl->pctldev); 1351 } 1352 1353 ret = intel_gpio_probe(pctrl, irq); 1354 if (ret) 1355 return ret; 1356 1357 platform_set_drvdata(pdev, pctrl); 1358 1359 return 0; 1360 } 1361 EXPORT_SYMBOL_GPL(intel_pinctrl_probe); 1362 1363 #ifdef CONFIG_PM_SLEEP 1364 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin) 1365 { 1366 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1367 1368 if (!pd || !intel_pad_usable(pctrl, pin)) 1369 return false; 1370 1371 /* 1372 * Only restore the pin if it is actually in use by the kernel (or 1373 * by userspace). It is possible that some pins are used by the 1374 * BIOS during resume and those are not always locked down so leave 1375 * them alone. 1376 */ 1377 if (pd->mux_owner || pd->gpio_owner || 1378 gpiochip_line_is_irq(&pctrl->chip, pin)) 1379 return true; 1380 1381 return false; 1382 } 1383 1384 int intel_pinctrl_suspend(struct device *dev) 1385 { 1386 struct platform_device *pdev = to_platform_device(dev); 1387 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1388 struct intel_community_context *communities; 1389 struct intel_pad_context *pads; 1390 int i; 1391 1392 pads = pctrl->context.pads; 1393 for (i = 0; i < pctrl->soc->npins; i++) { 1394 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1395 void __iomem *padcfg; 1396 u32 val; 1397 1398 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1399 continue; 1400 1401 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1402 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1403 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1404 pads[i].padcfg1 = val; 1405 1406 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1407 if (padcfg) 1408 pads[i].padcfg2 = readl(padcfg); 1409 } 1410 1411 communities = pctrl->context.communities; 1412 for (i = 0; i < pctrl->ncommunities; i++) { 1413 struct intel_community *community = &pctrl->communities[i]; 1414 void __iomem *base; 1415 unsigned gpp; 1416 1417 base = community->regs + community->ie_offset; 1418 for (gpp = 0; gpp < community->ngpps; gpp++) 1419 communities[i].intmask[gpp] = readl(base + gpp * 4); 1420 } 1421 1422 return 0; 1423 } 1424 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); 1425 1426 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1427 { 1428 size_t i; 1429 1430 for (i = 0; i < pctrl->ncommunities; i++) { 1431 const struct intel_community *community; 1432 void __iomem *base; 1433 unsigned gpp; 1434 1435 community = &pctrl->communities[i]; 1436 base = community->regs; 1437 1438 for (gpp = 0; gpp < community->ngpps; gpp++) { 1439 /* Mask and clear all interrupts */ 1440 writel(0, base + community->ie_offset + gpp * 4); 1441 writel(0xffff, base + community->is_offset + gpp * 4); 1442 } 1443 } 1444 } 1445 1446 int intel_pinctrl_resume(struct device *dev) 1447 { 1448 struct platform_device *pdev = to_platform_device(dev); 1449 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1450 const struct intel_community_context *communities; 1451 const struct intel_pad_context *pads; 1452 int i; 1453 1454 /* Mask all interrupts */ 1455 intel_gpio_irq_init(pctrl); 1456 1457 pads = pctrl->context.pads; 1458 for (i = 0; i < pctrl->soc->npins; i++) { 1459 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1460 void __iomem *padcfg; 1461 u32 val; 1462 1463 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1464 continue; 1465 1466 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); 1467 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; 1468 if (val != pads[i].padcfg0) { 1469 writel(pads[i].padcfg0, padcfg); 1470 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", 1471 desc->number, readl(padcfg)); 1472 } 1473 1474 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); 1475 val = readl(padcfg); 1476 if (val != pads[i].padcfg1) { 1477 writel(pads[i].padcfg1, padcfg); 1478 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", 1479 desc->number, readl(padcfg)); 1480 } 1481 1482 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1483 if (padcfg) { 1484 val = readl(padcfg); 1485 if (val != pads[i].padcfg2) { 1486 writel(pads[i].padcfg2, padcfg); 1487 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n", 1488 desc->number, readl(padcfg)); 1489 } 1490 } 1491 } 1492 1493 communities = pctrl->context.communities; 1494 for (i = 0; i < pctrl->ncommunities; i++) { 1495 struct intel_community *community = &pctrl->communities[i]; 1496 void __iomem *base; 1497 unsigned gpp; 1498 1499 base = community->regs + community->ie_offset; 1500 for (gpp = 0; gpp < community->ngpps; gpp++) { 1501 writel(communities[i].intmask[gpp], base + gpp * 4); 1502 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, 1503 readl(base + gpp * 4)); 1504 } 1505 } 1506 1507 return 0; 1508 } 1509 EXPORT_SYMBOL_GPL(intel_pinctrl_resume); 1510 #endif 1511 1512 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1513 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1514 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1515 MODULE_LICENSE("GPL v2"); 1516