1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel pinctrl/GPIO core driver. 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/log2.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/time.h> 18 19 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinconf-generic.h> 23 24 #include "../core.h" 25 #include "pinctrl-intel.h" 26 27 /* Offset from regs */ 28 #define REVID 0x000 29 #define REVID_SHIFT 16 30 #define REVID_MASK GENMASK(31, 16) 31 32 #define CAPLIST 0x004 33 #define CAPLIST_ID_SHIFT 16 34 #define CAPLIST_ID_MASK GENMASK(23, 16) 35 #define CAPLIST_ID_GPIO_HW_INFO 1 36 #define CAPLIST_ID_PWM 2 37 #define CAPLIST_ID_BLINK 3 38 #define CAPLIST_ID_EXP 4 39 #define CAPLIST_NEXT_SHIFT 0 40 #define CAPLIST_NEXT_MASK GENMASK(15, 0) 41 42 #define PADBAR 0x00c 43 44 #define PADOWN_BITS 4 45 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 46 #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) 47 #define PADOWN_GPP(p) ((p) / 8) 48 49 /* Offset from pad_regs */ 50 #define PADCFG0 0x000 51 #define PADCFG0_RXEVCFG_SHIFT 25 52 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25) 53 #define PADCFG0_RXEVCFG_LEVEL 0 54 #define PADCFG0_RXEVCFG_EDGE 1 55 #define PADCFG0_RXEVCFG_DISABLED 2 56 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 57 #define PADCFG0_PREGFRXSEL BIT(24) 58 #define PADCFG0_RXINV BIT(23) 59 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 60 #define PADCFG0_GPIROUTSCI BIT(19) 61 #define PADCFG0_GPIROUTSMI BIT(18) 62 #define PADCFG0_GPIROUTNMI BIT(17) 63 #define PADCFG0_PMODE_SHIFT 10 64 #define PADCFG0_PMODE_MASK GENMASK(13, 10) 65 #define PADCFG0_PMODE_GPIO 0 66 #define PADCFG0_GPIORXDIS BIT(9) 67 #define PADCFG0_GPIOTXDIS BIT(8) 68 #define PADCFG0_GPIORXSTATE BIT(1) 69 #define PADCFG0_GPIOTXSTATE BIT(0) 70 71 #define PADCFG1 0x004 72 #define PADCFG1_TERM_UP BIT(13) 73 #define PADCFG1_TERM_SHIFT 10 74 #define PADCFG1_TERM_MASK GENMASK(12, 10) 75 #define PADCFG1_TERM_20K BIT(2) 76 #define PADCFG1_TERM_5K BIT(1) 77 #define PADCFG1_TERM_1K BIT(0) 78 #define PADCFG1_TERM_833 (BIT(1) | BIT(0)) 79 80 #define PADCFG2 0x008 81 #define PADCFG2_DEBEN BIT(0) 82 #define PADCFG2_DEBOUNCE_SHIFT 1 83 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) 84 85 #define DEBOUNCE_PERIOD_NSEC 31250 86 87 struct intel_pad_context { 88 u32 padcfg0; 89 u32 padcfg1; 90 u32 padcfg2; 91 }; 92 93 struct intel_community_context { 94 u32 *intmask; 95 u32 *hostown; 96 }; 97 98 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 99 #define padgroup_offset(g, p) ((p) - (g)->base) 100 101 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 102 unsigned int pin) 103 { 104 struct intel_community *community; 105 int i; 106 107 for (i = 0; i < pctrl->ncommunities; i++) { 108 community = &pctrl->communities[i]; 109 if (pin >= community->pin_base && 110 pin < community->pin_base + community->npins) 111 return community; 112 } 113 114 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 115 return NULL; 116 } 117 118 static const struct intel_padgroup * 119 intel_community_get_padgroup(const struct intel_community *community, 120 unsigned int pin) 121 { 122 int i; 123 124 for (i = 0; i < community->ngpps; i++) { 125 const struct intel_padgroup *padgrp = &community->gpps[i]; 126 127 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) 128 return padgrp; 129 } 130 131 return NULL; 132 } 133 134 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, 135 unsigned int pin, unsigned int reg) 136 { 137 const struct intel_community *community; 138 unsigned int padno; 139 size_t nregs; 140 141 community = intel_get_community(pctrl, pin); 142 if (!community) 143 return NULL; 144 145 padno = pin_to_padno(community, pin); 146 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; 147 148 if (reg >= nregs * 4) 149 return NULL; 150 151 return community->pad_regs + reg + padno * nregs * 4; 152 } 153 154 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin) 155 { 156 const struct intel_community *community; 157 const struct intel_padgroup *padgrp; 158 unsigned int gpp, offset, gpp_offset; 159 void __iomem *padown; 160 161 community = intel_get_community(pctrl, pin); 162 if (!community) 163 return false; 164 if (!community->padown_offset) 165 return true; 166 167 padgrp = intel_community_get_padgroup(community, pin); 168 if (!padgrp) 169 return false; 170 171 gpp_offset = padgroup_offset(padgrp, pin); 172 gpp = PADOWN_GPP(gpp_offset); 173 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; 174 padown = community->regs + offset; 175 176 return !(readl(padown) & PADOWN_MASK(gpp_offset)); 177 } 178 179 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin) 180 { 181 const struct intel_community *community; 182 const struct intel_padgroup *padgrp; 183 unsigned int offset, gpp_offset; 184 void __iomem *hostown; 185 186 community = intel_get_community(pctrl, pin); 187 if (!community) 188 return true; 189 if (!community->hostown_offset) 190 return false; 191 192 padgrp = intel_community_get_padgroup(community, pin); 193 if (!padgrp) 194 return true; 195 196 gpp_offset = padgroup_offset(padgrp, pin); 197 offset = community->hostown_offset + padgrp->reg_num * 4; 198 hostown = community->regs + offset; 199 200 return !(readl(hostown) & BIT(gpp_offset)); 201 } 202 203 /** 204 * enum - Locking variants of the pad configuration 205 * 206 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers 207 * @PAD_LOCKED: pad configuration registers, except TX state, are locked 208 * @PAD_LOCKED_TX: pad configuration TX state is locked 209 * @PAD_LOCKED_FULL: pad configuration registers are locked completely 210 * 211 * Locking is considered as read-only mode for corresponding registers and 212 * their respective fields. That said, TX state bit is locked separately from 213 * the main locking scheme. 214 */ 215 enum { 216 PAD_UNLOCKED = 0, 217 PAD_LOCKED = 1, 218 PAD_LOCKED_TX = 2, 219 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX, 220 }; 221 222 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin) 223 { 224 struct intel_community *community; 225 const struct intel_padgroup *padgrp; 226 unsigned int offset, gpp_offset; 227 u32 value; 228 int ret = PAD_UNLOCKED; 229 230 community = intel_get_community(pctrl, pin); 231 if (!community) 232 return PAD_LOCKED_FULL; 233 if (!community->padcfglock_offset) 234 return PAD_UNLOCKED; 235 236 padgrp = intel_community_get_padgroup(community, pin); 237 if (!padgrp) 238 return PAD_LOCKED_FULL; 239 240 gpp_offset = padgroup_offset(padgrp, pin); 241 242 /* 243 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 244 * the pad is considered unlocked. Any other case means that it is 245 * either fully or partially locked. 246 */ 247 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; 248 value = readl(community->regs + offset); 249 if (value & BIT(gpp_offset)) 250 ret |= PAD_LOCKED; 251 252 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; 253 value = readl(community->regs + offset); 254 if (value & BIT(gpp_offset)) 255 ret |= PAD_LOCKED_TX; 256 257 return ret; 258 } 259 260 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin) 261 { 262 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED; 263 } 264 265 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) 266 { 267 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); 268 } 269 270 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 271 { 272 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 273 274 return pctrl->soc->ngroups; 275 } 276 277 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 278 unsigned int group) 279 { 280 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 281 282 return pctrl->soc->groups[group].grp.name; 283 } 284 285 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 286 const unsigned int **pins, unsigned int *npins) 287 { 288 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 289 290 *pins = pctrl->soc->groups[group].grp.pins; 291 *npins = pctrl->soc->groups[group].grp.npins; 292 return 0; 293 } 294 295 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 296 unsigned int pin) 297 { 298 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 299 void __iomem *padcfg; 300 u32 cfg0, cfg1, mode; 301 int locked; 302 bool acpi; 303 304 if (!intel_pad_owned_by_host(pctrl, pin)) { 305 seq_puts(s, "not available"); 306 return; 307 } 308 309 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 310 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 311 312 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 313 if (mode == PADCFG0_PMODE_GPIO) 314 seq_puts(s, "GPIO "); 315 else 316 seq_printf(s, "mode %d ", mode); 317 318 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 319 320 /* Dump the additional PADCFG registers if available */ 321 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); 322 if (padcfg) 323 seq_printf(s, " 0x%08x", readl(padcfg)); 324 325 locked = intel_pad_locked(pctrl, pin); 326 acpi = intel_pad_acpi_mode(pctrl, pin); 327 328 if (locked || acpi) { 329 seq_puts(s, " ["); 330 if (locked) 331 seq_puts(s, "LOCKED"); 332 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) 333 seq_puts(s, " tx"); 334 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) 335 seq_puts(s, " full"); 336 337 if (locked && acpi) 338 seq_puts(s, ", "); 339 340 if (acpi) 341 seq_puts(s, "ACPI"); 342 seq_puts(s, "]"); 343 } 344 } 345 346 static const struct pinctrl_ops intel_pinctrl_ops = { 347 .get_groups_count = intel_get_groups_count, 348 .get_group_name = intel_get_group_name, 349 .get_group_pins = intel_get_group_pins, 350 .pin_dbg_show = intel_pin_dbg_show, 351 }; 352 353 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 354 { 355 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 356 357 return pctrl->soc->nfunctions; 358 } 359 360 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 361 unsigned int function) 362 { 363 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 364 365 return pctrl->soc->functions[function].name; 366 } 367 368 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 369 unsigned int function, 370 const char * const **groups, 371 unsigned int * const ngroups) 372 { 373 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 374 375 *groups = pctrl->soc->functions[function].groups; 376 *ngroups = pctrl->soc->functions[function].ngroups; 377 return 0; 378 } 379 380 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, 381 unsigned int function, unsigned int group) 382 { 383 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 384 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 385 unsigned long flags; 386 int i; 387 388 raw_spin_lock_irqsave(&pctrl->lock, flags); 389 390 /* 391 * All pins in the groups needs to be accessible and writable 392 * before we can enable the mux for this group. 393 */ 394 for (i = 0; i < grp->grp.npins; i++) { 395 if (!intel_pad_usable(pctrl, grp->grp.pins[i])) { 396 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 397 return -EBUSY; 398 } 399 } 400 401 /* Now enable the mux setting for each pin in the group */ 402 for (i = 0; i < grp->grp.npins; i++) { 403 void __iomem *padcfg0; 404 u32 value; 405 406 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0); 407 value = readl(padcfg0); 408 409 value &= ~PADCFG0_PMODE_MASK; 410 411 if (grp->modes) 412 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; 413 else 414 value |= grp->mode << PADCFG0_PMODE_SHIFT; 415 416 writel(value, padcfg0); 417 } 418 419 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 420 421 return 0; 422 } 423 424 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) 425 { 426 u32 value; 427 428 value = readl(padcfg0); 429 if (input) { 430 value &= ~PADCFG0_GPIORXDIS; 431 value |= PADCFG0_GPIOTXDIS; 432 } else { 433 value &= ~PADCFG0_GPIOTXDIS; 434 value |= PADCFG0_GPIORXDIS; 435 } 436 writel(value, padcfg0); 437 } 438 439 static int __intel_gpio_get_gpio_mode(u32 value) 440 { 441 return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 442 } 443 444 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) 445 { 446 return __intel_gpio_get_gpio_mode(readl(padcfg0)); 447 } 448 449 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) 450 { 451 u32 value; 452 453 value = readl(padcfg0); 454 455 /* Put the pad into GPIO mode */ 456 value &= ~PADCFG0_PMODE_MASK; 457 value |= PADCFG0_PMODE_GPIO; 458 459 /* Disable TX buffer and enable RX (this will be input) */ 460 value &= ~PADCFG0_GPIORXDIS; 461 value |= PADCFG0_GPIOTXDIS; 462 463 /* Disable SCI/SMI/NMI generation */ 464 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 465 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 466 467 writel(value, padcfg0); 468 } 469 470 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 471 struct pinctrl_gpio_range *range, 472 unsigned int pin) 473 { 474 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 475 void __iomem *padcfg0; 476 unsigned long flags; 477 478 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 479 480 raw_spin_lock_irqsave(&pctrl->lock, flags); 481 482 if (!intel_pad_owned_by_host(pctrl, pin)) { 483 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 484 return -EBUSY; 485 } 486 487 if (!intel_pad_is_unlocked(pctrl, pin)) { 488 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 489 return 0; 490 } 491 492 /* 493 * If pin is already configured in GPIO mode, we assume that 494 * firmware provides correct settings. In such case we avoid 495 * potential glitches on the pin. Otherwise, for the pin in 496 * alternative mode, consumer has to supply respective flags. 497 */ 498 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) { 499 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 500 return 0; 501 } 502 503 intel_gpio_set_gpio_mode(padcfg0); 504 505 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 506 507 return 0; 508 } 509 510 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 511 struct pinctrl_gpio_range *range, 512 unsigned int pin, bool input) 513 { 514 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 515 void __iomem *padcfg0; 516 unsigned long flags; 517 518 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 519 520 raw_spin_lock_irqsave(&pctrl->lock, flags); 521 __intel_gpio_set_direction(padcfg0, input); 522 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 523 524 return 0; 525 } 526 527 static const struct pinmux_ops intel_pinmux_ops = { 528 .get_functions_count = intel_get_functions_count, 529 .get_function_name = intel_get_function_name, 530 .get_function_groups = intel_get_function_groups, 531 .set_mux = intel_pinmux_set_mux, 532 .gpio_request_enable = intel_gpio_request_enable, 533 .gpio_set_direction = intel_gpio_set_direction, 534 }; 535 536 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin, 537 enum pin_config_param param, u32 *arg) 538 { 539 const struct intel_community *community; 540 void __iomem *padcfg1; 541 unsigned long flags; 542 u32 value, term; 543 544 community = intel_get_community(pctrl, pin); 545 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 546 547 raw_spin_lock_irqsave(&pctrl->lock, flags); 548 value = readl(padcfg1); 549 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 550 551 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 552 553 switch (param) { 554 case PIN_CONFIG_BIAS_DISABLE: 555 if (term) 556 return -EINVAL; 557 break; 558 559 case PIN_CONFIG_BIAS_PULL_UP: 560 if (!term || !(value & PADCFG1_TERM_UP)) 561 return -EINVAL; 562 563 switch (term) { 564 case PADCFG1_TERM_833: 565 *arg = 833; 566 break; 567 case PADCFG1_TERM_1K: 568 *arg = 1000; 569 break; 570 case PADCFG1_TERM_5K: 571 *arg = 5000; 572 break; 573 case PADCFG1_TERM_20K: 574 *arg = 20000; 575 break; 576 } 577 578 break; 579 580 case PIN_CONFIG_BIAS_PULL_DOWN: 581 if (!term || value & PADCFG1_TERM_UP) 582 return -EINVAL; 583 584 switch (term) { 585 case PADCFG1_TERM_833: 586 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 587 return -EINVAL; 588 *arg = 833; 589 break; 590 case PADCFG1_TERM_1K: 591 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 592 return -EINVAL; 593 *arg = 1000; 594 break; 595 case PADCFG1_TERM_5K: 596 *arg = 5000; 597 break; 598 case PADCFG1_TERM_20K: 599 *arg = 20000; 600 break; 601 } 602 603 break; 604 605 default: 606 return -EINVAL; 607 } 608 609 return 0; 610 } 611 612 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin, 613 enum pin_config_param param, u32 *arg) 614 { 615 void __iomem *padcfg2; 616 unsigned long flags; 617 unsigned long v; 618 u32 value2; 619 620 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 621 if (!padcfg2) 622 return -ENOTSUPP; 623 624 raw_spin_lock_irqsave(&pctrl->lock, flags); 625 value2 = readl(padcfg2); 626 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 627 if (!(value2 & PADCFG2_DEBEN)) 628 return -EINVAL; 629 630 v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; 631 *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC; 632 633 return 0; 634 } 635 636 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 637 unsigned long *config) 638 { 639 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 640 enum pin_config_param param = pinconf_to_config_param(*config); 641 u32 arg = 0; 642 int ret; 643 644 if (!intel_pad_owned_by_host(pctrl, pin)) 645 return -ENOTSUPP; 646 647 switch (param) { 648 case PIN_CONFIG_BIAS_DISABLE: 649 case PIN_CONFIG_BIAS_PULL_UP: 650 case PIN_CONFIG_BIAS_PULL_DOWN: 651 ret = intel_config_get_pull(pctrl, pin, param, &arg); 652 if (ret) 653 return ret; 654 break; 655 656 case PIN_CONFIG_INPUT_DEBOUNCE: 657 ret = intel_config_get_debounce(pctrl, pin, param, &arg); 658 if (ret) 659 return ret; 660 break; 661 662 default: 663 return -ENOTSUPP; 664 } 665 666 *config = pinconf_to_config_packed(param, arg); 667 return 0; 668 } 669 670 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 671 unsigned long config) 672 { 673 unsigned int param = pinconf_to_config_param(config); 674 unsigned int arg = pinconf_to_config_argument(config); 675 const struct intel_community *community; 676 void __iomem *padcfg1; 677 unsigned long flags; 678 int ret = 0; 679 u32 value; 680 681 community = intel_get_community(pctrl, pin); 682 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 683 684 raw_spin_lock_irqsave(&pctrl->lock, flags); 685 686 value = readl(padcfg1); 687 688 switch (param) { 689 case PIN_CONFIG_BIAS_DISABLE: 690 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 691 break; 692 693 case PIN_CONFIG_BIAS_PULL_UP: 694 value &= ~PADCFG1_TERM_MASK; 695 696 value |= PADCFG1_TERM_UP; 697 698 /* Set default strength value in case none is given */ 699 if (arg == 1) 700 arg = 5000; 701 702 switch (arg) { 703 case 20000: 704 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 705 break; 706 case 5000: 707 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 708 break; 709 case 1000: 710 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 711 break; 712 case 833: 713 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; 714 break; 715 default: 716 ret = -EINVAL; 717 } 718 719 break; 720 721 case PIN_CONFIG_BIAS_PULL_DOWN: 722 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); 723 724 /* Set default strength value in case none is given */ 725 if (arg == 1) 726 arg = 5000; 727 728 switch (arg) { 729 case 20000: 730 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 731 break; 732 case 5000: 733 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 734 break; 735 case 1000: 736 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 737 ret = -EINVAL; 738 break; 739 } 740 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 741 break; 742 case 833: 743 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 744 ret = -EINVAL; 745 break; 746 } 747 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; 748 break; 749 default: 750 ret = -EINVAL; 751 } 752 753 break; 754 } 755 756 if (!ret) 757 writel(value, padcfg1); 758 759 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 760 761 return ret; 762 } 763 764 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, 765 unsigned int pin, unsigned int debounce) 766 { 767 void __iomem *padcfg0, *padcfg2; 768 unsigned long flags; 769 u32 value0, value2; 770 771 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 772 if (!padcfg2) 773 return -ENOTSUPP; 774 775 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 776 777 raw_spin_lock_irqsave(&pctrl->lock, flags); 778 779 value0 = readl(padcfg0); 780 value2 = readl(padcfg2); 781 782 /* Disable glitch filter and debouncer */ 783 value0 &= ~PADCFG0_PREGFRXSEL; 784 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); 785 786 if (debounce) { 787 unsigned long v; 788 789 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC); 790 if (v < 3 || v > 15) { 791 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 792 return -EINVAL; 793 } 794 795 /* Enable glitch filter and debouncer */ 796 value0 |= PADCFG0_PREGFRXSEL; 797 value2 |= v << PADCFG2_DEBOUNCE_SHIFT; 798 value2 |= PADCFG2_DEBEN; 799 } 800 801 writel(value0, padcfg0); 802 writel(value2, padcfg2); 803 804 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 805 806 return 0; 807 } 808 809 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 810 unsigned long *configs, unsigned int nconfigs) 811 { 812 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 813 int i, ret; 814 815 if (!intel_pad_usable(pctrl, pin)) 816 return -ENOTSUPP; 817 818 for (i = 0; i < nconfigs; i++) { 819 switch (pinconf_to_config_param(configs[i])) { 820 case PIN_CONFIG_BIAS_DISABLE: 821 case PIN_CONFIG_BIAS_PULL_UP: 822 case PIN_CONFIG_BIAS_PULL_DOWN: 823 ret = intel_config_set_pull(pctrl, pin, configs[i]); 824 if (ret) 825 return ret; 826 break; 827 828 case PIN_CONFIG_INPUT_DEBOUNCE: 829 ret = intel_config_set_debounce(pctrl, pin, 830 pinconf_to_config_argument(configs[i])); 831 if (ret) 832 return ret; 833 break; 834 835 default: 836 return -ENOTSUPP; 837 } 838 } 839 840 return 0; 841 } 842 843 static const struct pinconf_ops intel_pinconf_ops = { 844 .is_generic = true, 845 .pin_config_get = intel_config_get, 846 .pin_config_set = intel_config_set, 847 }; 848 849 static const struct pinctrl_desc intel_pinctrl_desc = { 850 .pctlops = &intel_pinctrl_ops, 851 .pmxops = &intel_pinmux_ops, 852 .confops = &intel_pinconf_ops, 853 .owner = THIS_MODULE, 854 }; 855 856 /** 857 * intel_gpio_to_pin() - Translate from GPIO offset to pin number 858 * @pctrl: Pinctrl structure 859 * @offset: GPIO offset from gpiolib 860 * @community: Community is filled here if not %NULL 861 * @padgrp: Pad group is filled here if not %NULL 862 * 863 * When coming through gpiolib irqchip, the GPIO offset is not 864 * automatically translated to pinctrl pin number. This function can be 865 * used to find out the corresponding pinctrl pin. 866 * 867 * Return: a pin number and pointers to the community and pad group, which 868 * the pin belongs to, or negative error code if translation can't be done. 869 */ 870 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, 871 const struct intel_community **community, 872 const struct intel_padgroup **padgrp) 873 { 874 int i; 875 876 for (i = 0; i < pctrl->ncommunities; i++) { 877 const struct intel_community *comm = &pctrl->communities[i]; 878 int j; 879 880 for (j = 0; j < comm->ngpps; j++) { 881 const struct intel_padgroup *pgrp = &comm->gpps[j]; 882 883 if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 884 continue; 885 886 if (offset >= pgrp->gpio_base && 887 offset < pgrp->gpio_base + pgrp->size) { 888 int pin; 889 890 pin = pgrp->base + offset - pgrp->gpio_base; 891 if (community) 892 *community = comm; 893 if (padgrp) 894 *padgrp = pgrp; 895 896 return pin; 897 } 898 } 899 } 900 901 return -EINVAL; 902 } 903 904 /** 905 * intel_pin_to_gpio() - Translate from pin number to GPIO offset 906 * @pctrl: Pinctrl structure 907 * @pin: pin number 908 * 909 * Translate the pin number of pinctrl to GPIO offset 910 * 911 * Return: a GPIO offset, or negative error code if translation can't be done. 912 */ 913 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin) 914 { 915 const struct intel_community *community; 916 const struct intel_padgroup *padgrp; 917 918 community = intel_get_community(pctrl, pin); 919 if (!community) 920 return -EINVAL; 921 922 padgrp = intel_community_get_padgroup(community, pin); 923 if (!padgrp) 924 return -EINVAL; 925 926 return pin - padgrp->base + padgrp->gpio_base; 927 } 928 929 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) 930 { 931 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 932 void __iomem *reg; 933 u32 padcfg0; 934 int pin; 935 936 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 937 if (pin < 0) 938 return -EINVAL; 939 940 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 941 if (!reg) 942 return -EINVAL; 943 944 padcfg0 = readl(reg); 945 if (!(padcfg0 & PADCFG0_GPIOTXDIS)) 946 return !!(padcfg0 & PADCFG0_GPIOTXSTATE); 947 948 return !!(padcfg0 & PADCFG0_GPIORXSTATE); 949 } 950 951 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, 952 int value) 953 { 954 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 955 unsigned long flags; 956 void __iomem *reg; 957 u32 padcfg0; 958 int pin; 959 960 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 961 if (pin < 0) 962 return; 963 964 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 965 if (!reg) 966 return; 967 968 raw_spin_lock_irqsave(&pctrl->lock, flags); 969 padcfg0 = readl(reg); 970 if (value) 971 padcfg0 |= PADCFG0_GPIOTXSTATE; 972 else 973 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 974 writel(padcfg0, reg); 975 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 976 } 977 978 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 979 { 980 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 981 unsigned long flags; 982 void __iomem *reg; 983 u32 padcfg0; 984 int pin; 985 986 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 987 if (pin < 0) 988 return -EINVAL; 989 990 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 991 if (!reg) 992 return -EINVAL; 993 994 raw_spin_lock_irqsave(&pctrl->lock, flags); 995 padcfg0 = readl(reg); 996 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 997 if (padcfg0 & PADCFG0_PMODE_MASK) 998 return -EINVAL; 999 1000 if (padcfg0 & PADCFG0_GPIOTXDIS) 1001 return GPIO_LINE_DIRECTION_IN; 1002 1003 return GPIO_LINE_DIRECTION_OUT; 1004 } 1005 1006 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1007 { 1008 return pinctrl_gpio_direction_input(chip->base + offset); 1009 } 1010 1011 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 1012 int value) 1013 { 1014 intel_gpio_set(chip, offset, value); 1015 return pinctrl_gpio_direction_output(chip->base + offset); 1016 } 1017 1018 static const struct gpio_chip intel_gpio_chip = { 1019 .owner = THIS_MODULE, 1020 .request = gpiochip_generic_request, 1021 .free = gpiochip_generic_free, 1022 .get_direction = intel_gpio_get_direction, 1023 .direction_input = intel_gpio_direction_input, 1024 .direction_output = intel_gpio_direction_output, 1025 .get = intel_gpio_get, 1026 .set = intel_gpio_set, 1027 .set_config = gpiochip_generic_config, 1028 }; 1029 1030 static void intel_gpio_irq_ack(struct irq_data *d) 1031 { 1032 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1033 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1034 const struct intel_community *community; 1035 const struct intel_padgroup *padgrp; 1036 int pin; 1037 1038 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 1039 if (pin >= 0) { 1040 unsigned int gpp, gpp_offset, is_offset; 1041 1042 gpp = padgrp->reg_num; 1043 gpp_offset = padgroup_offset(padgrp, pin); 1044 is_offset = community->is_offset + gpp * 4; 1045 1046 raw_spin_lock(&pctrl->lock); 1047 writel(BIT(gpp_offset), community->regs + is_offset); 1048 raw_spin_unlock(&pctrl->lock); 1049 } 1050 } 1051 1052 static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) 1053 { 1054 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1055 const struct intel_community *community; 1056 const struct intel_padgroup *padgrp; 1057 int pin; 1058 1059 pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp); 1060 if (pin >= 0) { 1061 unsigned int gpp, gpp_offset; 1062 unsigned long flags; 1063 void __iomem *reg, *is; 1064 u32 value; 1065 1066 gpp = padgrp->reg_num; 1067 gpp_offset = padgroup_offset(padgrp, pin); 1068 1069 reg = community->regs + community->ie_offset + gpp * 4; 1070 is = community->regs + community->is_offset + gpp * 4; 1071 1072 raw_spin_lock_irqsave(&pctrl->lock, flags); 1073 1074 /* Clear interrupt status first to avoid unexpected interrupt */ 1075 writel(BIT(gpp_offset), is); 1076 1077 value = readl(reg); 1078 if (mask) 1079 value &= ~BIT(gpp_offset); 1080 else 1081 value |= BIT(gpp_offset); 1082 writel(value, reg); 1083 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1084 } 1085 } 1086 1087 static void intel_gpio_irq_mask(struct irq_data *d) 1088 { 1089 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1090 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1091 1092 intel_gpio_irq_mask_unmask(gc, hwirq, true); 1093 gpiochip_disable_irq(gc, hwirq); 1094 } 1095 1096 static void intel_gpio_irq_unmask(struct irq_data *d) 1097 { 1098 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1099 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1100 1101 gpiochip_enable_irq(gc, hwirq); 1102 intel_gpio_irq_mask_unmask(gc, hwirq, false); 1103 } 1104 1105 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) 1106 { 1107 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1108 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1109 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1110 unsigned long flags; 1111 void __iomem *reg; 1112 u32 value; 1113 1114 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1115 if (!reg) 1116 return -EINVAL; 1117 1118 /* 1119 * If the pin is in ACPI mode it is still usable as a GPIO but it 1120 * cannot be used as IRQ because GPI_IS status bit will not be 1121 * updated by the host controller hardware. 1122 */ 1123 if (intel_pad_acpi_mode(pctrl, pin)) { 1124 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 1125 return -EPERM; 1126 } 1127 1128 raw_spin_lock_irqsave(&pctrl->lock, flags); 1129 1130 intel_gpio_set_gpio_mode(reg); 1131 1132 value = readl(reg); 1133 1134 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 1135 1136 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 1137 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 1138 } else if (type & IRQ_TYPE_EDGE_FALLING) { 1139 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1140 value |= PADCFG0_RXINV; 1141 } else if (type & IRQ_TYPE_EDGE_RISING) { 1142 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1143 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1144 if (type & IRQ_TYPE_LEVEL_LOW) 1145 value |= PADCFG0_RXINV; 1146 } else { 1147 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 1148 } 1149 1150 writel(value, reg); 1151 1152 if (type & IRQ_TYPE_EDGE_BOTH) 1153 irq_set_handler_locked(d, handle_edge_irq); 1154 else if (type & IRQ_TYPE_LEVEL_MASK) 1155 irq_set_handler_locked(d, handle_level_irq); 1156 1157 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1158 1159 return 0; 1160 } 1161 1162 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 1163 { 1164 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1165 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1166 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1167 1168 if (on) 1169 enable_irq_wake(pctrl->irq); 1170 else 1171 disable_irq_wake(pctrl->irq); 1172 1173 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); 1174 return 0; 1175 } 1176 1177 static const struct irq_chip intel_gpio_irq_chip = { 1178 .name = "intel-gpio", 1179 .irq_ack = intel_gpio_irq_ack, 1180 .irq_mask = intel_gpio_irq_mask, 1181 .irq_unmask = intel_gpio_irq_unmask, 1182 .irq_set_type = intel_gpio_irq_type, 1183 .irq_set_wake = intel_gpio_irq_wake, 1184 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 1185 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1186 }; 1187 1188 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 1189 const struct intel_community *community) 1190 { 1191 struct gpio_chip *gc = &pctrl->chip; 1192 unsigned int gpp; 1193 int ret = 0; 1194 1195 for (gpp = 0; gpp < community->ngpps; gpp++) { 1196 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1197 unsigned long pending, enabled, gpp_offset; 1198 1199 raw_spin_lock(&pctrl->lock); 1200 1201 pending = readl(community->regs + community->is_offset + 1202 padgrp->reg_num * 4); 1203 enabled = readl(community->regs + community->ie_offset + 1204 padgrp->reg_num * 4); 1205 1206 raw_spin_unlock(&pctrl->lock); 1207 1208 /* Only interrupts that are enabled */ 1209 pending &= enabled; 1210 1211 for_each_set_bit(gpp_offset, &pending, padgrp->size) { 1212 unsigned int irq; 1213 1214 irq = irq_find_mapping(gc->irq.domain, 1215 padgrp->gpio_base + gpp_offset); 1216 generic_handle_irq(irq); 1217 } 1218 1219 ret += pending ? 1 : 0; 1220 } 1221 1222 return ret; 1223 } 1224 1225 static irqreturn_t intel_gpio_irq(int irq, void *data) 1226 { 1227 const struct intel_community *community; 1228 struct intel_pinctrl *pctrl = data; 1229 unsigned int i; 1230 int ret = 0; 1231 1232 /* Need to check all communities for pending interrupts */ 1233 for (i = 0; i < pctrl->ncommunities; i++) { 1234 community = &pctrl->communities[i]; 1235 ret += intel_gpio_community_irq_handler(pctrl, community); 1236 } 1237 1238 return IRQ_RETVAL(ret); 1239 } 1240 1241 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1242 { 1243 int i; 1244 1245 for (i = 0; i < pctrl->ncommunities; i++) { 1246 const struct intel_community *community; 1247 void __iomem *base; 1248 unsigned int gpp; 1249 1250 community = &pctrl->communities[i]; 1251 base = community->regs; 1252 1253 for (gpp = 0; gpp < community->ngpps; gpp++) { 1254 /* Mask and clear all interrupts */ 1255 writel(0, base + community->ie_offset + gpp * 4); 1256 writel(0xffff, base + community->is_offset + gpp * 4); 1257 } 1258 } 1259 } 1260 1261 static int intel_gpio_irq_init_hw(struct gpio_chip *gc) 1262 { 1263 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1264 1265 /* 1266 * Make sure the interrupt lines are in a proper state before 1267 * further configuration. 1268 */ 1269 intel_gpio_irq_init(pctrl); 1270 1271 return 0; 1272 } 1273 1274 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl, 1275 const struct intel_community *community) 1276 { 1277 int ret = 0, i; 1278 1279 for (i = 0; i < community->ngpps; i++) { 1280 const struct intel_padgroup *gpp = &community->gpps[i]; 1281 1282 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1283 continue; 1284 1285 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1286 gpp->gpio_base, gpp->base, 1287 gpp->size); 1288 if (ret) 1289 return ret; 1290 } 1291 1292 return ret; 1293 } 1294 1295 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) 1296 { 1297 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1298 int ret, i; 1299 1300 for (i = 0; i < pctrl->ncommunities; i++) { 1301 struct intel_community *community = &pctrl->communities[i]; 1302 1303 ret = intel_gpio_add_community_ranges(pctrl, community); 1304 if (ret) { 1305 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1306 return ret; 1307 } 1308 } 1309 1310 return 0; 1311 } 1312 1313 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1314 { 1315 const struct intel_community *community; 1316 unsigned int ngpio = 0; 1317 int i, j; 1318 1319 for (i = 0; i < pctrl->ncommunities; i++) { 1320 community = &pctrl->communities[i]; 1321 for (j = 0; j < community->ngpps; j++) { 1322 const struct intel_padgroup *gpp = &community->gpps[j]; 1323 1324 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1325 continue; 1326 1327 if (gpp->gpio_base + gpp->size > ngpio) 1328 ngpio = gpp->gpio_base + gpp->size; 1329 } 1330 } 1331 1332 return ngpio; 1333 } 1334 1335 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1336 { 1337 int ret; 1338 struct gpio_irq_chip *girq; 1339 1340 pctrl->chip = intel_gpio_chip; 1341 1342 /* Setup GPIO chip */ 1343 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); 1344 pctrl->chip.label = dev_name(pctrl->dev); 1345 pctrl->chip.parent = pctrl->dev; 1346 pctrl->chip.base = -1; 1347 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; 1348 pctrl->irq = irq; 1349 1350 /* 1351 * On some platforms several GPIO controllers share the same interrupt 1352 * line. 1353 */ 1354 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1355 IRQF_SHARED | IRQF_NO_THREAD, 1356 dev_name(pctrl->dev), pctrl); 1357 if (ret) { 1358 dev_err(pctrl->dev, "failed to request interrupt\n"); 1359 return ret; 1360 } 1361 1362 /* Setup IRQ chip */ 1363 girq = &pctrl->chip.irq; 1364 gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip); 1365 /* This will let us handle the IRQ in the driver */ 1366 girq->parent_handler = NULL; 1367 girq->num_parents = 0; 1368 girq->default_type = IRQ_TYPE_NONE; 1369 girq->handler = handle_bad_irq; 1370 girq->init_hw = intel_gpio_irq_init_hw; 1371 1372 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1373 if (ret) { 1374 dev_err(pctrl->dev, "failed to register gpiochip\n"); 1375 return ret; 1376 } 1377 1378 return 0; 1379 } 1380 1381 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl, 1382 struct intel_community *community) 1383 { 1384 struct intel_padgroup *gpps; 1385 unsigned int padown_num = 0; 1386 size_t i, ngpps = community->ngpps; 1387 1388 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1389 if (!gpps) 1390 return -ENOMEM; 1391 1392 for (i = 0; i < ngpps; i++) { 1393 gpps[i] = community->gpps[i]; 1394 1395 if (gpps[i].size > 32) 1396 return -EINVAL; 1397 1398 /* Special treatment for GPIO base */ 1399 switch (gpps[i].gpio_base) { 1400 case INTEL_GPIO_BASE_MATCH: 1401 gpps[i].gpio_base = gpps[i].base; 1402 break; 1403 case INTEL_GPIO_BASE_ZERO: 1404 gpps[i].gpio_base = 0; 1405 break; 1406 case INTEL_GPIO_BASE_NOMAP: 1407 break; 1408 default: 1409 break; 1410 } 1411 1412 gpps[i].padown_num = padown_num; 1413 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); 1414 } 1415 1416 community->gpps = gpps; 1417 1418 return 0; 1419 } 1420 1421 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl, 1422 struct intel_community *community) 1423 { 1424 struct intel_padgroup *gpps; 1425 unsigned int npins = community->npins; 1426 unsigned int padown_num = 0; 1427 size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size); 1428 1429 if (community->gpp_size > 32) 1430 return -EINVAL; 1431 1432 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1433 if (!gpps) 1434 return -ENOMEM; 1435 1436 for (i = 0; i < ngpps; i++) { 1437 unsigned int gpp_size = community->gpp_size; 1438 1439 gpps[i].reg_num = i; 1440 gpps[i].base = community->pin_base + i * gpp_size; 1441 gpps[i].size = min(gpp_size, npins); 1442 npins -= gpps[i].size; 1443 1444 gpps[i].gpio_base = gpps[i].base; 1445 gpps[i].padown_num = padown_num; 1446 1447 /* 1448 * In older hardware the number of padown registers per 1449 * group is fixed regardless of the group size. 1450 */ 1451 if (community->gpp_num_padown_regs) 1452 padown_num += community->gpp_num_padown_regs; 1453 else 1454 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); 1455 } 1456 1457 community->ngpps = ngpps; 1458 community->gpps = gpps; 1459 1460 return 0; 1461 } 1462 1463 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 1464 { 1465 #ifdef CONFIG_PM_SLEEP 1466 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 1467 struct intel_community_context *communities; 1468 struct intel_pad_context *pads; 1469 int i; 1470 1471 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 1472 if (!pads) 1473 return -ENOMEM; 1474 1475 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 1476 sizeof(*communities), GFP_KERNEL); 1477 if (!communities) 1478 return -ENOMEM; 1479 1480 1481 for (i = 0; i < pctrl->ncommunities; i++) { 1482 struct intel_community *community = &pctrl->communities[i]; 1483 u32 *intmask, *hostown; 1484 1485 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1486 sizeof(*intmask), GFP_KERNEL); 1487 if (!intmask) 1488 return -ENOMEM; 1489 1490 communities[i].intmask = intmask; 1491 1492 hostown = devm_kcalloc(pctrl->dev, community->ngpps, 1493 sizeof(*hostown), GFP_KERNEL); 1494 if (!hostown) 1495 return -ENOMEM; 1496 1497 communities[i].hostown = hostown; 1498 } 1499 1500 pctrl->context.pads = pads; 1501 pctrl->context.communities = communities; 1502 #endif 1503 1504 return 0; 1505 } 1506 1507 static int intel_pinctrl_probe(struct platform_device *pdev, 1508 const struct intel_pinctrl_soc_data *soc_data) 1509 { 1510 struct intel_pinctrl *pctrl; 1511 int i, ret, irq; 1512 1513 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1514 if (!pctrl) 1515 return -ENOMEM; 1516 1517 pctrl->dev = &pdev->dev; 1518 pctrl->soc = soc_data; 1519 raw_spin_lock_init(&pctrl->lock); 1520 1521 /* 1522 * Make a copy of the communities which we can use to hold pointers 1523 * to the registers. 1524 */ 1525 pctrl->ncommunities = pctrl->soc->ncommunities; 1526 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, 1527 sizeof(*pctrl->communities), GFP_KERNEL); 1528 if (!pctrl->communities) 1529 return -ENOMEM; 1530 1531 for (i = 0; i < pctrl->ncommunities; i++) { 1532 struct intel_community *community = &pctrl->communities[i]; 1533 void __iomem *regs; 1534 u32 offset; 1535 u32 value; 1536 1537 *community = pctrl->soc->communities[i]; 1538 1539 regs = devm_platform_ioremap_resource(pdev, community->barno); 1540 if (IS_ERR(regs)) 1541 return PTR_ERR(regs); 1542 1543 /* 1544 * Determine community features based on the revision. 1545 * A value of all ones means the device is not present. 1546 */ 1547 value = readl(regs + REVID); 1548 if (value == ~0u) 1549 return -ENODEV; 1550 if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) { 1551 community->features |= PINCTRL_FEATURE_DEBOUNCE; 1552 community->features |= PINCTRL_FEATURE_1K_PD; 1553 } 1554 1555 /* Determine community features based on the capabilities */ 1556 offset = CAPLIST; 1557 do { 1558 value = readl(regs + offset); 1559 switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) { 1560 case CAPLIST_ID_GPIO_HW_INFO: 1561 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO; 1562 break; 1563 case CAPLIST_ID_PWM: 1564 community->features |= PINCTRL_FEATURE_PWM; 1565 break; 1566 case CAPLIST_ID_BLINK: 1567 community->features |= PINCTRL_FEATURE_BLINK; 1568 break; 1569 case CAPLIST_ID_EXP: 1570 community->features |= PINCTRL_FEATURE_EXP; 1571 break; 1572 default: 1573 break; 1574 } 1575 offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT; 1576 } while (offset); 1577 1578 dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features); 1579 1580 /* Read offset of the pad configuration registers */ 1581 offset = readl(regs + PADBAR); 1582 1583 community->regs = regs; 1584 community->pad_regs = regs + offset; 1585 1586 if (community->gpps) 1587 ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community); 1588 else 1589 ret = intel_pinctrl_add_padgroups_by_size(pctrl, community); 1590 if (ret) 1591 return ret; 1592 } 1593 1594 irq = platform_get_irq(pdev, 0); 1595 if (irq < 0) 1596 return irq; 1597 1598 ret = intel_pinctrl_pm_init(pctrl); 1599 if (ret) 1600 return ret; 1601 1602 pctrl->pctldesc = intel_pinctrl_desc; 1603 pctrl->pctldesc.name = dev_name(&pdev->dev); 1604 pctrl->pctldesc.pins = pctrl->soc->pins; 1605 pctrl->pctldesc.npins = pctrl->soc->npins; 1606 1607 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1608 pctrl); 1609 if (IS_ERR(pctrl->pctldev)) { 1610 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1611 return PTR_ERR(pctrl->pctldev); 1612 } 1613 1614 ret = intel_gpio_probe(pctrl, irq); 1615 if (ret) 1616 return ret; 1617 1618 platform_set_drvdata(pdev, pctrl); 1619 1620 return 0; 1621 } 1622 1623 int intel_pinctrl_probe_by_hid(struct platform_device *pdev) 1624 { 1625 const struct intel_pinctrl_soc_data *data; 1626 1627 data = device_get_match_data(&pdev->dev); 1628 if (!data) 1629 return -ENODATA; 1630 1631 return intel_pinctrl_probe(pdev, data); 1632 } 1633 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); 1634 1635 int intel_pinctrl_probe_by_uid(struct platform_device *pdev) 1636 { 1637 const struct intel_pinctrl_soc_data *data; 1638 1639 data = intel_pinctrl_get_soc_data(pdev); 1640 if (IS_ERR(data)) 1641 return PTR_ERR(data); 1642 1643 return intel_pinctrl_probe(pdev, data); 1644 } 1645 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); 1646 1647 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) 1648 { 1649 const struct intel_pinctrl_soc_data * const *table; 1650 const struct intel_pinctrl_soc_data *data = NULL; 1651 1652 table = device_get_match_data(&pdev->dev); 1653 if (table) { 1654 struct acpi_device *adev = ACPI_COMPANION(&pdev->dev); 1655 unsigned int i; 1656 1657 for (i = 0; table[i]; i++) { 1658 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) { 1659 data = table[i]; 1660 break; 1661 } 1662 } 1663 } else { 1664 const struct platform_device_id *id; 1665 1666 id = platform_get_device_id(pdev); 1667 if (!id) 1668 return ERR_PTR(-ENODEV); 1669 1670 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data; 1671 data = table[pdev->id]; 1672 } 1673 1674 return data ?: ERR_PTR(-ENODATA); 1675 } 1676 EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data); 1677 1678 #ifdef CONFIG_PM_SLEEP 1679 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) 1680 { 1681 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1682 u32 value; 1683 1684 if (!pd || !intel_pad_usable(pctrl, pin)) 1685 return false; 1686 1687 /* 1688 * Only restore the pin if it is actually in use by the kernel (or 1689 * by userspace). It is possible that some pins are used by the 1690 * BIOS during resume and those are not always locked down so leave 1691 * them alone. 1692 */ 1693 if (pd->mux_owner || pd->gpio_owner || 1694 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) 1695 return true; 1696 1697 /* 1698 * The firmware on some systems may configure GPIO pins to be 1699 * an interrupt source in so called "direct IRQ" mode. In such 1700 * cases the GPIO controller driver has no idea if those pins 1701 * are being used or not. At the same time, there is a known bug 1702 * in the firmwares that don't restore the pin settings correctly 1703 * after suspend, i.e. by an unknown reason the Rx value becomes 1704 * inverted. 1705 * 1706 * Hence, let's save and restore the pins that are configured 1707 * as GPIOs in the input mode with GPIROUTIOXAPIC bit set. 1708 * 1709 * See https://bugzilla.kernel.org/show_bug.cgi?id=214749. 1710 */ 1711 value = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 1712 if ((value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) && 1713 (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO)) 1714 return true; 1715 1716 return false; 1717 } 1718 1719 int intel_pinctrl_suspend_noirq(struct device *dev) 1720 { 1721 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1722 struct intel_community_context *communities; 1723 struct intel_pad_context *pads; 1724 int i; 1725 1726 pads = pctrl->context.pads; 1727 for (i = 0; i < pctrl->soc->npins; i++) { 1728 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1729 void __iomem *padcfg; 1730 u32 val; 1731 1732 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1733 continue; 1734 1735 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1736 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1737 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1738 pads[i].padcfg1 = val; 1739 1740 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1741 if (padcfg) 1742 pads[i].padcfg2 = readl(padcfg); 1743 } 1744 1745 communities = pctrl->context.communities; 1746 for (i = 0; i < pctrl->ncommunities; i++) { 1747 struct intel_community *community = &pctrl->communities[i]; 1748 void __iomem *base; 1749 unsigned int gpp; 1750 1751 base = community->regs + community->ie_offset; 1752 for (gpp = 0; gpp < community->ngpps; gpp++) 1753 communities[i].intmask[gpp] = readl(base + gpp * 4); 1754 1755 base = community->regs + community->hostown_offset; 1756 for (gpp = 0; gpp < community->ngpps; gpp++) 1757 communities[i].hostown[gpp] = readl(base + gpp * 4); 1758 } 1759 1760 return 0; 1761 } 1762 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq); 1763 1764 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value) 1765 { 1766 u32 curr, updated; 1767 1768 curr = readl(reg); 1769 1770 updated = (curr & ~mask) | (value & mask); 1771 if (curr == updated) 1772 return false; 1773 1774 writel(updated, reg); 1775 return true; 1776 } 1777 1778 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, 1779 void __iomem *base, unsigned int gpp, u32 saved) 1780 { 1781 const struct intel_community *community = &pctrl->communities[c]; 1782 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1783 struct device *dev = pctrl->dev; 1784 const char *dummy; 1785 u32 requested = 0; 1786 unsigned int i; 1787 1788 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1789 return; 1790 1791 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy) 1792 requested |= BIT(i); 1793 1794 if (!intel_gpio_update_reg(base + gpp * 4, requested, saved)) 1795 return; 1796 1797 dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1798 } 1799 1800 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, 1801 void __iomem *base, unsigned int gpp, u32 saved) 1802 { 1803 struct device *dev = pctrl->dev; 1804 1805 if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved)) 1806 return; 1807 1808 dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1809 } 1810 1811 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, 1812 unsigned int reg, u32 saved) 1813 { 1814 u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0; 1815 unsigned int n = reg / sizeof(u32); 1816 struct device *dev = pctrl->dev; 1817 void __iomem *padcfg; 1818 1819 padcfg = intel_get_padcfg(pctrl, pin, reg); 1820 if (!padcfg) 1821 return; 1822 1823 if (!intel_gpio_update_reg(padcfg, ~mask, saved)) 1824 return; 1825 1826 dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg)); 1827 } 1828 1829 int intel_pinctrl_resume_noirq(struct device *dev) 1830 { 1831 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1832 const struct intel_community_context *communities; 1833 const struct intel_pad_context *pads; 1834 int i; 1835 1836 /* Mask all interrupts */ 1837 intel_gpio_irq_init(pctrl); 1838 1839 pads = pctrl->context.pads; 1840 for (i = 0; i < pctrl->soc->npins; i++) { 1841 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1842 1843 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1844 continue; 1845 1846 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); 1847 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); 1848 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); 1849 } 1850 1851 communities = pctrl->context.communities; 1852 for (i = 0; i < pctrl->ncommunities; i++) { 1853 struct intel_community *community = &pctrl->communities[i]; 1854 void __iomem *base; 1855 unsigned int gpp; 1856 1857 base = community->regs + community->ie_offset; 1858 for (gpp = 0; gpp < community->ngpps; gpp++) 1859 intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]); 1860 1861 base = community->regs + community->hostown_offset; 1862 for (gpp = 0; gpp < community->ngpps; gpp++) 1863 intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]); 1864 } 1865 1866 return 0; 1867 } 1868 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq); 1869 #endif 1870 1871 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1872 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1873 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1874 MODULE_LICENSE("GPL v2"); 1875