1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pinctrl GPIO driver for Intel Baytrail 4 * 5 * Copyright (C) 2012-2013 Intel Corporation 6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/array_size.h> 11 #include <linux/bitops.h> 12 #include <linux/cleanup.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/types.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm.h> 21 #include <linux/property.h> 22 #include <linux/seq_file.h> 23 #include <linux/string_helpers.h> 24 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 #include <linux/pinctrl/pinconf.h> 28 #include <linux/pinctrl/pinconf-generic.h> 29 30 #include "pinctrl-intel.h" 31 32 /* memory mapped register offsets */ 33 #define BYT_CONF0_REG 0x000 34 #define BYT_CONF1_REG 0x004 35 #define BYT_VAL_REG 0x008 36 #define BYT_DFT_REG 0x00c 37 #define BYT_INT_STAT_REG 0x800 38 #define BYT_DIRECT_IRQ_REG 0x980 39 #define BYT_DEBOUNCE_REG 0x9d0 40 41 /* BYT_CONF0_REG register bits */ 42 #define BYT_IODEN BIT(31) 43 #define BYT_DIRECT_IRQ_EN BIT(27) 44 #define BYT_TRIG_MASK GENMASK(26, 24) 45 #define BYT_TRIG_NEG BIT(26) 46 #define BYT_TRIG_POS BIT(25) 47 #define BYT_TRIG_LVL BIT(24) 48 #define BYT_DEBOUNCE_EN BIT(20) 49 #define BYT_GLITCH_FILTER_EN BIT(19) 50 #define BYT_GLITCH_F_SLOW_CLK BIT(17) 51 #define BYT_GLITCH_F_FAST_CLK BIT(16) 52 #define BYT_PULL_STR_SHIFT 9 53 #define BYT_PULL_STR_MASK GENMASK(10, 9) 54 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 55 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) 56 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) 57 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) 58 #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7) 59 #define BYT_PULL_ASSIGN_DOWN BIT(8) 60 #define BYT_PULL_ASSIGN_UP BIT(7) 61 #define BYT_PIN_MUX GENMASK(2, 0) 62 63 /* BYT_VAL_REG register bits */ 64 #define BYT_DIR_MASK GENMASK(2, 1) 65 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ 66 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ 67 #define BYT_LEVEL BIT(0) 68 69 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX) 70 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL) 71 72 /* BYT_DEBOUNCE_REG bits */ 73 #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0) 74 #define BYT_DEBOUNCE_PULSE_375US 1 75 #define BYT_DEBOUNCE_PULSE_750US 2 76 #define BYT_DEBOUNCE_PULSE_1500US 3 77 #define BYT_DEBOUNCE_PULSE_3MS 4 78 #define BYT_DEBOUNCE_PULSE_6MS 5 79 #define BYT_DEBOUNCE_PULSE_12MS 6 80 #define BYT_DEBOUNCE_PULSE_24MS 7 81 82 #define BYT_NGPIO_SCORE 102 83 #define BYT_NGPIO_NCORE 28 84 #define BYT_NGPIO_SUS 44 85 86 #define BYT_SCORE_ACPI_UID "1" 87 #define BYT_NCORE_ACPI_UID "2" 88 #define BYT_SUS_ACPI_UID "3" 89 90 /* 91 * This is the function value most pins have for GPIO muxing. If the value 92 * differs from the default one, it must be explicitly mentioned. Otherwise, the 93 * pin control implementation will set the muxing value to default GPIO if it 94 * does not find a match for the requested function. 95 */ 96 #define BYT_DEFAULT_GPIO_MUX 0 97 #define BYT_ALTER_GPIO_MUX 1 98 99 struct intel_pad_context { 100 u32 conf0; 101 u32 val; 102 }; 103 104 #define BYT_COMMUNITY(p, n, g, map) \ 105 { \ 106 .pin_base = (p), \ 107 .npins = (n), \ 108 .gpps = (g), \ 109 .ngpps = ARRAY_SIZE(g), \ 110 .pad_map = (map),\ 111 } 112 113 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */ 114 static const struct pinctrl_pin_desc byt_score_pins[] = { 115 PINCTRL_PIN(0, "SATA_GP0"), 116 PINCTRL_PIN(1, "SATA_GP1"), 117 PINCTRL_PIN(2, "SATA_LED#"), 118 PINCTRL_PIN(3, "PCIE_CLKREQ0"), 119 PINCTRL_PIN(4, "PCIE_CLKREQ1"), 120 PINCTRL_PIN(5, "PCIE_CLKREQ2"), 121 PINCTRL_PIN(6, "PCIE_CLKREQ3"), 122 PINCTRL_PIN(7, "SD3_WP"), 123 PINCTRL_PIN(8, "HDA_RST"), 124 PINCTRL_PIN(9, "HDA_SYNC"), 125 PINCTRL_PIN(10, "HDA_CLK"), 126 PINCTRL_PIN(11, "HDA_SDO"), 127 PINCTRL_PIN(12, "HDA_SDI0"), 128 PINCTRL_PIN(13, "HDA_SDI1"), 129 PINCTRL_PIN(14, "GPIO_S0_SC14"), 130 PINCTRL_PIN(15, "GPIO_S0_SC15"), 131 PINCTRL_PIN(16, "MMC1_CLK"), 132 PINCTRL_PIN(17, "MMC1_D0"), 133 PINCTRL_PIN(18, "MMC1_D1"), 134 PINCTRL_PIN(19, "MMC1_D2"), 135 PINCTRL_PIN(20, "MMC1_D3"), 136 PINCTRL_PIN(21, "MMC1_D4"), 137 PINCTRL_PIN(22, "MMC1_D5"), 138 PINCTRL_PIN(23, "MMC1_D6"), 139 PINCTRL_PIN(24, "MMC1_D7"), 140 PINCTRL_PIN(25, "MMC1_CMD"), 141 PINCTRL_PIN(26, "MMC1_RST"), 142 PINCTRL_PIN(27, "SD2_CLK"), 143 PINCTRL_PIN(28, "SD2_D0"), 144 PINCTRL_PIN(29, "SD2_D1"), 145 PINCTRL_PIN(30, "SD2_D2"), 146 PINCTRL_PIN(31, "SD2_D3_CD"), 147 PINCTRL_PIN(32, "SD2_CMD"), 148 PINCTRL_PIN(33, "SD3_CLK"), 149 PINCTRL_PIN(34, "SD3_D0"), 150 PINCTRL_PIN(35, "SD3_D1"), 151 PINCTRL_PIN(36, "SD3_D2"), 152 PINCTRL_PIN(37, "SD3_D3"), 153 PINCTRL_PIN(38, "SD3_CD"), 154 PINCTRL_PIN(39, "SD3_CMD"), 155 PINCTRL_PIN(40, "SD3_1P8EN"), 156 PINCTRL_PIN(41, "SD3_PWREN#"), 157 PINCTRL_PIN(42, "ILB_LPC_AD0"), 158 PINCTRL_PIN(43, "ILB_LPC_AD1"), 159 PINCTRL_PIN(44, "ILB_LPC_AD2"), 160 PINCTRL_PIN(45, "ILB_LPC_AD3"), 161 PINCTRL_PIN(46, "ILB_LPC_FRAME"), 162 PINCTRL_PIN(47, "ILB_LPC_CLK0"), 163 PINCTRL_PIN(48, "ILB_LPC_CLK1"), 164 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"), 165 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"), 166 PINCTRL_PIN(51, "PCU_SMB_DATA"), 167 PINCTRL_PIN(52, "PCU_SMB_CLK"), 168 PINCTRL_PIN(53, "PCU_SMB_ALERT"), 169 PINCTRL_PIN(54, "ILB_8254_SPKR"), 170 PINCTRL_PIN(55, "GPIO_S0_SC55"), 171 PINCTRL_PIN(56, "GPIO_S0_SC56"), 172 PINCTRL_PIN(57, "GPIO_S0_SC57"), 173 PINCTRL_PIN(58, "GPIO_S0_SC58"), 174 PINCTRL_PIN(59, "GPIO_S0_SC59"), 175 PINCTRL_PIN(60, "GPIO_S0_SC60"), 176 PINCTRL_PIN(61, "GPIO_S0_SC61"), 177 PINCTRL_PIN(62, "LPE_I2S2_CLK"), 178 PINCTRL_PIN(63, "LPE_I2S2_FRM"), 179 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"), 180 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"), 181 PINCTRL_PIN(66, "SIO_SPI_CS"), 182 PINCTRL_PIN(67, "SIO_SPI_MISO"), 183 PINCTRL_PIN(68, "SIO_SPI_MOSI"), 184 PINCTRL_PIN(69, "SIO_SPI_CLK"), 185 PINCTRL_PIN(70, "SIO_UART1_RXD"), 186 PINCTRL_PIN(71, "SIO_UART1_TXD"), 187 PINCTRL_PIN(72, "SIO_UART1_RTS"), 188 PINCTRL_PIN(73, "SIO_UART1_CTS"), 189 PINCTRL_PIN(74, "SIO_UART2_RXD"), 190 PINCTRL_PIN(75, "SIO_UART2_TXD"), 191 PINCTRL_PIN(76, "SIO_UART2_RTS"), 192 PINCTRL_PIN(77, "SIO_UART2_CTS"), 193 PINCTRL_PIN(78, "SIO_I2C0_DATA"), 194 PINCTRL_PIN(79, "SIO_I2C0_CLK"), 195 PINCTRL_PIN(80, "SIO_I2C1_DATA"), 196 PINCTRL_PIN(81, "SIO_I2C1_CLK"), 197 PINCTRL_PIN(82, "SIO_I2C2_DATA"), 198 PINCTRL_PIN(83, "SIO_I2C2_CLK"), 199 PINCTRL_PIN(84, "SIO_I2C3_DATA"), 200 PINCTRL_PIN(85, "SIO_I2C3_CLK"), 201 PINCTRL_PIN(86, "SIO_I2C4_DATA"), 202 PINCTRL_PIN(87, "SIO_I2C4_CLK"), 203 PINCTRL_PIN(88, "SIO_I2C5_DATA"), 204 PINCTRL_PIN(89, "SIO_I2C5_CLK"), 205 PINCTRL_PIN(90, "SIO_I2C6_DATA"), 206 PINCTRL_PIN(91, "SIO_I2C6_CLK"), 207 PINCTRL_PIN(92, "GPIO_S0_SC92"), 208 PINCTRL_PIN(93, "GPIO_S0_SC93"), 209 PINCTRL_PIN(94, "SIO_PWM0"), 210 PINCTRL_PIN(95, "SIO_PWM1"), 211 PINCTRL_PIN(96, "PMC_PLT_CLK0"), 212 PINCTRL_PIN(97, "PMC_PLT_CLK1"), 213 PINCTRL_PIN(98, "PMC_PLT_CLK2"), 214 PINCTRL_PIN(99, "PMC_PLT_CLK3"), 215 PINCTRL_PIN(100, "PMC_PLT_CLK4"), 216 PINCTRL_PIN(101, "PMC_PLT_CLK5"), 217 }; 218 219 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = { 220 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, 221 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, 222 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, 223 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, 224 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, 225 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, 226 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, 227 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, 228 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, 229 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, 230 97, 100, 231 }; 232 233 /* SCORE groups */ 234 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 }; 235 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 }; 236 static const unsigned int byt_score_uart3_pins[] = { 57, 61 }; 237 238 static const unsigned int byt_score_pwm0_pins[] = { 94 }; 239 static const unsigned int byt_score_pwm1_pins[] = { 95 }; 240 241 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 }; 242 243 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 }; 244 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 }; 245 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 }; 246 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 }; 247 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 }; 248 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 }; 249 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 }; 250 251 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 }; 252 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 }; 253 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 }; 254 255 static const unsigned int byt_score_sdcard_pins[] = { 256 7, 33, 34, 35, 36, 37, 38, 39, 40, 41, 257 }; 258 static const unsigned int byt_score_sdcard_mux_values[] = { 259 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 260 }; 261 262 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 }; 263 264 static const unsigned int byt_score_emmc_pins[] = { 265 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 266 }; 267 268 static const unsigned int byt_score_ilb_lpc_pins[] = { 269 42, 43, 44, 45, 46, 47, 48, 49, 50, 270 }; 271 272 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 }; 273 274 static const unsigned int byt_score_plt_clk0_pins[] = { 96 }; 275 static const unsigned int byt_score_plt_clk1_pins[] = { 97 }; 276 static const unsigned int byt_score_plt_clk2_pins[] = { 98 }; 277 static const unsigned int byt_score_plt_clk3_pins[] = { 99 }; 278 static const unsigned int byt_score_plt_clk4_pins[] = { 100 }; 279 static const unsigned int byt_score_plt_clk5_pins[] = { 101 }; 280 281 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 }; 282 283 static const struct intel_pingroup byt_score_groups[] = { 284 PIN_GROUP_GPIO("uart1_grp", byt_score_uart1_pins, 1), 285 PIN_GROUP_GPIO("uart2_grp", byt_score_uart2_pins, 1), 286 PIN_GROUP_GPIO("uart3_grp", byt_score_uart3_pins, 1), 287 PIN_GROUP_GPIO("pwm0_grp", byt_score_pwm0_pins, 1), 288 PIN_GROUP_GPIO("pwm1_grp", byt_score_pwm1_pins, 1), 289 PIN_GROUP_GPIO("ssp2_grp", byt_score_ssp2_pins, 1), 290 PIN_GROUP_GPIO("sio_spi_grp", byt_score_sio_spi_pins, 1), 291 PIN_GROUP_GPIO("i2c5_grp", byt_score_i2c5_pins, 1), 292 PIN_GROUP_GPIO("i2c6_grp", byt_score_i2c6_pins, 1), 293 PIN_GROUP_GPIO("i2c4_grp", byt_score_i2c4_pins, 1), 294 PIN_GROUP_GPIO("i2c3_grp", byt_score_i2c3_pins, 1), 295 PIN_GROUP_GPIO("i2c2_grp", byt_score_i2c2_pins, 1), 296 PIN_GROUP_GPIO("i2c1_grp", byt_score_i2c1_pins, 1), 297 PIN_GROUP_GPIO("i2c0_grp", byt_score_i2c0_pins, 1), 298 PIN_GROUP_GPIO("ssp0_grp", byt_score_ssp0_pins, 1), 299 PIN_GROUP_GPIO("ssp1_grp", byt_score_ssp1_pins, 1), 300 PIN_GROUP_GPIO("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values), 301 PIN_GROUP_GPIO("sdio_grp", byt_score_sdio_pins, 1), 302 PIN_GROUP_GPIO("emmc_grp", byt_score_emmc_pins, 1), 303 PIN_GROUP_GPIO("lpc_grp", byt_score_ilb_lpc_pins, 1), 304 PIN_GROUP_GPIO("sata_grp", byt_score_sata_pins, 1), 305 PIN_GROUP_GPIO("plt_clk0_grp", byt_score_plt_clk0_pins, 1), 306 PIN_GROUP_GPIO("plt_clk1_grp", byt_score_plt_clk1_pins, 1), 307 PIN_GROUP_GPIO("plt_clk2_grp", byt_score_plt_clk2_pins, 1), 308 PIN_GROUP_GPIO("plt_clk3_grp", byt_score_plt_clk3_pins, 1), 309 PIN_GROUP_GPIO("plt_clk4_grp", byt_score_plt_clk4_pins, 1), 310 PIN_GROUP_GPIO("plt_clk5_grp", byt_score_plt_clk5_pins, 1), 311 PIN_GROUP_GPIO("smbus_grp", byt_score_smbus_pins, 1), 312 }; 313 314 static const char * const byt_score_uart_groups[] = { 315 "uart1_grp", "uart2_grp", "uart3_grp", 316 }; 317 static const char * const byt_score_pwm_groups[] = { 318 "pwm0_grp", "pwm1_grp", 319 }; 320 static const char * const byt_score_ssp_groups[] = { 321 "ssp0_grp", "ssp1_grp", "ssp2_grp", 322 }; 323 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" }; 324 static const char * const byt_score_i2c_groups[] = { 325 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", 326 "i2c6_grp", 327 }; 328 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" }; 329 static const char * const byt_score_sdio_groups[] = { "sdio_grp" }; 330 static const char * const byt_score_emmc_groups[] = { "emmc_grp" }; 331 static const char * const byt_score_lpc_groups[] = { "lpc_grp" }; 332 static const char * const byt_score_sata_groups[] = { "sata_grp" }; 333 static const char * const byt_score_plt_clk_groups[] = { 334 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 335 "plt_clk4_grp", "plt_clk5_grp", 336 }; 337 static const char * const byt_score_smbus_groups[] = { "smbus_grp" }; 338 static const char * const byt_score_gpio_groups[] = { 339 "uart1_grp_gpio", "uart2_grp_gpio", "uart3_grp_gpio", "pwm0_grp_gpio", 340 "pwm1_grp_gpio", "ssp0_grp_gpio", "ssp1_grp_gpio", "ssp2_grp_gpio", 341 "sio_spi_grp_gpio", "i2c0_grp_gpio", "i2c1_grp_gpio", "i2c2_grp_gpio", 342 "i2c3_grp_gpio", "i2c4_grp_gpio", "i2c5_grp_gpio", "i2c6_grp_gpio", 343 "sdcard_grp_gpio", "sdio_grp_gpio", "emmc_grp_gpio", "lpc_grp_gpio", 344 "sata_grp_gpio", "plt_clk0_grp_gpio", "plt_clk1_grp_gpio", 345 "plt_clk2_grp_gpio", "plt_clk3_grp_gpio", "plt_clk4_grp_gpio", 346 "plt_clk5_grp_gpio", "smbus_grp_gpio", 347 }; 348 349 static const struct intel_function byt_score_functions[] = { 350 FUNCTION("uart", byt_score_uart_groups), 351 FUNCTION("pwm", byt_score_pwm_groups), 352 FUNCTION("ssp", byt_score_ssp_groups), 353 FUNCTION("spi", byt_score_spi_groups), 354 FUNCTION("i2c", byt_score_i2c_groups), 355 FUNCTION("sdcard", byt_score_sdcard_groups), 356 FUNCTION("sdio", byt_score_sdio_groups), 357 FUNCTION("emmc", byt_score_emmc_groups), 358 FUNCTION("lpc", byt_score_lpc_groups), 359 FUNCTION("sata", byt_score_sata_groups), 360 FUNCTION("plt_clk", byt_score_plt_clk_groups), 361 FUNCTION("smbus", byt_score_smbus_groups), 362 FUNCTION("gpio", byt_score_gpio_groups), 363 }; 364 365 static const struct intel_padgroup byt_score_gpps[] = { 366 INTEL_GPP(0, 0, 31, 0), 367 INTEL_GPP(1, 32, 63, 32), 368 INTEL_GPP(2, 64, 95, 64), 369 INTEL_GPP(3, 96, 101, 96), 370 }; 371 372 static const struct intel_community byt_score_communities[] = { 373 BYT_COMMUNITY(0, 102, byt_score_gpps, byt_score_pins_map), 374 }; 375 376 static const struct intel_pinctrl_soc_data byt_score_soc_data = { 377 .uid = BYT_SCORE_ACPI_UID, 378 .pins = byt_score_pins, 379 .npins = ARRAY_SIZE(byt_score_pins), 380 .groups = byt_score_groups, 381 .ngroups = ARRAY_SIZE(byt_score_groups), 382 .functions = byt_score_functions, 383 .nfunctions = ARRAY_SIZE(byt_score_functions), 384 .communities = byt_score_communities, 385 .ncommunities = ARRAY_SIZE(byt_score_communities), 386 }; 387 388 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */ 389 static const struct pinctrl_pin_desc byt_sus_pins[] = { 390 PINCTRL_PIN(0, "GPIO_S50"), 391 PINCTRL_PIN(1, "GPIO_S51"), 392 PINCTRL_PIN(2, "GPIO_S52"), 393 PINCTRL_PIN(3, "GPIO_S53"), 394 PINCTRL_PIN(4, "GPIO_S54"), 395 PINCTRL_PIN(5, "GPIO_S55"), 396 PINCTRL_PIN(6, "GPIO_S56"), 397 PINCTRL_PIN(7, "GPIO_S57"), 398 PINCTRL_PIN(8, "GPIO_S58"), 399 PINCTRL_PIN(9, "GPIO_S59"), 400 PINCTRL_PIN(10, "GPIO_S510"), 401 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"), 402 PINCTRL_PIN(12, "PMC_SUSCLK0"), 403 PINCTRL_PIN(13, "GPIO_S513"), 404 PINCTRL_PIN(14, "USB_ULPI_RST"), 405 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"), 406 PINCTRL_PIN(16, "PMC_PWRBTN"), 407 PINCTRL_PIN(17, "GPIO_S517"), 408 PINCTRL_PIN(18, "PMC_SUS_STAT"), 409 PINCTRL_PIN(19, "USB_OC0"), 410 PINCTRL_PIN(20, "USB_OC1"), 411 PINCTRL_PIN(21, "PCU_SPI_CS1"), 412 PINCTRL_PIN(22, "GPIO_S522"), 413 PINCTRL_PIN(23, "GPIO_S523"), 414 PINCTRL_PIN(24, "GPIO_S524"), 415 PINCTRL_PIN(25, "GPIO_S525"), 416 PINCTRL_PIN(26, "GPIO_S526"), 417 PINCTRL_PIN(27, "GPIO_S527"), 418 PINCTRL_PIN(28, "GPIO_S528"), 419 PINCTRL_PIN(29, "GPIO_S529"), 420 PINCTRL_PIN(30, "GPIO_S530"), 421 PINCTRL_PIN(31, "USB_ULPI_CLK"), 422 PINCTRL_PIN(32, "USB_ULPI_DATA0"), 423 PINCTRL_PIN(33, "USB_ULPI_DATA1"), 424 PINCTRL_PIN(34, "USB_ULPI_DATA2"), 425 PINCTRL_PIN(35, "USB_ULPI_DATA3"), 426 PINCTRL_PIN(36, "USB_ULPI_DATA4"), 427 PINCTRL_PIN(37, "USB_ULPI_DATA5"), 428 PINCTRL_PIN(38, "USB_ULPI_DATA6"), 429 PINCTRL_PIN(39, "USB_ULPI_DATA7"), 430 PINCTRL_PIN(40, "USB_ULPI_DIR"), 431 PINCTRL_PIN(41, "USB_ULPI_NXT"), 432 PINCTRL_PIN(42, "USB_ULPI_STP"), 433 PINCTRL_PIN(43, "USB_ULPI_REFCLK"), 434 }; 435 436 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = { 437 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 438 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 439 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 440 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 441 52, 53, 59, 40, 442 }; 443 444 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 }; 445 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 }; 446 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 }; 447 448 static const unsigned int byt_sus_usb_ulpi_pins[] = { 449 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 450 }; 451 static const unsigned int byt_sus_usb_ulpi_mode_values[] = { 452 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 453 }; 454 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = { 455 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 456 }; 457 458 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 }; 459 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 }; 460 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 }; 461 462 static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 }; 463 static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 }; 464 465 static const struct intel_pingroup byt_sus_groups[] = { 466 PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values), 467 PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values), 468 PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values), 469 PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values), 470 PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values), 471 PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values), 472 PIN_GROUP_GPIO("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1), 473 PIN_GROUP_GPIO("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1), 474 }; 475 476 static const char * const byt_sus_usb_groups[] = { 477 "usb_oc_grp", "usb_ulpi_grp", 478 }; 479 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" }; 480 static const char * const byt_sus_pmu_clk_groups[] = { 481 "pmu_clk1_grp", "pmu_clk2_grp", 482 }; 483 static const char * const byt_sus_gpio_groups[] = { 484 "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio", 485 "pmu_clk1_grp_gpio", "pmu_clk2_grp_gpio", 486 }; 487 488 static const struct intel_function byt_sus_functions[] = { 489 FUNCTION("usb", byt_sus_usb_groups), 490 FUNCTION("spi", byt_sus_spi_groups), 491 FUNCTION("gpio", byt_sus_gpio_groups), 492 FUNCTION("pmu_clk", byt_sus_pmu_clk_groups), 493 }; 494 495 static const struct intel_padgroup byt_sus_gpps[] = { 496 INTEL_GPP(0, 0, 31, 0), 497 INTEL_GPP(1, 32, 43, 32), 498 }; 499 500 static const struct intel_community byt_sus_communities[] = { 501 BYT_COMMUNITY(0, 44, byt_sus_gpps, byt_sus_pins_map), 502 }; 503 504 static const struct intel_pinctrl_soc_data byt_sus_soc_data = { 505 .uid = BYT_SUS_ACPI_UID, 506 .pins = byt_sus_pins, 507 .npins = ARRAY_SIZE(byt_sus_pins), 508 .groups = byt_sus_groups, 509 .ngroups = ARRAY_SIZE(byt_sus_groups), 510 .functions = byt_sus_functions, 511 .nfunctions = ARRAY_SIZE(byt_sus_functions), 512 .communities = byt_sus_communities, 513 .ncommunities = ARRAY_SIZE(byt_sus_communities), 514 }; 515 516 static const struct pinctrl_pin_desc byt_ncore_pins[] = { 517 PINCTRL_PIN(0, "HV_DDI0_HPD"), 518 PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"), 519 PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"), 520 PINCTRL_PIN(3, "PANEL0_VDDEN"), 521 PINCTRL_PIN(4, "PANEL0_BKLTEN"), 522 PINCTRL_PIN(5, "PANEL0_BKLTCTL"), 523 PINCTRL_PIN(6, "HV_DDI1_HPD"), 524 PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"), 525 PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"), 526 PINCTRL_PIN(9, "PANEL1_VDDEN"), 527 PINCTRL_PIN(10, "PANEL1_BKLTEN"), 528 PINCTRL_PIN(11, "PANEL1_BKLTCTL"), 529 PINCTRL_PIN(12, "GP_INTD_DSI_TE1"), 530 PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"), 531 PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"), 532 PINCTRL_PIN(15, "GP_CAMERASB00"), 533 PINCTRL_PIN(16, "GP_CAMERASB01"), 534 PINCTRL_PIN(17, "GP_CAMERASB02"), 535 PINCTRL_PIN(18, "GP_CAMERASB03"), 536 PINCTRL_PIN(19, "GP_CAMERASB04"), 537 PINCTRL_PIN(20, "GP_CAMERASB05"), 538 PINCTRL_PIN(21, "GP_CAMERASB06"), 539 PINCTRL_PIN(22, "GP_CAMERASB07"), 540 PINCTRL_PIN(23, "GP_CAMERASB08"), 541 PINCTRL_PIN(24, "GP_CAMERASB09"), 542 PINCTRL_PIN(25, "GP_CAMERASB10"), 543 PINCTRL_PIN(26, "GP_CAMERASB11"), 544 PINCTRL_PIN(27, "GP_INTD_DSI_TE2"), 545 }; 546 547 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = { 548 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 549 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 550 3, 6, 10, 13, 2, 5, 9, 7, 551 }; 552 553 static const struct intel_padgroup byt_ncore_gpps[] = { 554 INTEL_GPP(0, 0, 27, 0), 555 }; 556 557 static const struct intel_community byt_ncore_communities[] = { 558 BYT_COMMUNITY(0, 28, byt_ncore_gpps, byt_ncore_pins_map), 559 }; 560 561 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = { 562 .uid = BYT_NCORE_ACPI_UID, 563 .pins = byt_ncore_pins, 564 .npins = ARRAY_SIZE(byt_ncore_pins), 565 .communities = byt_ncore_communities, 566 .ncommunities = ARRAY_SIZE(byt_ncore_communities), 567 }; 568 569 static const struct intel_pinctrl_soc_data *byt_soc_data[] = { 570 &byt_score_soc_data, 571 &byt_sus_soc_data, 572 &byt_ncore_soc_data, 573 NULL 574 }; 575 576 static DEFINE_RAW_SPINLOCK(byt_lock); 577 578 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, 579 int reg) 580 { 581 const struct intel_community *comm; 582 u32 reg_offset; 583 584 comm = intel_get_community(vg, offset); 585 if (!comm) 586 return NULL; 587 588 offset -= comm->pin_base; 589 switch (reg) { 590 case BYT_INT_STAT_REG: 591 reg_offset = (offset / 32) * 4; 592 break; 593 case BYT_DEBOUNCE_REG: 594 reg_offset = 0; 595 break; 596 default: 597 reg_offset = comm->pad_map[offset] * 16; 598 break; 599 } 600 601 return comm->pad_regs + reg_offset + reg; 602 } 603 604 static const struct pinctrl_ops byt_pinctrl_ops = { 605 .get_groups_count = intel_get_groups_count, 606 .get_group_name = intel_get_group_name, 607 .get_group_pins = intel_get_group_pins, 608 }; 609 610 static void byt_set_group_simple_mux(struct intel_pinctrl *vg, 611 const struct intel_pingroup group, 612 unsigned int func) 613 { 614 int i; 615 616 guard(raw_spinlock_irqsave)(&byt_lock); 617 618 for (i = 0; i < group.grp.npins; i++) { 619 void __iomem *padcfg0; 620 u32 value; 621 622 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG); 623 if (!padcfg0) { 624 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", 625 group.grp.name, i); 626 continue; 627 } 628 629 value = readl(padcfg0); 630 value &= ~BYT_PIN_MUX; 631 value |= func; 632 writel(value, padcfg0); 633 } 634 } 635 636 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg, 637 const struct intel_pingroup group, 638 const unsigned int *func) 639 { 640 int i; 641 642 guard(raw_spinlock_irqsave)(&byt_lock); 643 644 for (i = 0; i < group.grp.npins; i++) { 645 void __iomem *padcfg0; 646 u32 value; 647 648 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG); 649 if (!padcfg0) { 650 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", 651 group.grp.name, i); 652 continue; 653 } 654 655 value = readl(padcfg0); 656 value &= ~BYT_PIN_MUX; 657 value |= func[i]; 658 writel(value, padcfg0); 659 } 660 } 661 662 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 663 unsigned int group_selector) 664 { 665 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 666 const struct intel_function func = vg->soc->functions[func_selector]; 667 const struct intel_pingroup group = vg->soc->groups[group_selector]; 668 669 if (group.modes) 670 byt_set_group_mixed_mux(vg, group, group.modes); 671 else if (!strcmp(func.func.name, "gpio")) 672 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX); 673 else 674 byt_set_group_simple_mux(vg, group, group.mode); 675 676 return 0; 677 } 678 679 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset) 680 { 681 /* SCORE pin 92-93 */ 682 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) && 683 offset >= 92 && offset <= 93) 684 return BYT_ALTER_GPIO_MUX; 685 686 /* SUS pin 11-21 */ 687 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) && 688 offset >= 11 && offset <= 21) 689 return BYT_ALTER_GPIO_MUX; 690 691 return BYT_DEFAULT_GPIO_MUX; 692 } 693 694 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset) 695 { 696 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 697 u32 value; 698 699 guard(raw_spinlock_irqsave)(&byt_lock); 700 701 value = readl(reg); 702 703 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */ 704 if (!(value & BYT_DIRECT_IRQ_EN)) 705 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 706 707 writel(value, reg); 708 } 709 710 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, 711 struct pinctrl_gpio_range *range, 712 unsigned int offset) 713 { 714 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 715 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 716 u32 value, gpio_mux; 717 718 guard(raw_spinlock_irqsave)(&byt_lock); 719 720 /* 721 * In most cases, func pin mux 000 means GPIO function. 722 * But, some pins may have func pin mux 001 represents 723 * GPIO function. 724 * 725 * Because there are devices out there where some pins were not 726 * configured correctly we allow changing the mux value from 727 * request (but print out warning about that). 728 */ 729 value = readl(reg) & BYT_PIN_MUX; 730 gpio_mux = byt_get_gpio_mux(vg, offset); 731 if (gpio_mux == value) 732 return 0; 733 734 value = readl(reg) & ~BYT_PIN_MUX; 735 value |= gpio_mux; 736 writel(value, reg); 737 738 dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset); 739 740 return 0; 741 } 742 743 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, 744 struct pinctrl_gpio_range *range, 745 unsigned int offset) 746 { 747 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 748 749 byt_gpio_clear_triggering(vg, offset); 750 } 751 752 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg, 753 unsigned int offset) 754 { 755 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 756 757 /* 758 * Before making any direction modifications, do a check if gpio is set 759 * for direct IRQ. On Bay Trail, setting GPIO to output does not make 760 * sense, so let's at least inform the caller before they shoot 761 * themselves in the foot. 762 */ 763 if (readl(conf_reg) & BYT_DIRECT_IRQ_EN) 764 dev_info_once(vg->dev, 765 "Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n", 766 offset); 767 } 768 769 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, 770 struct pinctrl_gpio_range *range, 771 unsigned int offset, 772 bool input) 773 { 774 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 775 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 776 u32 value; 777 778 guard(raw_spinlock_irqsave)(&byt_lock); 779 780 value = readl(val_reg); 781 value &= ~BYT_DIR_MASK; 782 if (input) 783 value |= BYT_OUTPUT_EN; 784 else 785 byt_gpio_direct_irq_check(vg, offset); 786 787 writel(value, val_reg); 788 789 return 0; 790 } 791 792 static const struct pinmux_ops byt_pinmux_ops = { 793 .get_functions_count = intel_get_functions_count, 794 .get_function_name = intel_get_function_name, 795 .get_function_groups = intel_get_function_groups, 796 .set_mux = byt_set_mux, 797 .gpio_request_enable = byt_gpio_request_enable, 798 .gpio_disable_free = byt_gpio_disable_free, 799 .gpio_set_direction = byt_gpio_set_direction, 800 }; 801 802 static void byt_get_pull_strength(u32 reg, u16 *strength) 803 { 804 switch (reg & BYT_PULL_STR_MASK) { 805 case BYT_PULL_STR_2K: 806 *strength = 2000; 807 break; 808 case BYT_PULL_STR_10K: 809 *strength = 10000; 810 break; 811 case BYT_PULL_STR_20K: 812 *strength = 20000; 813 break; 814 case BYT_PULL_STR_40K: 815 *strength = 40000; 816 break; 817 } 818 } 819 820 static int byt_set_pull_strength(u32 *reg, u16 strength) 821 { 822 *reg &= ~BYT_PULL_STR_MASK; 823 824 switch (strength) { 825 case 1: /* Set default strength value in case none is given */ 826 case 2000: 827 *reg |= BYT_PULL_STR_2K; 828 break; 829 case 10000: 830 *reg |= BYT_PULL_STR_10K; 831 break; 832 case 20000: 833 *reg |= BYT_PULL_STR_20K; 834 break; 835 case 40000: 836 *reg |= BYT_PULL_STR_40K; 837 break; 838 default: 839 return -EINVAL; 840 } 841 842 return 0; 843 } 844 845 static void byt_gpio_force_input_mode(struct intel_pinctrl *vg, unsigned int offset) 846 { 847 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 848 u32 value; 849 850 value = readl(reg); 851 if (!(value & BYT_INPUT_EN)) 852 return; 853 854 /* 855 * Pull assignment is only applicable in input mode. If 856 * chip is not in input mode, set it and warn about it. 857 */ 858 value &= ~BYT_INPUT_EN; 859 writel(value, reg); 860 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset); 861 } 862 863 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, 864 unsigned long *config) 865 { 866 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 867 enum pin_config_param param = pinconf_to_config_param(*config); 868 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 869 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 870 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 871 u32 conf, pull, val, debounce; 872 u16 arg = 0; 873 874 scoped_guard(raw_spinlock_irqsave, &byt_lock) { 875 conf = readl(conf_reg); 876 val = readl(val_reg); 877 } 878 879 pull = conf & BYT_PULL_ASSIGN_MASK; 880 881 switch (param) { 882 case PIN_CONFIG_BIAS_DISABLE: 883 if (pull) 884 return -EINVAL; 885 break; 886 case PIN_CONFIG_BIAS_PULL_DOWN: 887 /* Pull assignment is only applicable in input mode */ 888 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN) 889 return -EINVAL; 890 891 byt_get_pull_strength(conf, &arg); 892 893 break; 894 case PIN_CONFIG_BIAS_PULL_UP: 895 /* Pull assignment is only applicable in input mode */ 896 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP) 897 return -EINVAL; 898 899 byt_get_pull_strength(conf, &arg); 900 901 break; 902 case PIN_CONFIG_INPUT_DEBOUNCE: 903 if (!(conf & BYT_DEBOUNCE_EN)) 904 return -EINVAL; 905 906 scoped_guard(raw_spinlock_irqsave, &byt_lock) 907 debounce = readl(db_reg); 908 909 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) { 910 case BYT_DEBOUNCE_PULSE_375US: 911 arg = 375; 912 break; 913 case BYT_DEBOUNCE_PULSE_750US: 914 arg = 750; 915 break; 916 case BYT_DEBOUNCE_PULSE_1500US: 917 arg = 1500; 918 break; 919 case BYT_DEBOUNCE_PULSE_3MS: 920 arg = 3000; 921 break; 922 case BYT_DEBOUNCE_PULSE_6MS: 923 arg = 6000; 924 break; 925 case BYT_DEBOUNCE_PULSE_12MS: 926 arg = 12000; 927 break; 928 case BYT_DEBOUNCE_PULSE_24MS: 929 arg = 24000; 930 break; 931 default: 932 return -EINVAL; 933 } 934 935 break; 936 default: 937 return -ENOTSUPP; 938 } 939 940 *config = pinconf_to_config_packed(param, arg); 941 942 return 0; 943 } 944 945 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 946 unsigned int offset, 947 unsigned long *configs, 948 unsigned int num_configs) 949 { 950 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 951 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 952 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 953 u32 conf, db_pulse, debounce; 954 enum pin_config_param param; 955 int i, ret; 956 u32 arg; 957 958 guard(raw_spinlock_irqsave)(&byt_lock); 959 960 conf = readl(conf_reg); 961 962 for (i = 0; i < num_configs; i++) { 963 param = pinconf_to_config_param(configs[i]); 964 arg = pinconf_to_config_argument(configs[i]); 965 966 switch (param) { 967 case PIN_CONFIG_BIAS_DISABLE: 968 conf &= ~BYT_PULL_ASSIGN_MASK; 969 break; 970 case PIN_CONFIG_BIAS_PULL_DOWN: 971 byt_gpio_force_input_mode(vg, offset); 972 973 conf &= ~BYT_PULL_ASSIGN_MASK; 974 conf |= BYT_PULL_ASSIGN_DOWN; 975 ret = byt_set_pull_strength(&conf, arg); 976 if (ret) 977 return ret; 978 979 break; 980 case PIN_CONFIG_BIAS_PULL_UP: 981 byt_gpio_force_input_mode(vg, offset); 982 983 conf &= ~BYT_PULL_ASSIGN_MASK; 984 conf |= BYT_PULL_ASSIGN_UP; 985 ret = byt_set_pull_strength(&conf, arg); 986 if (ret) 987 return ret; 988 989 break; 990 case PIN_CONFIG_INPUT_DEBOUNCE: 991 switch (arg) { 992 case 0: 993 db_pulse = 0; 994 break; 995 case 375: 996 db_pulse = BYT_DEBOUNCE_PULSE_375US; 997 break; 998 case 750: 999 db_pulse = BYT_DEBOUNCE_PULSE_750US; 1000 break; 1001 case 1500: 1002 db_pulse = BYT_DEBOUNCE_PULSE_1500US; 1003 break; 1004 case 3000: 1005 db_pulse = BYT_DEBOUNCE_PULSE_3MS; 1006 break; 1007 case 6000: 1008 db_pulse = BYT_DEBOUNCE_PULSE_6MS; 1009 break; 1010 case 12000: 1011 db_pulse = BYT_DEBOUNCE_PULSE_12MS; 1012 break; 1013 case 24000: 1014 db_pulse = BYT_DEBOUNCE_PULSE_24MS; 1015 break; 1016 default: 1017 return -EINVAL; 1018 } 1019 1020 if (db_pulse) { 1021 debounce = readl(db_reg); 1022 debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse; 1023 writel(debounce, db_reg); 1024 1025 conf |= BYT_DEBOUNCE_EN; 1026 } else { 1027 conf &= ~BYT_DEBOUNCE_EN; 1028 } 1029 1030 break; 1031 default: 1032 return -ENOTSUPP; 1033 } 1034 } 1035 1036 writel(conf, conf_reg); 1037 1038 return 0; 1039 } 1040 1041 static const struct pinconf_ops byt_pinconf_ops = { 1042 .is_generic = true, 1043 .pin_config_get = byt_pin_config_get, 1044 .pin_config_set = byt_pin_config_set, 1045 }; 1046 1047 static const struct pinctrl_desc byt_pinctrl_desc = { 1048 .pctlops = &byt_pinctrl_ops, 1049 .pmxops = &byt_pinmux_ops, 1050 .confops = &byt_pinconf_ops, 1051 .owner = THIS_MODULE, 1052 }; 1053 1054 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) 1055 { 1056 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1057 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1058 u32 val; 1059 1060 scoped_guard(raw_spinlock_irqsave, &byt_lock) 1061 val = readl(reg); 1062 1063 return !!(val & BYT_LEVEL); 1064 } 1065 1066 static int byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1067 { 1068 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1069 void __iomem *reg; 1070 u32 old_val; 1071 1072 reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1073 if (!reg) 1074 return -EINVAL; 1075 1076 guard(raw_spinlock_irqsave)(&byt_lock); 1077 1078 old_val = readl(reg); 1079 if (value) 1080 writel(old_val | BYT_LEVEL, reg); 1081 else 1082 writel(old_val & ~BYT_LEVEL, reg); 1083 1084 return 0; 1085 } 1086 1087 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1088 { 1089 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1090 void __iomem *reg; 1091 u32 value; 1092 1093 reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1094 if (!reg) 1095 return -EINVAL; 1096 1097 scoped_guard(raw_spinlock_irqsave, &byt_lock) 1098 value = readl(reg); 1099 1100 if (!(value & BYT_OUTPUT_EN)) 1101 return GPIO_LINE_DIRECTION_OUT; 1102 if (!(value & BYT_INPUT_EN)) 1103 return GPIO_LINE_DIRECTION_IN; 1104 1105 return -EINVAL; 1106 } 1107 1108 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1109 { 1110 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1111 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1112 u32 reg; 1113 1114 guard(raw_spinlock_irqsave)(&byt_lock); 1115 1116 reg = readl(val_reg); 1117 reg &= ~BYT_DIR_MASK; 1118 reg |= BYT_OUTPUT_EN; 1119 writel(reg, val_reg); 1120 1121 return 0; 1122 } 1123 1124 /* 1125 * Note despite the temptation this MUST NOT be converted into a call to 1126 * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this 1127 * MUST be done as a single BYT_VAL_REG register write. 1128 * See the commit message of the commit adding this comment for details. 1129 */ 1130 static int byt_gpio_direction_output(struct gpio_chip *chip, 1131 unsigned int offset, int value) 1132 { 1133 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1134 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1135 u32 reg; 1136 1137 guard(raw_spinlock_irqsave)(&byt_lock); 1138 1139 byt_gpio_direct_irq_check(vg, offset); 1140 1141 reg = readl(val_reg); 1142 reg &= ~BYT_DIR_MASK; 1143 if (value) 1144 reg |= BYT_LEVEL; 1145 else 1146 reg &= ~BYT_LEVEL; 1147 1148 writel(reg, val_reg); 1149 1150 return 0; 1151 } 1152 1153 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1154 { 1155 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1156 int i; 1157 u32 conf0, val; 1158 1159 for (i = 0; i < vg->soc->npins; i++) { 1160 const struct intel_community *comm; 1161 void __iomem *conf_reg, *val_reg; 1162 const char *pull_str = NULL; 1163 const char *pull = NULL; 1164 unsigned int pin; 1165 1166 pin = vg->soc->pins[i].number; 1167 1168 conf_reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1169 if (!conf_reg) { 1170 seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin); 1171 continue; 1172 } 1173 1174 val_reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1175 if (!val_reg) { 1176 seq_printf(s, "Pin %i: can't retrieve VAL\n", pin); 1177 continue; 1178 } 1179 1180 scoped_guard(raw_spinlock_irqsave, &byt_lock) { 1181 conf0 = readl(conf_reg); 1182 val = readl(val_reg); 1183 } 1184 1185 comm = intel_get_community(vg, pin); 1186 if (!comm) { 1187 seq_printf(s, "Pin %i: can't retrieve community\n", pin); 1188 continue; 1189 } 1190 1191 char *label __free(kfree) = gpiochip_dup_line_label(chip, i); 1192 if (IS_ERR(label)) 1193 continue; 1194 1195 switch (conf0 & BYT_PULL_ASSIGN_MASK) { 1196 case BYT_PULL_ASSIGN_UP: 1197 pull = "up"; 1198 break; 1199 case BYT_PULL_ASSIGN_DOWN: 1200 pull = "down"; 1201 break; 1202 } 1203 1204 switch (conf0 & BYT_PULL_STR_MASK) { 1205 case BYT_PULL_STR_2K: 1206 pull_str = "2k"; 1207 break; 1208 case BYT_PULL_STR_10K: 1209 pull_str = "10k"; 1210 break; 1211 case BYT_PULL_STR_20K: 1212 pull_str = "20k"; 1213 break; 1214 case BYT_PULL_STR_40K: 1215 pull_str = "40k"; 1216 break; 1217 } 1218 1219 seq_printf(s, 1220 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", 1221 pin, 1222 label ?: "Unrequested", 1223 val & BYT_INPUT_EN ? " " : "in", 1224 val & BYT_OUTPUT_EN ? " " : "out", 1225 str_hi_lo(val & BYT_LEVEL), 1226 comm->pad_map[i], comm->pad_map[i] * 16, 1227 conf0 & 0x7, 1228 conf0 & BYT_TRIG_NEG ? " fall" : " ", 1229 conf0 & BYT_TRIG_POS ? " rise" : " ", 1230 conf0 & BYT_TRIG_LVL ? " level" : " "); 1231 1232 if (pull && pull_str) 1233 seq_printf(s, " %-4s %-3s", pull, pull_str); 1234 else 1235 seq_puts(s, " "); 1236 1237 if (conf0 & BYT_IODEN) 1238 seq_puts(s, " open-drain"); 1239 1240 seq_puts(s, "\n"); 1241 } 1242 } 1243 1244 static const struct gpio_chip byt_gpio_chip = { 1245 .owner = THIS_MODULE, 1246 .request = gpiochip_generic_request, 1247 .free = gpiochip_generic_free, 1248 .get_direction = byt_gpio_get_direction, 1249 .direction_input = byt_gpio_direction_input, 1250 .direction_output = byt_gpio_direction_output, 1251 .get = byt_gpio_get, 1252 .set = byt_gpio_set, 1253 .set_config = gpiochip_generic_config, 1254 .dbg_show = byt_gpio_dbg_show, 1255 }; 1256 1257 static void byt_irq_ack(struct irq_data *d) 1258 { 1259 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1260 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1261 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1262 void __iomem *reg; 1263 1264 reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG); 1265 if (!reg) 1266 return; 1267 1268 guard(raw_spinlock)(&byt_lock); 1269 1270 writel(BIT(hwirq % 32), reg); 1271 } 1272 1273 static void byt_irq_mask(struct irq_data *d) 1274 { 1275 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1276 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1277 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1278 1279 byt_gpio_clear_triggering(vg, hwirq); 1280 gpiochip_disable_irq(gc, hwirq); 1281 } 1282 1283 static void byt_irq_unmask(struct irq_data *d) 1284 { 1285 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1286 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1287 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1288 void __iomem *reg; 1289 u32 value; 1290 1291 gpiochip_enable_irq(gc, hwirq); 1292 1293 reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG); 1294 if (!reg) 1295 return; 1296 1297 guard(raw_spinlock_irqsave)(&byt_lock); 1298 1299 value = readl(reg); 1300 1301 switch (irqd_get_trigger_type(d)) { 1302 case IRQ_TYPE_LEVEL_HIGH: 1303 value |= BYT_TRIG_LVL; 1304 fallthrough; 1305 case IRQ_TYPE_EDGE_RISING: 1306 value |= BYT_TRIG_POS; 1307 break; 1308 case IRQ_TYPE_LEVEL_LOW: 1309 value |= BYT_TRIG_LVL; 1310 fallthrough; 1311 case IRQ_TYPE_EDGE_FALLING: 1312 value |= BYT_TRIG_NEG; 1313 break; 1314 case IRQ_TYPE_EDGE_BOTH: 1315 value |= (BYT_TRIG_NEG | BYT_TRIG_POS); 1316 break; 1317 } 1318 1319 writel(value, reg); 1320 } 1321 1322 static int byt_irq_type(struct irq_data *d, unsigned int type) 1323 { 1324 struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1325 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1326 void __iomem *reg; 1327 u32 value; 1328 1329 reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG); 1330 if (!reg) 1331 return -EINVAL; 1332 1333 guard(raw_spinlock_irqsave)(&byt_lock); 1334 1335 value = readl(reg); 1336 1337 WARN(value & BYT_DIRECT_IRQ_EN, 1338 "Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing"); 1339 1340 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 1341 * are used to indicate high and low level triggering 1342 */ 1343 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 1344 BYT_TRIG_LVL); 1345 /* Enable glitch filtering */ 1346 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK | 1347 BYT_GLITCH_F_FAST_CLK; 1348 1349 writel(value, reg); 1350 1351 if (type & IRQ_TYPE_EDGE_BOTH) 1352 irq_set_handler_locked(d, handle_edge_irq); 1353 else if (type & IRQ_TYPE_LEVEL_MASK) 1354 irq_set_handler_locked(d, handle_level_irq); 1355 1356 return 0; 1357 } 1358 1359 static const struct irq_chip byt_gpio_irq_chip = { 1360 .name = "BYT-GPIO", 1361 .irq_ack = byt_irq_ack, 1362 .irq_mask = byt_irq_mask, 1363 .irq_unmask = byt_irq_unmask, 1364 .irq_set_type = byt_irq_type, 1365 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE, 1366 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1367 }; 1368 1369 static void byt_gpio_irq_handler(struct irq_desc *desc) 1370 { 1371 struct irq_data *data = irq_desc_get_irq_data(desc); 1372 struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc)); 1373 struct irq_chip *chip = irq_data_get_irq_chip(data); 1374 u32 base, pin; 1375 void __iomem *reg; 1376 unsigned long pending; 1377 1378 chained_irq_enter(chip, desc); 1379 1380 /* check from GPIO controller which pin triggered the interrupt */ 1381 for (base = 0; base < vg->chip.ngpio; base += 32) { 1382 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1383 1384 if (!reg) { 1385 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); 1386 continue; 1387 } 1388 1389 scoped_guard(raw_spinlock, &byt_lock) 1390 pending = readl(reg); 1391 for_each_set_bit(pin, &pending, 32) 1392 generic_handle_domain_irq(vg->chip.irq.domain, base + pin); 1393 } 1394 1395 chained_irq_exit(chip, desc); 1396 } 1397 1398 static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0) 1399 { 1400 int direct_irq, ioapic_direct_irq_base; 1401 u8 *match, direct_irq_mux[16]; 1402 u32 trig; 1403 1404 memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG, 1405 sizeof(direct_irq_mux)); 1406 match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux)); 1407 if (!match) { 1408 dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin); 1409 return false; 1410 } 1411 1412 direct_irq = match - direct_irq_mux; 1413 /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */ 1414 ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67; 1415 dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin, 1416 direct_irq, direct_irq + ioapic_direct_irq_base); 1417 1418 /* 1419 * Testing has shown that the way direct IRQs work is that the combination of the 1420 * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ 1421 * trigger block, which normally sets the status flag in the IRQ status reg at 1422 * 0x800, to one of the IO-APIC pins according to the mux registers. 1423 * 1424 * This means that: 1425 * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block 1426 * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly 1427 * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, 1428 * selecting edge mode operation then on the first edge the IO-APIC pin goes 1429 * high, but since no write-to-clear write will be done to the IRQ status reg 1430 * at 0x800, the detected edge condition will never get cleared. 1431 */ 1432 trig = conf0 & BYT_TRIG_MASK; 1433 if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) && 1434 trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) { 1435 dev_warn(vg->dev, 1436 FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n", 1437 pin, conf0); 1438 return false; 1439 } 1440 1441 return true; 1442 } 1443 1444 static void byt_init_irq_valid_mask(struct gpio_chip *chip, 1445 unsigned long *valid_mask, 1446 unsigned int ngpios) 1447 { 1448 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1449 void __iomem *reg; 1450 u32 value; 1451 int i; 1452 1453 /* 1454 * Clear interrupt triggers for all pins that are GPIOs and 1455 * do not use direct IRQ mode. This will prevent spurious 1456 * interrupts from misconfigured pins. 1457 */ 1458 for (i = 0; i < vg->soc->npins; i++) { 1459 unsigned int pin = vg->soc->pins[i].number; 1460 1461 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1462 if (!reg) { 1463 dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i); 1464 continue; 1465 } 1466 1467 value = readl(reg); 1468 if (value & BYT_DIRECT_IRQ_EN) { 1469 if (byt_direct_irq_sanity_check(vg, i, value)) { 1470 clear_bit(i, valid_mask); 1471 } else { 1472 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | 1473 BYT_TRIG_NEG | BYT_TRIG_LVL); 1474 writel(value, reg); 1475 } 1476 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { 1477 byt_gpio_clear_triggering(vg, i); 1478 dev_dbg(vg->dev, "disabling GPIO %d\n", i); 1479 } 1480 } 1481 } 1482 1483 static int byt_gpio_irq_init_hw(struct gpio_chip *chip) 1484 { 1485 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1486 void __iomem *reg; 1487 u32 base, value; 1488 1489 /* clear interrupt status trigger registers */ 1490 for (base = 0; base < vg->soc->npins; base += 32) { 1491 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1492 1493 if (!reg) { 1494 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); 1495 continue; 1496 } 1497 1498 writel(0xffffffff, reg); 1499 /* make sure trigger bits are cleared, if not then a pin 1500 might be misconfigured in bios */ 1501 value = readl(reg); 1502 if (value) 1503 dev_err(vg->dev, 1504 "GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n", 1505 base / 32, value); 1506 } 1507 1508 return 0; 1509 } 1510 1511 static int byt_gpio_probe(struct intel_pinctrl *vg) 1512 { 1513 struct platform_device *pdev = to_platform_device(vg->dev); 1514 struct gpio_chip *gc; 1515 int irq, ret; 1516 1517 /* Set up gpio chip */ 1518 vg->chip = byt_gpio_chip; 1519 gc = &vg->chip; 1520 gc->label = dev_name(vg->dev); 1521 gc->base = -1; 1522 gc->can_sleep = false; 1523 gc->add_pin_ranges = intel_gpio_add_pin_ranges; 1524 gc->parent = vg->dev; 1525 gc->ngpio = vg->soc->npins; 1526 1527 #ifdef CONFIG_PM_SLEEP 1528 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads), 1529 GFP_KERNEL); 1530 if (!vg->context.pads) 1531 return -ENOMEM; 1532 #endif 1533 1534 /* set up interrupts */ 1535 irq = platform_get_irq_optional(pdev, 0); 1536 if (irq > 0) { 1537 struct gpio_irq_chip *girq; 1538 1539 girq = &gc->irq; 1540 gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip); 1541 girq->init_hw = byt_gpio_irq_init_hw; 1542 girq->init_valid_mask = byt_init_irq_valid_mask; 1543 girq->parent_handler = byt_gpio_irq_handler; 1544 girq->num_parents = 1; 1545 girq->parents = devm_kcalloc(vg->dev, girq->num_parents, 1546 sizeof(*girq->parents), GFP_KERNEL); 1547 if (!girq->parents) 1548 return -ENOMEM; 1549 girq->parents[0] = irq; 1550 girq->default_type = IRQ_TYPE_NONE; 1551 girq->handler = handle_bad_irq; 1552 } 1553 1554 ret = devm_gpiochip_add_data(vg->dev, gc, vg); 1555 if (ret) 1556 return dev_err_probe(vg->dev, ret, "failed to register gpiochip\n"); 1557 1558 return 0; 1559 } 1560 1561 static int byt_set_soc_data(struct intel_pinctrl *vg, 1562 const struct intel_pinctrl_soc_data *soc) 1563 { 1564 struct platform_device *pdev = to_platform_device(vg->dev); 1565 int i; 1566 1567 vg->soc = soc; 1568 1569 vg->ncommunities = vg->soc->ncommunities; 1570 vg->communities = devm_kmemdup_array(vg->dev, vg->soc->communities, vg->ncommunities, 1571 sizeof(*vg->soc->communities), GFP_KERNEL); 1572 if (!vg->communities) 1573 return -ENOMEM; 1574 1575 for (i = 0; i < vg->soc->ncommunities; i++) { 1576 struct intel_community *comm = vg->communities + i; 1577 1578 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0); 1579 if (IS_ERR(comm->pad_regs)) 1580 return PTR_ERR(comm->pad_regs); 1581 } 1582 1583 return 0; 1584 } 1585 1586 static const struct acpi_device_id byt_gpio_acpi_match[] = { 1587 { "INT33B2", (kernel_ulong_t)byt_soc_data }, 1588 { "INT33FC", (kernel_ulong_t)byt_soc_data }, 1589 { } 1590 }; 1591 1592 static int byt_pinctrl_probe(struct platform_device *pdev) 1593 { 1594 const struct intel_pinctrl_soc_data *soc_data; 1595 struct device *dev = &pdev->dev; 1596 struct intel_pinctrl *vg; 1597 int ret; 1598 1599 soc_data = intel_pinctrl_get_soc_data(pdev); 1600 if (IS_ERR(soc_data)) 1601 return PTR_ERR(soc_data); 1602 1603 vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL); 1604 if (!vg) 1605 return -ENOMEM; 1606 1607 vg->dev = dev; 1608 ret = byt_set_soc_data(vg, soc_data); 1609 if (ret) 1610 return dev_err_probe(dev, ret, "failed to set soc data\n"); 1611 1612 vg->pctldesc = byt_pinctrl_desc; 1613 vg->pctldesc.name = dev_name(dev); 1614 vg->pctldesc.pins = vg->soc->pins; 1615 vg->pctldesc.npins = vg->soc->npins; 1616 1617 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg); 1618 if (IS_ERR(vg->pctldev)) 1619 return PTR_ERR(vg->pctldev); 1620 1621 ret = byt_gpio_probe(vg); 1622 if (ret) 1623 return ret; 1624 1625 platform_set_drvdata(pdev, vg); 1626 1627 return 0; 1628 } 1629 1630 static int byt_gpio_suspend(struct device *dev) 1631 { 1632 struct intel_pinctrl *vg = dev_get_drvdata(dev); 1633 int i; 1634 1635 guard(raw_spinlock_irqsave)(&byt_lock); 1636 1637 for (i = 0; i < vg->soc->npins; i++) { 1638 void __iomem *reg; 1639 u32 value; 1640 unsigned int pin = vg->soc->pins[i].number; 1641 1642 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1643 if (!reg) { 1644 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); 1645 continue; 1646 } 1647 value = readl(reg) & BYT_CONF0_RESTORE_MASK; 1648 vg->context.pads[i].conf0 = value; 1649 1650 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1651 if (!reg) { 1652 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); 1653 continue; 1654 } 1655 value = readl(reg) & BYT_VAL_RESTORE_MASK; 1656 vg->context.pads[i].val = value; 1657 } 1658 1659 return 0; 1660 } 1661 1662 static int byt_gpio_resume(struct device *dev) 1663 { 1664 struct intel_pinctrl *vg = dev_get_drvdata(dev); 1665 int i; 1666 1667 guard(raw_spinlock_irqsave)(&byt_lock); 1668 1669 for (i = 0; i < vg->soc->npins; i++) { 1670 void __iomem *reg; 1671 u32 value; 1672 unsigned int pin = vg->soc->pins[i].number; 1673 1674 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1675 if (!reg) { 1676 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); 1677 continue; 1678 } 1679 value = readl(reg); 1680 if ((value & BYT_CONF0_RESTORE_MASK) != 1681 vg->context.pads[i].conf0) { 1682 value &= ~BYT_CONF0_RESTORE_MASK; 1683 value |= vg->context.pads[i].conf0; 1684 writel(value, reg); 1685 dev_info(dev, "restored pin %d CONF0 %#08x", i, value); 1686 } 1687 1688 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1689 if (!reg) { 1690 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); 1691 continue; 1692 } 1693 value = readl(reg); 1694 if ((value & BYT_VAL_RESTORE_MASK) != 1695 vg->context.pads[i].val) { 1696 u32 v; 1697 1698 v = value & ~BYT_VAL_RESTORE_MASK; 1699 v |= vg->context.pads[i].val; 1700 if (v != value) { 1701 writel(v, reg); 1702 dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v); 1703 } 1704 } 1705 } 1706 1707 return 0; 1708 } 1709 1710 static const struct dev_pm_ops byt_gpio_pm_ops = { 1711 LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) 1712 }; 1713 1714 static struct platform_driver byt_gpio_driver = { 1715 .probe = byt_pinctrl_probe, 1716 .driver = { 1717 .name = "byt_gpio", 1718 .pm = pm_sleep_ptr(&byt_gpio_pm_ops), 1719 .acpi_match_table = byt_gpio_acpi_match, 1720 .suppress_bind_attrs = true, 1721 }, 1722 }; 1723 1724 static int __init byt_gpio_init(void) 1725 { 1726 return platform_driver_register(&byt_gpio_driver); 1727 } 1728 subsys_initcall(byt_gpio_init); 1729 1730 MODULE_IMPORT_NS("PINCTRL_INTEL"); 1731