xref: /linux/drivers/pinctrl/intel/pinctrl-baytrail.c (revision ad30469a841b50dbb541df4d6971d891f703c297)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Pinctrl GPIO driver for Intel Baytrail
4  *
5  * Copyright (c) 2012-2013, Intel Corporation
6  * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7  */
8 
9 #include <linux/acpi.h>
10 #include <linux/array_size.h>
11 #include <linux/bitops.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm.h>
20 #include <linux/property.h>
21 #include <linux/seq_file.h>
22 #include <linux/string_helpers.h>
23 
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinconf-generic.h>
28 
29 #include "pinctrl-intel.h"
30 
31 /* memory mapped register offsets */
32 #define BYT_CONF0_REG		0x000
33 #define BYT_CONF1_REG		0x004
34 #define BYT_VAL_REG		0x008
35 #define BYT_DFT_REG		0x00c
36 #define BYT_INT_STAT_REG	0x800
37 #define BYT_DIRECT_IRQ_REG	0x980
38 #define BYT_DEBOUNCE_REG	0x9d0
39 
40 /* BYT_CONF0_REG register bits */
41 #define BYT_IODEN		BIT(31)
42 #define BYT_DIRECT_IRQ_EN	BIT(27)
43 #define BYT_TRIG_MASK		GENMASK(26, 24)
44 #define BYT_TRIG_NEG		BIT(26)
45 #define BYT_TRIG_POS		BIT(25)
46 #define BYT_TRIG_LVL		BIT(24)
47 #define BYT_DEBOUNCE_EN		BIT(20)
48 #define BYT_GLITCH_FILTER_EN	BIT(19)
49 #define BYT_GLITCH_F_SLOW_CLK	BIT(17)
50 #define BYT_GLITCH_F_FAST_CLK	BIT(16)
51 #define BYT_PULL_STR_SHIFT	9
52 #define BYT_PULL_STR_MASK	GENMASK(10, 9)
53 #define BYT_PULL_STR_2K		(0 << BYT_PULL_STR_SHIFT)
54 #define BYT_PULL_STR_10K	(1 << BYT_PULL_STR_SHIFT)
55 #define BYT_PULL_STR_20K	(2 << BYT_PULL_STR_SHIFT)
56 #define BYT_PULL_STR_40K	(3 << BYT_PULL_STR_SHIFT)
57 #define BYT_PULL_ASSIGN_MASK	GENMASK(8, 7)
58 #define BYT_PULL_ASSIGN_DOWN	BIT(8)
59 #define BYT_PULL_ASSIGN_UP	BIT(7)
60 #define BYT_PIN_MUX		GENMASK(2, 0)
61 
62 /* BYT_VAL_REG register bits */
63 #define BYT_DIR_MASK		GENMASK(2, 1)
64 #define BYT_INPUT_EN		BIT(2)  /* 0: input enabled (active low)*/
65 #define BYT_OUTPUT_EN		BIT(1)  /* 0: output enabled (active low)*/
66 #define BYT_LEVEL		BIT(0)
67 
68 #define BYT_CONF0_RESTORE_MASK	(BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
69 #define BYT_VAL_RESTORE_MASK	(BYT_DIR_MASK | BYT_LEVEL)
70 
71 /* BYT_DEBOUNCE_REG bits */
72 #define BYT_DEBOUNCE_PULSE_MASK		GENMASK(2, 0)
73 #define BYT_DEBOUNCE_PULSE_375US	1
74 #define BYT_DEBOUNCE_PULSE_750US	2
75 #define BYT_DEBOUNCE_PULSE_1500US	3
76 #define BYT_DEBOUNCE_PULSE_3MS		4
77 #define BYT_DEBOUNCE_PULSE_6MS		5
78 #define BYT_DEBOUNCE_PULSE_12MS		6
79 #define BYT_DEBOUNCE_PULSE_24MS		7
80 
81 #define BYT_NGPIO_SCORE		102
82 #define BYT_NGPIO_NCORE		28
83 #define BYT_NGPIO_SUS		44
84 
85 #define BYT_SCORE_ACPI_UID	"1"
86 #define BYT_NCORE_ACPI_UID	"2"
87 #define BYT_SUS_ACPI_UID	"3"
88 
89 /*
90  * This is the function value most pins have for GPIO muxing. If the value
91  * differs from the default one, it must be explicitly mentioned. Otherwise, the
92  * pin control implementation will set the muxing value to default GPIO if it
93  * does not find a match for the requested function.
94  */
95 #define BYT_DEFAULT_GPIO_MUX	0
96 #define BYT_ALTER_GPIO_MUX	1
97 
98 struct intel_pad_context {
99 	u32 conf0;
100 	u32 val;
101 };
102 
103 #define COMMUNITY(p, n, map)		\
104 	{				\
105 		.pin_base	= (p),	\
106 		.npins		= (n),	\
107 		.pad_map	= (map),\
108 	}
109 
110 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
111 static const struct pinctrl_pin_desc byt_score_pins[] = {
112 	PINCTRL_PIN(0, "SATA_GP0"),
113 	PINCTRL_PIN(1, "SATA_GP1"),
114 	PINCTRL_PIN(2, "SATA_LED#"),
115 	PINCTRL_PIN(3, "PCIE_CLKREQ0"),
116 	PINCTRL_PIN(4, "PCIE_CLKREQ1"),
117 	PINCTRL_PIN(5, "PCIE_CLKREQ2"),
118 	PINCTRL_PIN(6, "PCIE_CLKREQ3"),
119 	PINCTRL_PIN(7, "SD3_WP"),
120 	PINCTRL_PIN(8, "HDA_RST"),
121 	PINCTRL_PIN(9, "HDA_SYNC"),
122 	PINCTRL_PIN(10, "HDA_CLK"),
123 	PINCTRL_PIN(11, "HDA_SDO"),
124 	PINCTRL_PIN(12, "HDA_SDI0"),
125 	PINCTRL_PIN(13, "HDA_SDI1"),
126 	PINCTRL_PIN(14, "GPIO_S0_SC14"),
127 	PINCTRL_PIN(15, "GPIO_S0_SC15"),
128 	PINCTRL_PIN(16, "MMC1_CLK"),
129 	PINCTRL_PIN(17, "MMC1_D0"),
130 	PINCTRL_PIN(18, "MMC1_D1"),
131 	PINCTRL_PIN(19, "MMC1_D2"),
132 	PINCTRL_PIN(20, "MMC1_D3"),
133 	PINCTRL_PIN(21, "MMC1_D4"),
134 	PINCTRL_PIN(22, "MMC1_D5"),
135 	PINCTRL_PIN(23, "MMC1_D6"),
136 	PINCTRL_PIN(24, "MMC1_D7"),
137 	PINCTRL_PIN(25, "MMC1_CMD"),
138 	PINCTRL_PIN(26, "MMC1_RST"),
139 	PINCTRL_PIN(27, "SD2_CLK"),
140 	PINCTRL_PIN(28, "SD2_D0"),
141 	PINCTRL_PIN(29, "SD2_D1"),
142 	PINCTRL_PIN(30, "SD2_D2"),
143 	PINCTRL_PIN(31, "SD2_D3_CD"),
144 	PINCTRL_PIN(32, "SD2_CMD"),
145 	PINCTRL_PIN(33, "SD3_CLK"),
146 	PINCTRL_PIN(34, "SD3_D0"),
147 	PINCTRL_PIN(35, "SD3_D1"),
148 	PINCTRL_PIN(36, "SD3_D2"),
149 	PINCTRL_PIN(37, "SD3_D3"),
150 	PINCTRL_PIN(38, "SD3_CD"),
151 	PINCTRL_PIN(39, "SD3_CMD"),
152 	PINCTRL_PIN(40, "SD3_1P8EN"),
153 	PINCTRL_PIN(41, "SD3_PWREN#"),
154 	PINCTRL_PIN(42, "ILB_LPC_AD0"),
155 	PINCTRL_PIN(43, "ILB_LPC_AD1"),
156 	PINCTRL_PIN(44, "ILB_LPC_AD2"),
157 	PINCTRL_PIN(45, "ILB_LPC_AD3"),
158 	PINCTRL_PIN(46, "ILB_LPC_FRAME"),
159 	PINCTRL_PIN(47, "ILB_LPC_CLK0"),
160 	PINCTRL_PIN(48, "ILB_LPC_CLK1"),
161 	PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
162 	PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
163 	PINCTRL_PIN(51, "PCU_SMB_DATA"),
164 	PINCTRL_PIN(52, "PCU_SMB_CLK"),
165 	PINCTRL_PIN(53, "PCU_SMB_ALERT"),
166 	PINCTRL_PIN(54, "ILB_8254_SPKR"),
167 	PINCTRL_PIN(55, "GPIO_S0_SC55"),
168 	PINCTRL_PIN(56, "GPIO_S0_SC56"),
169 	PINCTRL_PIN(57, "GPIO_S0_SC57"),
170 	PINCTRL_PIN(58, "GPIO_S0_SC58"),
171 	PINCTRL_PIN(59, "GPIO_S0_SC59"),
172 	PINCTRL_PIN(60, "GPIO_S0_SC60"),
173 	PINCTRL_PIN(61, "GPIO_S0_SC61"),
174 	PINCTRL_PIN(62, "LPE_I2S2_CLK"),
175 	PINCTRL_PIN(63, "LPE_I2S2_FRM"),
176 	PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
177 	PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
178 	PINCTRL_PIN(66, "SIO_SPI_CS"),
179 	PINCTRL_PIN(67, "SIO_SPI_MISO"),
180 	PINCTRL_PIN(68, "SIO_SPI_MOSI"),
181 	PINCTRL_PIN(69, "SIO_SPI_CLK"),
182 	PINCTRL_PIN(70, "SIO_UART1_RXD"),
183 	PINCTRL_PIN(71, "SIO_UART1_TXD"),
184 	PINCTRL_PIN(72, "SIO_UART1_RTS"),
185 	PINCTRL_PIN(73, "SIO_UART1_CTS"),
186 	PINCTRL_PIN(74, "SIO_UART2_RXD"),
187 	PINCTRL_PIN(75, "SIO_UART2_TXD"),
188 	PINCTRL_PIN(76, "SIO_UART2_RTS"),
189 	PINCTRL_PIN(77, "SIO_UART2_CTS"),
190 	PINCTRL_PIN(78, "SIO_I2C0_DATA"),
191 	PINCTRL_PIN(79, "SIO_I2C0_CLK"),
192 	PINCTRL_PIN(80, "SIO_I2C1_DATA"),
193 	PINCTRL_PIN(81, "SIO_I2C1_CLK"),
194 	PINCTRL_PIN(82, "SIO_I2C2_DATA"),
195 	PINCTRL_PIN(83, "SIO_I2C2_CLK"),
196 	PINCTRL_PIN(84, "SIO_I2C3_DATA"),
197 	PINCTRL_PIN(85, "SIO_I2C3_CLK"),
198 	PINCTRL_PIN(86, "SIO_I2C4_DATA"),
199 	PINCTRL_PIN(87, "SIO_I2C4_CLK"),
200 	PINCTRL_PIN(88, "SIO_I2C5_DATA"),
201 	PINCTRL_PIN(89, "SIO_I2C5_CLK"),
202 	PINCTRL_PIN(90, "SIO_I2C6_DATA"),
203 	PINCTRL_PIN(91, "SIO_I2C6_CLK"),
204 	PINCTRL_PIN(92, "GPIO_S0_SC92"),
205 	PINCTRL_PIN(93, "GPIO_S0_SC93"),
206 	PINCTRL_PIN(94, "SIO_PWM0"),
207 	PINCTRL_PIN(95, "SIO_PWM1"),
208 	PINCTRL_PIN(96, "PMC_PLT_CLK0"),
209 	PINCTRL_PIN(97, "PMC_PLT_CLK1"),
210 	PINCTRL_PIN(98, "PMC_PLT_CLK2"),
211 	PINCTRL_PIN(99, "PMC_PLT_CLK3"),
212 	PINCTRL_PIN(100, "PMC_PLT_CLK4"),
213 	PINCTRL_PIN(101, "PMC_PLT_CLK5"),
214 };
215 
216 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
217 	85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
218 	36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
219 	54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
220 	52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
221 	95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
222 	86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
223 	80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
224 	2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
225 	31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
226 	24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
227 	97, 100,
228 };
229 
230 /* SCORE groups */
231 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
232 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
233 
234 static const unsigned int byt_score_pwm0_pins[] = { 94 };
235 static const unsigned int byt_score_pwm1_pins[] = { 95 };
236 
237 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
238 
239 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
240 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
241 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
242 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
243 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
244 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
245 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
246 
247 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
248 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
249 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
250 
251 static const unsigned int byt_score_sdcard_pins[] = {
252 	7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
253 };
254 static const unsigned int byt_score_sdcard_mux_values[] = {
255 	2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
256 };
257 
258 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
259 
260 static const unsigned int byt_score_emmc_pins[] = {
261 	16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
262 };
263 
264 static const unsigned int byt_score_ilb_lpc_pins[] = {
265 	42, 43, 44, 45, 46, 47, 48, 49, 50,
266 };
267 
268 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
269 
270 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
271 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
272 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
273 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
274 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
275 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
276 
277 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
278 
279 static const struct intel_pingroup byt_score_groups[] = {
280 	PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
281 	PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
282 	PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
283 	PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
284 	PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
285 	PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
286 	PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
287 	PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
288 	PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
289 	PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
290 	PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
291 	PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
292 	PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
293 	PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
294 	PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
295 	PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
296 	PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
297 	PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
298 	PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
299 	PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
300 	PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
301 	PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
302 	PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
303 	PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
304 	PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
305 	PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
306 	PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
307 };
308 
309 static const char * const byt_score_uart_groups[] = {
310 	"uart1_grp", "uart2_grp",
311 };
312 static const char * const byt_score_pwm_groups[] = {
313 	"pwm0_grp", "pwm1_grp",
314 };
315 static const char * const byt_score_ssp_groups[] = {
316 	"ssp0_grp", "ssp1_grp", "ssp2_grp",
317 };
318 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
319 static const char * const byt_score_i2c_groups[] = {
320 	"i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
321 	"i2c6_grp",
322 };
323 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
324 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
325 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
326 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
327 static const char * const byt_score_sata_groups[] = { "sata_grp" };
328 static const char * const byt_score_plt_clk_groups[] = {
329 	"plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
330 	"plt_clk4_grp", "plt_clk5_grp",
331 };
332 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
333 static const char * const byt_score_gpio_groups[] = {
334 	"uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
335 	"ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
336 	"i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
337 	"sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
338 	"plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
339 	"plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
340 };
341 
342 static const struct intel_function byt_score_functions[] = {
343 	FUNCTION("uart", byt_score_uart_groups),
344 	FUNCTION("pwm", byt_score_pwm_groups),
345 	FUNCTION("ssp", byt_score_ssp_groups),
346 	FUNCTION("spi", byt_score_spi_groups),
347 	FUNCTION("i2c", byt_score_i2c_groups),
348 	FUNCTION("sdcard", byt_score_sdcard_groups),
349 	FUNCTION("sdio", byt_score_sdio_groups),
350 	FUNCTION("emmc", byt_score_emmc_groups),
351 	FUNCTION("lpc", byt_score_lpc_groups),
352 	FUNCTION("sata", byt_score_sata_groups),
353 	FUNCTION("plt_clk", byt_score_plt_clk_groups),
354 	FUNCTION("smbus", byt_score_smbus_groups),
355 	FUNCTION("gpio", byt_score_gpio_groups),
356 };
357 
358 static const struct intel_community byt_score_communities[] = {
359 	COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
360 };
361 
362 static const struct intel_pinctrl_soc_data byt_score_soc_data = {
363 	.uid		= BYT_SCORE_ACPI_UID,
364 	.pins		= byt_score_pins,
365 	.npins		= ARRAY_SIZE(byt_score_pins),
366 	.groups		= byt_score_groups,
367 	.ngroups	= ARRAY_SIZE(byt_score_groups),
368 	.functions	= byt_score_functions,
369 	.nfunctions	= ARRAY_SIZE(byt_score_functions),
370 	.communities	= byt_score_communities,
371 	.ncommunities	= ARRAY_SIZE(byt_score_communities),
372 };
373 
374 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>]  */
375 static const struct pinctrl_pin_desc byt_sus_pins[] = {
376 	PINCTRL_PIN(0, "GPIO_S50"),
377 	PINCTRL_PIN(1, "GPIO_S51"),
378 	PINCTRL_PIN(2, "GPIO_S52"),
379 	PINCTRL_PIN(3, "GPIO_S53"),
380 	PINCTRL_PIN(4, "GPIO_S54"),
381 	PINCTRL_PIN(5, "GPIO_S55"),
382 	PINCTRL_PIN(6, "GPIO_S56"),
383 	PINCTRL_PIN(7, "GPIO_S57"),
384 	PINCTRL_PIN(8, "GPIO_S58"),
385 	PINCTRL_PIN(9, "GPIO_S59"),
386 	PINCTRL_PIN(10, "GPIO_S510"),
387 	PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
388 	PINCTRL_PIN(12, "PMC_SUSCLK0"),
389 	PINCTRL_PIN(13, "GPIO_S513"),
390 	PINCTRL_PIN(14, "USB_ULPI_RST"),
391 	PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
392 	PINCTRL_PIN(16, "PMC_PWRBTN"),
393 	PINCTRL_PIN(17, "GPIO_S517"),
394 	PINCTRL_PIN(18, "PMC_SUS_STAT"),
395 	PINCTRL_PIN(19, "USB_OC0"),
396 	PINCTRL_PIN(20, "USB_OC1"),
397 	PINCTRL_PIN(21, "PCU_SPI_CS1"),
398 	PINCTRL_PIN(22, "GPIO_S522"),
399 	PINCTRL_PIN(23, "GPIO_S523"),
400 	PINCTRL_PIN(24, "GPIO_S524"),
401 	PINCTRL_PIN(25, "GPIO_S525"),
402 	PINCTRL_PIN(26, "GPIO_S526"),
403 	PINCTRL_PIN(27, "GPIO_S527"),
404 	PINCTRL_PIN(28, "GPIO_S528"),
405 	PINCTRL_PIN(29, "GPIO_S529"),
406 	PINCTRL_PIN(30, "GPIO_S530"),
407 	PINCTRL_PIN(31, "USB_ULPI_CLK"),
408 	PINCTRL_PIN(32, "USB_ULPI_DATA0"),
409 	PINCTRL_PIN(33, "USB_ULPI_DATA1"),
410 	PINCTRL_PIN(34, "USB_ULPI_DATA2"),
411 	PINCTRL_PIN(35, "USB_ULPI_DATA3"),
412 	PINCTRL_PIN(36, "USB_ULPI_DATA4"),
413 	PINCTRL_PIN(37, "USB_ULPI_DATA5"),
414 	PINCTRL_PIN(38, "USB_ULPI_DATA6"),
415 	PINCTRL_PIN(39, "USB_ULPI_DATA7"),
416 	PINCTRL_PIN(40, "USB_ULPI_DIR"),
417 	PINCTRL_PIN(41, "USB_ULPI_NXT"),
418 	PINCTRL_PIN(42, "USB_ULPI_STP"),
419 	PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
420 };
421 
422 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
423 	29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
424 	18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
425 	0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
426 	26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
427 	52, 53, 59, 40,
428 };
429 
430 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
431 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
432 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
433 
434 static const unsigned int byt_sus_usb_ulpi_pins[] = {
435 	14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
436 };
437 static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
438 	2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
439 };
440 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
441 	1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
442 };
443 
444 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
445 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
446 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
447 
448 static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 };
449 static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 };
450 
451 static const struct intel_pingroup byt_sus_groups[] = {
452 	PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
453 	PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
454 	PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
455 	PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
456 	PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
457 	PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
458 	PIN_GROUP("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1),
459 	PIN_GROUP("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1),
460 };
461 
462 static const char * const byt_sus_usb_groups[] = {
463 	"usb_oc_grp", "usb_ulpi_grp",
464 };
465 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
466 static const char * const byt_sus_pmu_clk_groups[] = {
467 	"pmu_clk1_grp", "pmu_clk2_grp",
468 };
469 static const char * const byt_sus_gpio_groups[] = {
470 	"usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
471 	"pmu_clk1_grp", "pmu_clk2_grp",
472 };
473 
474 static const struct intel_function byt_sus_functions[] = {
475 	FUNCTION("usb", byt_sus_usb_groups),
476 	FUNCTION("spi", byt_sus_spi_groups),
477 	FUNCTION("gpio", byt_sus_gpio_groups),
478 	FUNCTION("pmu_clk", byt_sus_pmu_clk_groups),
479 };
480 
481 static const struct intel_community byt_sus_communities[] = {
482 	COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
483 };
484 
485 static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
486 	.uid		= BYT_SUS_ACPI_UID,
487 	.pins		= byt_sus_pins,
488 	.npins		= ARRAY_SIZE(byt_sus_pins),
489 	.groups		= byt_sus_groups,
490 	.ngroups	= ARRAY_SIZE(byt_sus_groups),
491 	.functions	= byt_sus_functions,
492 	.nfunctions	= ARRAY_SIZE(byt_sus_functions),
493 	.communities	= byt_sus_communities,
494 	.ncommunities	= ARRAY_SIZE(byt_sus_communities),
495 };
496 
497 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
498 	PINCTRL_PIN(0, "HV_DDI0_HPD"),
499 	PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"),
500 	PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"),
501 	PINCTRL_PIN(3, "PANEL0_VDDEN"),
502 	PINCTRL_PIN(4, "PANEL0_BKLTEN"),
503 	PINCTRL_PIN(5, "PANEL0_BKLTCTL"),
504 	PINCTRL_PIN(6, "HV_DDI1_HPD"),
505 	PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"),
506 	PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"),
507 	PINCTRL_PIN(9, "PANEL1_VDDEN"),
508 	PINCTRL_PIN(10, "PANEL1_BKLTEN"),
509 	PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
510 	PINCTRL_PIN(12, "GP_INTD_DSI_TE1"),
511 	PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"),
512 	PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"),
513 	PINCTRL_PIN(15, "GP_CAMERASB00"),
514 	PINCTRL_PIN(16, "GP_CAMERASB01"),
515 	PINCTRL_PIN(17, "GP_CAMERASB02"),
516 	PINCTRL_PIN(18, "GP_CAMERASB03"),
517 	PINCTRL_PIN(19, "GP_CAMERASB04"),
518 	PINCTRL_PIN(20, "GP_CAMERASB05"),
519 	PINCTRL_PIN(21, "GP_CAMERASB06"),
520 	PINCTRL_PIN(22, "GP_CAMERASB07"),
521 	PINCTRL_PIN(23, "GP_CAMERASB08"),
522 	PINCTRL_PIN(24, "GP_CAMERASB09"),
523 	PINCTRL_PIN(25, "GP_CAMERASB10"),
524 	PINCTRL_PIN(26, "GP_CAMERASB11"),
525 	PINCTRL_PIN(27, "GP_INTD_DSI_TE2"),
526 };
527 
528 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
529 	19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
530 	14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
531 	3, 6, 10, 13, 2, 5, 9, 7,
532 };
533 
534 static const struct intel_community byt_ncore_communities[] = {
535 	COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
536 };
537 
538 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
539 	.uid		= BYT_NCORE_ACPI_UID,
540 	.pins		= byt_ncore_pins,
541 	.npins		= ARRAY_SIZE(byt_ncore_pins),
542 	.communities	= byt_ncore_communities,
543 	.ncommunities	= ARRAY_SIZE(byt_ncore_communities),
544 };
545 
546 static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
547 	&byt_score_soc_data,
548 	&byt_sus_soc_data,
549 	&byt_ncore_soc_data,
550 	NULL
551 };
552 
553 static DEFINE_RAW_SPINLOCK(byt_lock);
554 
555 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
556 				  int reg)
557 {
558 	struct intel_community *comm = intel_get_community(vg, offset);
559 	u32 reg_offset;
560 
561 	if (!comm)
562 		return NULL;
563 
564 	offset -= comm->pin_base;
565 	switch (reg) {
566 	case BYT_INT_STAT_REG:
567 		reg_offset = (offset / 32) * 4;
568 		break;
569 	case BYT_DEBOUNCE_REG:
570 		reg_offset = 0;
571 		break;
572 	default:
573 		reg_offset = comm->pad_map[offset] * 16;
574 		break;
575 	}
576 
577 	return comm->pad_regs + reg_offset + reg;
578 }
579 
580 static const struct pinctrl_ops byt_pinctrl_ops = {
581 	.get_groups_count	= intel_get_groups_count,
582 	.get_group_name		= intel_get_group_name,
583 	.get_group_pins		= intel_get_group_pins,
584 };
585 
586 static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
587 				     const struct intel_pingroup group,
588 				     unsigned int func)
589 {
590 	unsigned long flags;
591 	int i;
592 
593 	raw_spin_lock_irqsave(&byt_lock, flags);
594 
595 	for (i = 0; i < group.grp.npins; i++) {
596 		void __iomem *padcfg0;
597 		u32 value;
598 
599 		padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
600 		if (!padcfg0) {
601 			dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
602 				 group.grp.name, i);
603 			continue;
604 		}
605 
606 		value = readl(padcfg0);
607 		value &= ~BYT_PIN_MUX;
608 		value |= func;
609 		writel(value, padcfg0);
610 	}
611 
612 	raw_spin_unlock_irqrestore(&byt_lock, flags);
613 }
614 
615 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
616 				    const struct intel_pingroup group,
617 				    const unsigned int *func)
618 {
619 	unsigned long flags;
620 	int i;
621 
622 	raw_spin_lock_irqsave(&byt_lock, flags);
623 
624 	for (i = 0; i < group.grp.npins; i++) {
625 		void __iomem *padcfg0;
626 		u32 value;
627 
628 		padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
629 		if (!padcfg0) {
630 			dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
631 				 group.grp.name, i);
632 			continue;
633 		}
634 
635 		value = readl(padcfg0);
636 		value &= ~BYT_PIN_MUX;
637 		value |= func[i];
638 		writel(value, padcfg0);
639 	}
640 
641 	raw_spin_unlock_irqrestore(&byt_lock, flags);
642 }
643 
644 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
645 		       unsigned int group_selector)
646 {
647 	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
648 	const struct intel_function func = vg->soc->functions[func_selector];
649 	const struct intel_pingroup group = vg->soc->groups[group_selector];
650 
651 	if (group.modes)
652 		byt_set_group_mixed_mux(vg, group, group.modes);
653 	else if (!strcmp(func.func.name, "gpio"))
654 		byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
655 	else
656 		byt_set_group_simple_mux(vg, group, group.mode);
657 
658 	return 0;
659 }
660 
661 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
662 {
663 	/* SCORE pin 92-93 */
664 	if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&
665 	    offset >= 92 && offset <= 93)
666 		return BYT_ALTER_GPIO_MUX;
667 
668 	/* SUS pin 11-21 */
669 	if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&
670 	    offset >= 11 && offset <= 21)
671 		return BYT_ALTER_GPIO_MUX;
672 
673 	return BYT_DEFAULT_GPIO_MUX;
674 }
675 
676 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
677 {
678 	void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
679 	unsigned long flags;
680 	u32 value;
681 
682 	raw_spin_lock_irqsave(&byt_lock, flags);
683 	value = readl(reg);
684 
685 	/* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
686 	if (!(value & BYT_DIRECT_IRQ_EN))
687 		value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
688 
689 	writel(value, reg);
690 	raw_spin_unlock_irqrestore(&byt_lock, flags);
691 }
692 
693 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
694 				   struct pinctrl_gpio_range *range,
695 				   unsigned int offset)
696 {
697 	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
698 	void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
699 	u32 value, gpio_mux;
700 	unsigned long flags;
701 
702 	raw_spin_lock_irqsave(&byt_lock, flags);
703 
704 	/*
705 	 * In most cases, func pin mux 000 means GPIO function.
706 	 * But, some pins may have func pin mux 001 represents
707 	 * GPIO function.
708 	 *
709 	 * Because there are devices out there where some pins were not
710 	 * configured correctly we allow changing the mux value from
711 	 * request (but print out warning about that).
712 	 */
713 	value = readl(reg) & BYT_PIN_MUX;
714 	gpio_mux = byt_get_gpio_mux(vg, offset);
715 	if (gpio_mux != value) {
716 		value = readl(reg) & ~BYT_PIN_MUX;
717 		value |= gpio_mux;
718 		writel(value, reg);
719 
720 		dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);
721 	}
722 
723 	raw_spin_unlock_irqrestore(&byt_lock, flags);
724 
725 	return 0;
726 }
727 
728 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
729 				  struct pinctrl_gpio_range *range,
730 				  unsigned int offset)
731 {
732 	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
733 
734 	byt_gpio_clear_triggering(vg, offset);
735 }
736 
737 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
738 				      unsigned int offset)
739 {
740 	void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
741 
742 	/*
743 	 * Before making any direction modifications, do a check if gpio is set
744 	 * for direct IRQ. On Bay Trail, setting GPIO to output does not make
745 	 * sense, so let's at least inform the caller before they shoot
746 	 * themselves in the foot.
747 	 */
748 	if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
749 		dev_info_once(vg->dev,
750 			      "Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n",
751 			      offset);
752 }
753 
754 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
755 				  struct pinctrl_gpio_range *range,
756 				  unsigned int offset,
757 				  bool input)
758 {
759 	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
760 	void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
761 	unsigned long flags;
762 	u32 value;
763 
764 	raw_spin_lock_irqsave(&byt_lock, flags);
765 
766 	value = readl(val_reg);
767 	value &= ~BYT_DIR_MASK;
768 	if (input)
769 		value |= BYT_OUTPUT_EN;
770 	else
771 		byt_gpio_direct_irq_check(vg, offset);
772 
773 	writel(value, val_reg);
774 
775 	raw_spin_unlock_irqrestore(&byt_lock, flags);
776 
777 	return 0;
778 }
779 
780 static const struct pinmux_ops byt_pinmux_ops = {
781 	.get_functions_count	= intel_get_functions_count,
782 	.get_function_name	= intel_get_function_name,
783 	.get_function_groups	= intel_get_function_groups,
784 	.set_mux		= byt_set_mux,
785 	.gpio_request_enable	= byt_gpio_request_enable,
786 	.gpio_disable_free	= byt_gpio_disable_free,
787 	.gpio_set_direction	= byt_gpio_set_direction,
788 };
789 
790 static void byt_get_pull_strength(u32 reg, u16 *strength)
791 {
792 	switch (reg & BYT_PULL_STR_MASK) {
793 	case BYT_PULL_STR_2K:
794 		*strength = 2000;
795 		break;
796 	case BYT_PULL_STR_10K:
797 		*strength = 10000;
798 		break;
799 	case BYT_PULL_STR_20K:
800 		*strength = 20000;
801 		break;
802 	case BYT_PULL_STR_40K:
803 		*strength = 40000;
804 		break;
805 	}
806 }
807 
808 static int byt_set_pull_strength(u32 *reg, u16 strength)
809 {
810 	*reg &= ~BYT_PULL_STR_MASK;
811 
812 	switch (strength) {
813 	case 2000:
814 		*reg |= BYT_PULL_STR_2K;
815 		break;
816 	case 10000:
817 		*reg |= BYT_PULL_STR_10K;
818 		break;
819 	case 20000:
820 		*reg |= BYT_PULL_STR_20K;
821 		break;
822 	case 40000:
823 		*reg |= BYT_PULL_STR_40K;
824 		break;
825 	default:
826 		return -EINVAL;
827 	}
828 
829 	return 0;
830 }
831 
832 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
833 			      unsigned long *config)
834 {
835 	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
836 	enum pin_config_param param = pinconf_to_config_param(*config);
837 	void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
838 	void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
839 	void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
840 	unsigned long flags;
841 	u32 conf, pull, val, debounce;
842 	u16 arg = 0;
843 
844 	raw_spin_lock_irqsave(&byt_lock, flags);
845 	conf = readl(conf_reg);
846 	pull = conf & BYT_PULL_ASSIGN_MASK;
847 	val = readl(val_reg);
848 	raw_spin_unlock_irqrestore(&byt_lock, flags);
849 
850 	switch (param) {
851 	case PIN_CONFIG_BIAS_DISABLE:
852 		if (pull)
853 			return -EINVAL;
854 		break;
855 	case PIN_CONFIG_BIAS_PULL_DOWN:
856 		/* Pull assignment is only applicable in input mode */
857 		if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
858 			return -EINVAL;
859 
860 		byt_get_pull_strength(conf, &arg);
861 
862 		break;
863 	case PIN_CONFIG_BIAS_PULL_UP:
864 		/* Pull assignment is only applicable in input mode */
865 		if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
866 			return -EINVAL;
867 
868 		byt_get_pull_strength(conf, &arg);
869 
870 		break;
871 	case PIN_CONFIG_INPUT_DEBOUNCE:
872 		if (!(conf & BYT_DEBOUNCE_EN))
873 			return -EINVAL;
874 
875 		raw_spin_lock_irqsave(&byt_lock, flags);
876 		debounce = readl(db_reg);
877 		raw_spin_unlock_irqrestore(&byt_lock, flags);
878 
879 		switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
880 		case BYT_DEBOUNCE_PULSE_375US:
881 			arg = 375;
882 			break;
883 		case BYT_DEBOUNCE_PULSE_750US:
884 			arg = 750;
885 			break;
886 		case BYT_DEBOUNCE_PULSE_1500US:
887 			arg = 1500;
888 			break;
889 		case BYT_DEBOUNCE_PULSE_3MS:
890 			arg = 3000;
891 			break;
892 		case BYT_DEBOUNCE_PULSE_6MS:
893 			arg = 6000;
894 			break;
895 		case BYT_DEBOUNCE_PULSE_12MS:
896 			arg = 12000;
897 			break;
898 		case BYT_DEBOUNCE_PULSE_24MS:
899 			arg = 24000;
900 			break;
901 		default:
902 			return -EINVAL;
903 		}
904 
905 		break;
906 	default:
907 		return -ENOTSUPP;
908 	}
909 
910 	*config = pinconf_to_config_packed(param, arg);
911 
912 	return 0;
913 }
914 
915 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
916 			      unsigned int offset,
917 			      unsigned long *configs,
918 			      unsigned int num_configs)
919 {
920 	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
921 	unsigned int param, arg;
922 	void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
923 	void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
924 	void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
925 	u32 conf, val, db_pulse, debounce;
926 	unsigned long flags;
927 	int i, ret = 0;
928 
929 	raw_spin_lock_irqsave(&byt_lock, flags);
930 
931 	conf = readl(conf_reg);
932 	val = readl(val_reg);
933 
934 	for (i = 0; i < num_configs; i++) {
935 		param = pinconf_to_config_param(configs[i]);
936 		arg = pinconf_to_config_argument(configs[i]);
937 
938 		switch (param) {
939 		case PIN_CONFIG_BIAS_DISABLE:
940 			conf &= ~BYT_PULL_ASSIGN_MASK;
941 			break;
942 		case PIN_CONFIG_BIAS_PULL_DOWN:
943 			/* Set default strength value in case none is given */
944 			if (arg == 1)
945 				arg = 2000;
946 
947 			/*
948 			 * Pull assignment is only applicable in input mode. If
949 			 * chip is not in input mode, set it and warn about it.
950 			 */
951 			if (val & BYT_INPUT_EN) {
952 				val &= ~BYT_INPUT_EN;
953 				writel(val, val_reg);
954 				dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
955 			}
956 
957 			conf &= ~BYT_PULL_ASSIGN_MASK;
958 			conf |= BYT_PULL_ASSIGN_DOWN;
959 			ret = byt_set_pull_strength(&conf, arg);
960 
961 			break;
962 		case PIN_CONFIG_BIAS_PULL_UP:
963 			/* Set default strength value in case none is given */
964 			if (arg == 1)
965 				arg = 2000;
966 
967 			/*
968 			 * Pull assignment is only applicable in input mode. If
969 			 * chip is not in input mode, set it and warn about it.
970 			 */
971 			if (val & BYT_INPUT_EN) {
972 				val &= ~BYT_INPUT_EN;
973 				writel(val, val_reg);
974 				dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
975 			}
976 
977 			conf &= ~BYT_PULL_ASSIGN_MASK;
978 			conf |= BYT_PULL_ASSIGN_UP;
979 			ret = byt_set_pull_strength(&conf, arg);
980 
981 			break;
982 		case PIN_CONFIG_INPUT_DEBOUNCE:
983 			if (arg) {
984 				conf |= BYT_DEBOUNCE_EN;
985 			} else {
986 				conf &= ~BYT_DEBOUNCE_EN;
987 
988 				/*
989 				 * No need to update the pulse value.
990 				 * Debounce is going to be disabled.
991 				 */
992 				break;
993 			}
994 
995 			switch (arg) {
996 			case 375:
997 				db_pulse = BYT_DEBOUNCE_PULSE_375US;
998 				break;
999 			case 750:
1000 				db_pulse = BYT_DEBOUNCE_PULSE_750US;
1001 				break;
1002 			case 1500:
1003 				db_pulse = BYT_DEBOUNCE_PULSE_1500US;
1004 				break;
1005 			case 3000:
1006 				db_pulse = BYT_DEBOUNCE_PULSE_3MS;
1007 				break;
1008 			case 6000:
1009 				db_pulse = BYT_DEBOUNCE_PULSE_6MS;
1010 				break;
1011 			case 12000:
1012 				db_pulse = BYT_DEBOUNCE_PULSE_12MS;
1013 				break;
1014 			case 24000:
1015 				db_pulse = BYT_DEBOUNCE_PULSE_24MS;
1016 				break;
1017 			default:
1018 				if (arg)
1019 					ret = -EINVAL;
1020 				break;
1021 			}
1022 
1023 			if (ret)
1024 				break;
1025 
1026 			debounce = readl(db_reg);
1027 			debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse;
1028 			writel(debounce, db_reg);
1029 
1030 			break;
1031 		default:
1032 			ret = -ENOTSUPP;
1033 		}
1034 
1035 		if (ret)
1036 			break;
1037 	}
1038 
1039 	if (!ret)
1040 		writel(conf, conf_reg);
1041 
1042 	raw_spin_unlock_irqrestore(&byt_lock, flags);
1043 
1044 	return ret;
1045 }
1046 
1047 static const struct pinconf_ops byt_pinconf_ops = {
1048 	.is_generic	= true,
1049 	.pin_config_get	= byt_pin_config_get,
1050 	.pin_config_set	= byt_pin_config_set,
1051 };
1052 
1053 static const struct pinctrl_desc byt_pinctrl_desc = {
1054 	.pctlops	= &byt_pinctrl_ops,
1055 	.pmxops		= &byt_pinmux_ops,
1056 	.confops	= &byt_pinconf_ops,
1057 	.owner		= THIS_MODULE,
1058 };
1059 
1060 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1061 {
1062 	struct intel_pinctrl *vg = gpiochip_get_data(chip);
1063 	void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1064 	unsigned long flags;
1065 	u32 val;
1066 
1067 	raw_spin_lock_irqsave(&byt_lock, flags);
1068 	val = readl(reg);
1069 	raw_spin_unlock_irqrestore(&byt_lock, flags);
1070 
1071 	return !!(val & BYT_LEVEL);
1072 }
1073 
1074 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1075 {
1076 	struct intel_pinctrl *vg = gpiochip_get_data(chip);
1077 	void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1078 	unsigned long flags;
1079 	u32 old_val;
1080 
1081 	if (!reg)
1082 		return;
1083 
1084 	raw_spin_lock_irqsave(&byt_lock, flags);
1085 	old_val = readl(reg);
1086 	if (value)
1087 		writel(old_val | BYT_LEVEL, reg);
1088 	else
1089 		writel(old_val & ~BYT_LEVEL, reg);
1090 	raw_spin_unlock_irqrestore(&byt_lock, flags);
1091 }
1092 
1093 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1094 {
1095 	struct intel_pinctrl *vg = gpiochip_get_data(chip);
1096 	void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1097 	unsigned long flags;
1098 	u32 value;
1099 
1100 	if (!reg)
1101 		return -EINVAL;
1102 
1103 	raw_spin_lock_irqsave(&byt_lock, flags);
1104 	value = readl(reg);
1105 	raw_spin_unlock_irqrestore(&byt_lock, flags);
1106 
1107 	if (!(value & BYT_OUTPUT_EN))
1108 		return GPIO_LINE_DIRECTION_OUT;
1109 	if (!(value & BYT_INPUT_EN))
1110 		return GPIO_LINE_DIRECTION_IN;
1111 
1112 	return -EINVAL;
1113 }
1114 
1115 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1116 {
1117 	struct intel_pinctrl *vg = gpiochip_get_data(chip);
1118 	void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1119 	unsigned long flags;
1120 	u32 reg;
1121 
1122 	raw_spin_lock_irqsave(&byt_lock, flags);
1123 
1124 	reg = readl(val_reg);
1125 	reg &= ~BYT_DIR_MASK;
1126 	reg |= BYT_OUTPUT_EN;
1127 	writel(reg, val_reg);
1128 
1129 	raw_spin_unlock_irqrestore(&byt_lock, flags);
1130 	return 0;
1131 }
1132 
1133 /*
1134  * Note despite the temptation this MUST NOT be converted into a call to
1135  * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this
1136  * MUST be done as a single BYT_VAL_REG register write.
1137  * See the commit message of the commit adding this comment for details.
1138  */
1139 static int byt_gpio_direction_output(struct gpio_chip *chip,
1140 				     unsigned int offset, int value)
1141 {
1142 	struct intel_pinctrl *vg = gpiochip_get_data(chip);
1143 	void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1144 	unsigned long flags;
1145 	u32 reg;
1146 
1147 	raw_spin_lock_irqsave(&byt_lock, flags);
1148 
1149 	byt_gpio_direct_irq_check(vg, offset);
1150 
1151 	reg = readl(val_reg);
1152 	reg &= ~BYT_DIR_MASK;
1153 	if (value)
1154 		reg |= BYT_LEVEL;
1155 	else
1156 		reg &= ~BYT_LEVEL;
1157 
1158 	writel(reg, val_reg);
1159 
1160 	raw_spin_unlock_irqrestore(&byt_lock, flags);
1161 	return 0;
1162 }
1163 
1164 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1165 {
1166 	struct intel_pinctrl *vg = gpiochip_get_data(chip);
1167 	int i;
1168 	u32 conf0, val;
1169 
1170 	for (i = 0; i < vg->soc->npins; i++) {
1171 		const struct intel_community *comm;
1172 		void __iomem *conf_reg, *val_reg;
1173 		const char *pull_str = NULL;
1174 		const char *pull = NULL;
1175 		unsigned long flags;
1176 		const char *label;
1177 		unsigned int pin;
1178 
1179 		pin = vg->soc->pins[i].number;
1180 
1181 		conf_reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1182 		if (!conf_reg) {
1183 			seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin);
1184 			continue;
1185 		}
1186 
1187 		val_reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1188 		if (!val_reg) {
1189 			seq_printf(s, "Pin %i: can't retrieve VAL\n", pin);
1190 			continue;
1191 		}
1192 
1193 		raw_spin_lock_irqsave(&byt_lock, flags);
1194 		conf0 = readl(conf_reg);
1195 		val = readl(val_reg);
1196 		raw_spin_unlock_irqrestore(&byt_lock, flags);
1197 
1198 		comm = intel_get_community(vg, pin);
1199 		if (!comm) {
1200 			seq_printf(s, "Pin %i: can't retrieve community\n", pin);
1201 			continue;
1202 		}
1203 		label = gpiochip_is_requested(chip, i);
1204 		if (!label)
1205 			label = "Unrequested";
1206 
1207 		switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1208 		case BYT_PULL_ASSIGN_UP:
1209 			pull = "up";
1210 			break;
1211 		case BYT_PULL_ASSIGN_DOWN:
1212 			pull = "down";
1213 			break;
1214 		}
1215 
1216 		switch (conf0 & BYT_PULL_STR_MASK) {
1217 		case BYT_PULL_STR_2K:
1218 			pull_str = "2k";
1219 			break;
1220 		case BYT_PULL_STR_10K:
1221 			pull_str = "10k";
1222 			break;
1223 		case BYT_PULL_STR_20K:
1224 			pull_str = "20k";
1225 			break;
1226 		case BYT_PULL_STR_40K:
1227 			pull_str = "40k";
1228 			break;
1229 		}
1230 
1231 		seq_printf(s,
1232 			   " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1233 			   pin,
1234 			   label,
1235 			   val & BYT_INPUT_EN ? "  " : "in",
1236 			   val & BYT_OUTPUT_EN ? "   " : "out",
1237 			   str_hi_lo(val & BYT_LEVEL),
1238 			   comm->pad_map[i], comm->pad_map[i] * 16,
1239 			   conf0 & 0x7,
1240 			   conf0 & BYT_TRIG_NEG ? " fall" : "     ",
1241 			   conf0 & BYT_TRIG_POS ? " rise" : "     ",
1242 			   conf0 & BYT_TRIG_LVL ? " level" : "      ");
1243 
1244 		if (pull && pull_str)
1245 			seq_printf(s, " %-4s %-3s", pull, pull_str);
1246 		else
1247 			seq_puts(s, "          ");
1248 
1249 		if (conf0 & BYT_IODEN)
1250 			seq_puts(s, " open-drain");
1251 
1252 		seq_puts(s, "\n");
1253 	}
1254 }
1255 
1256 static const struct gpio_chip byt_gpio_chip = {
1257 	.owner			= THIS_MODULE,
1258 	.request		= gpiochip_generic_request,
1259 	.free			= gpiochip_generic_free,
1260 	.get_direction		= byt_gpio_get_direction,
1261 	.direction_input	= byt_gpio_direction_input,
1262 	.direction_output	= byt_gpio_direction_output,
1263 	.get			= byt_gpio_get,
1264 	.set			= byt_gpio_set,
1265 	.set_config		= gpiochip_generic_config,
1266 	.dbg_show		= byt_gpio_dbg_show,
1267 };
1268 
1269 static void byt_irq_ack(struct irq_data *d)
1270 {
1271 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1272 	struct intel_pinctrl *vg = gpiochip_get_data(gc);
1273 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1274 	void __iomem *reg;
1275 
1276 	reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG);
1277 	if (!reg)
1278 		return;
1279 
1280 	raw_spin_lock(&byt_lock);
1281 	writel(BIT(hwirq % 32), reg);
1282 	raw_spin_unlock(&byt_lock);
1283 }
1284 
1285 static void byt_irq_mask(struct irq_data *d)
1286 {
1287 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1288 	struct intel_pinctrl *vg = gpiochip_get_data(gc);
1289 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1290 
1291 	byt_gpio_clear_triggering(vg, hwirq);
1292 	gpiochip_disable_irq(gc, hwirq);
1293 }
1294 
1295 static void byt_irq_unmask(struct irq_data *d)
1296 {
1297 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1298 	struct intel_pinctrl *vg = gpiochip_get_data(gc);
1299 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1300 	unsigned long flags;
1301 	void __iomem *reg;
1302 	u32 value;
1303 
1304 	gpiochip_enable_irq(gc, hwirq);
1305 
1306 	reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1307 	if (!reg)
1308 		return;
1309 
1310 	raw_spin_lock_irqsave(&byt_lock, flags);
1311 	value = readl(reg);
1312 
1313 	switch (irqd_get_trigger_type(d)) {
1314 	case IRQ_TYPE_LEVEL_HIGH:
1315 		value |= BYT_TRIG_LVL;
1316 		fallthrough;
1317 	case IRQ_TYPE_EDGE_RISING:
1318 		value |= BYT_TRIG_POS;
1319 		break;
1320 	case IRQ_TYPE_LEVEL_LOW:
1321 		value |= BYT_TRIG_LVL;
1322 		fallthrough;
1323 	case IRQ_TYPE_EDGE_FALLING:
1324 		value |= BYT_TRIG_NEG;
1325 		break;
1326 	case IRQ_TYPE_EDGE_BOTH:
1327 		value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1328 		break;
1329 	}
1330 
1331 	writel(value, reg);
1332 
1333 	raw_spin_unlock_irqrestore(&byt_lock, flags);
1334 }
1335 
1336 static int byt_irq_type(struct irq_data *d, unsigned int type)
1337 {
1338 	struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1339 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1340 	u32 value;
1341 	unsigned long flags;
1342 	void __iomem *reg;
1343 
1344 	reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1345 	if (!reg)
1346 		return -EINVAL;
1347 
1348 	raw_spin_lock_irqsave(&byt_lock, flags);
1349 	value = readl(reg);
1350 
1351 	WARN(value & BYT_DIRECT_IRQ_EN,
1352 	     "Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing");
1353 
1354 	/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1355 	 * are used to indicate high and low level triggering
1356 	 */
1357 	value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1358 		   BYT_TRIG_LVL);
1359 	/* Enable glitch filtering */
1360 	value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1361 		 BYT_GLITCH_F_FAST_CLK;
1362 
1363 	writel(value, reg);
1364 
1365 	if (type & IRQ_TYPE_EDGE_BOTH)
1366 		irq_set_handler_locked(d, handle_edge_irq);
1367 	else if (type & IRQ_TYPE_LEVEL_MASK)
1368 		irq_set_handler_locked(d, handle_level_irq);
1369 
1370 	raw_spin_unlock_irqrestore(&byt_lock, flags);
1371 
1372 	return 0;
1373 }
1374 
1375 static const struct irq_chip byt_gpio_irq_chip = {
1376 	.name		= "BYT-GPIO",
1377 	.irq_ack	= byt_irq_ack,
1378 	.irq_mask	= byt_irq_mask,
1379 	.irq_unmask	= byt_irq_unmask,
1380 	.irq_set_type	= byt_irq_type,
1381 	.flags		= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
1382 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
1383 };
1384 
1385 static void byt_gpio_irq_handler(struct irq_desc *desc)
1386 {
1387 	struct irq_data *data = irq_desc_get_irq_data(desc);
1388 	struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
1389 	struct irq_chip *chip = irq_data_get_irq_chip(data);
1390 	u32 base, pin;
1391 	void __iomem *reg;
1392 	unsigned long pending;
1393 
1394 	/* check from GPIO controller which pin triggered the interrupt */
1395 	for (base = 0; base < vg->chip.ngpio; base += 32) {
1396 		reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1397 
1398 		if (!reg) {
1399 			dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
1400 			continue;
1401 		}
1402 
1403 		raw_spin_lock(&byt_lock);
1404 		pending = readl(reg);
1405 		raw_spin_unlock(&byt_lock);
1406 		for_each_set_bit(pin, &pending, 32)
1407 			generic_handle_domain_irq(vg->chip.irq.domain, base + pin);
1408 	}
1409 	chip->irq_eoi(data);
1410 }
1411 
1412 static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0)
1413 {
1414 	int direct_irq, ioapic_direct_irq_base;
1415 	u8 *match, direct_irq_mux[16];
1416 	u32 trig;
1417 
1418 	memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG,
1419 		      sizeof(direct_irq_mux));
1420 	match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
1421 	if (!match) {
1422 		dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin);
1423 		return false;
1424 	}
1425 
1426 	direct_irq = match - direct_irq_mux;
1427 	/* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */
1428 	ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67;
1429 	dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin,
1430 		direct_irq, direct_irq + ioapic_direct_irq_base);
1431 
1432 	/*
1433 	 * Testing has shown that the way direct IRQs work is that the combination of the
1434 	 * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ
1435 	 * trigger block, which normally sets the status flag in the IRQ status reg at
1436 	 * 0x800, to one of the IO-APIC pins according to the mux registers.
1437 	 *
1438 	 * This means that:
1439 	 * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block
1440 	 * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly
1441 	 *    passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set,
1442 	 *    selecting edge mode operation then on the first edge the IO-APIC pin goes
1443 	 *    high, but since no write-to-clear write will be done to the IRQ status reg
1444 	 *    at 0x800, the detected edge condition will never get cleared.
1445 	 */
1446 	trig = conf0 & BYT_TRIG_MASK;
1447 	if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
1448 	    trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
1449 		dev_warn(vg->dev,
1450 			 FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n",
1451 			 pin, conf0);
1452 		return false;
1453 	}
1454 
1455 	return true;
1456 }
1457 
1458 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
1459 				    unsigned long *valid_mask,
1460 				    unsigned int ngpios)
1461 {
1462 	struct intel_pinctrl *vg = gpiochip_get_data(chip);
1463 	void __iomem *reg;
1464 	u32 value;
1465 	int i;
1466 
1467 	/*
1468 	 * Clear interrupt triggers for all pins that are GPIOs and
1469 	 * do not use direct IRQ mode. This will prevent spurious
1470 	 * interrupts from misconfigured pins.
1471 	 */
1472 	for (i = 0; i < vg->soc->npins; i++) {
1473 		unsigned int pin = vg->soc->pins[i].number;
1474 
1475 		reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1476 		if (!reg) {
1477 			dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i);
1478 			continue;
1479 		}
1480 
1481 		value = readl(reg);
1482 		if (value & BYT_DIRECT_IRQ_EN) {
1483 			if (byt_direct_irq_sanity_check(vg, i, value)) {
1484 				clear_bit(i, valid_mask);
1485 			} else {
1486 				value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS |
1487 					   BYT_TRIG_NEG | BYT_TRIG_LVL);
1488 				writel(value, reg);
1489 			}
1490 		} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1491 			byt_gpio_clear_triggering(vg, i);
1492 			dev_dbg(vg->dev, "disabling GPIO %d\n", i);
1493 		}
1494 	}
1495 }
1496 
1497 static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
1498 {
1499 	struct intel_pinctrl *vg = gpiochip_get_data(chip);
1500 	void __iomem *reg;
1501 	u32 base, value;
1502 
1503 	/* clear interrupt status trigger registers */
1504 	for (base = 0; base < vg->soc->npins; base += 32) {
1505 		reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1506 
1507 		if (!reg) {
1508 			dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
1509 			continue;
1510 		}
1511 
1512 		writel(0xffffffff, reg);
1513 		/* make sure trigger bits are cleared, if not then a pin
1514 		   might be misconfigured in bios */
1515 		value = readl(reg);
1516 		if (value)
1517 			dev_err(vg->dev,
1518 				"GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n",
1519 				base / 32, value);
1520 	}
1521 
1522 	return 0;
1523 }
1524 
1525 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
1526 {
1527 	struct intel_pinctrl *vg = gpiochip_get_data(chip);
1528 	struct device *dev = vg->dev;
1529 	int ret;
1530 
1531 	ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
1532 	if (ret)
1533 		dev_err(dev, "failed to add GPIO pin range\n");
1534 
1535 	return ret;
1536 }
1537 
1538 static int byt_gpio_probe(struct intel_pinctrl *vg)
1539 {
1540 	struct platform_device *pdev = to_platform_device(vg->dev);
1541 	struct gpio_chip *gc;
1542 	int irq, ret;
1543 
1544 	/* Set up gpio chip */
1545 	vg->chip	= byt_gpio_chip;
1546 	gc		= &vg->chip;
1547 	gc->label	= dev_name(vg->dev);
1548 	gc->base	= -1;
1549 	gc->can_sleep	= false;
1550 	gc->add_pin_ranges = byt_gpio_add_pin_ranges;
1551 	gc->parent	= vg->dev;
1552 	gc->ngpio	= vg->soc->npins;
1553 
1554 #ifdef CONFIG_PM_SLEEP
1555 	vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),
1556 					GFP_KERNEL);
1557 	if (!vg->context.pads)
1558 		return -ENOMEM;
1559 #endif
1560 
1561 	/* set up interrupts  */
1562 	irq = platform_get_irq_optional(pdev, 0);
1563 	if (irq > 0) {
1564 		struct gpio_irq_chip *girq;
1565 
1566 		girq = &gc->irq;
1567 		gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip);
1568 		girq->init_hw = byt_gpio_irq_init_hw;
1569 		girq->init_valid_mask = byt_init_irq_valid_mask;
1570 		girq->parent_handler = byt_gpio_irq_handler;
1571 		girq->num_parents = 1;
1572 		girq->parents = devm_kcalloc(vg->dev, girq->num_parents,
1573 					     sizeof(*girq->parents), GFP_KERNEL);
1574 		if (!girq->parents)
1575 			return -ENOMEM;
1576 		girq->parents[0] = irq;
1577 		girq->default_type = IRQ_TYPE_NONE;
1578 		girq->handler = handle_bad_irq;
1579 	}
1580 
1581 	ret = devm_gpiochip_add_data(vg->dev, gc, vg);
1582 	if (ret) {
1583 		dev_err(vg->dev, "failed adding byt-gpio chip\n");
1584 		return ret;
1585 	}
1586 
1587 	return ret;
1588 }
1589 
1590 static int byt_set_soc_data(struct intel_pinctrl *vg,
1591 			    const struct intel_pinctrl_soc_data *soc)
1592 {
1593 	struct platform_device *pdev = to_platform_device(vg->dev);
1594 	int i;
1595 
1596 	vg->soc = soc;
1597 
1598 	vg->ncommunities = vg->soc->ncommunities;
1599 	vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,
1600 				       sizeof(*vg->communities), GFP_KERNEL);
1601 	if (!vg->communities)
1602 		return -ENOMEM;
1603 
1604 	for (i = 0; i < vg->soc->ncommunities; i++) {
1605 		struct intel_community *comm = vg->communities + i;
1606 
1607 		*comm = vg->soc->communities[i];
1608 
1609 		comm->pad_regs = devm_platform_ioremap_resource(pdev, 0);
1610 		if (IS_ERR(comm->pad_regs))
1611 			return PTR_ERR(comm->pad_regs);
1612 	}
1613 
1614 	return 0;
1615 }
1616 
1617 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1618 	{ "INT33B2", (kernel_ulong_t)byt_soc_data },
1619 	{ "INT33FC", (kernel_ulong_t)byt_soc_data },
1620 	{ }
1621 };
1622 
1623 static int byt_pinctrl_probe(struct platform_device *pdev)
1624 {
1625 	const struct intel_pinctrl_soc_data *soc_data;
1626 	struct device *dev = &pdev->dev;
1627 	struct intel_pinctrl *vg;
1628 	int ret;
1629 
1630 	soc_data = intel_pinctrl_get_soc_data(pdev);
1631 	if (IS_ERR(soc_data))
1632 		return PTR_ERR(soc_data);
1633 
1634 	vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
1635 	if (!vg)
1636 		return -ENOMEM;
1637 
1638 	vg->dev = dev;
1639 	ret = byt_set_soc_data(vg, soc_data);
1640 	if (ret) {
1641 		dev_err(dev, "failed to set soc data\n");
1642 		return ret;
1643 	}
1644 
1645 	vg->pctldesc		= byt_pinctrl_desc;
1646 	vg->pctldesc.name	= dev_name(dev);
1647 	vg->pctldesc.pins	= vg->soc->pins;
1648 	vg->pctldesc.npins	= vg->soc->npins;
1649 
1650 	vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
1651 	if (IS_ERR(vg->pctldev)) {
1652 		dev_err(dev, "failed to register pinctrl driver\n");
1653 		return PTR_ERR(vg->pctldev);
1654 	}
1655 
1656 	ret = byt_gpio_probe(vg);
1657 	if (ret)
1658 		return ret;
1659 
1660 	platform_set_drvdata(pdev, vg);
1661 
1662 	return 0;
1663 }
1664 
1665 static int byt_gpio_suspend(struct device *dev)
1666 {
1667 	struct intel_pinctrl *vg = dev_get_drvdata(dev);
1668 	unsigned long flags;
1669 	int i;
1670 
1671 	raw_spin_lock_irqsave(&byt_lock, flags);
1672 
1673 	for (i = 0; i < vg->soc->npins; i++) {
1674 		void __iomem *reg;
1675 		u32 value;
1676 		unsigned int pin = vg->soc->pins[i].number;
1677 
1678 		reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1679 		if (!reg) {
1680 			dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
1681 			continue;
1682 		}
1683 		value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1684 		vg->context.pads[i].conf0 = value;
1685 
1686 		reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1687 		if (!reg) {
1688 			dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
1689 			continue;
1690 		}
1691 		value = readl(reg) & BYT_VAL_RESTORE_MASK;
1692 		vg->context.pads[i].val = value;
1693 	}
1694 
1695 	raw_spin_unlock_irqrestore(&byt_lock, flags);
1696 	return 0;
1697 }
1698 
1699 static int byt_gpio_resume(struct device *dev)
1700 {
1701 	struct intel_pinctrl *vg = dev_get_drvdata(dev);
1702 	unsigned long flags;
1703 	int i;
1704 
1705 	raw_spin_lock_irqsave(&byt_lock, flags);
1706 
1707 	for (i = 0; i < vg->soc->npins; i++) {
1708 		void __iomem *reg;
1709 		u32 value;
1710 		unsigned int pin = vg->soc->pins[i].number;
1711 
1712 		reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1713 		if (!reg) {
1714 			dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
1715 			continue;
1716 		}
1717 		value = readl(reg);
1718 		if ((value & BYT_CONF0_RESTORE_MASK) !=
1719 		     vg->context.pads[i].conf0) {
1720 			value &= ~BYT_CONF0_RESTORE_MASK;
1721 			value |= vg->context.pads[i].conf0;
1722 			writel(value, reg);
1723 			dev_info(dev, "restored pin %d CONF0 %#08x", i, value);
1724 		}
1725 
1726 		reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1727 		if (!reg) {
1728 			dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
1729 			continue;
1730 		}
1731 		value = readl(reg);
1732 		if ((value & BYT_VAL_RESTORE_MASK) !=
1733 		     vg->context.pads[i].val) {
1734 			u32 v;
1735 
1736 			v = value & ~BYT_VAL_RESTORE_MASK;
1737 			v |= vg->context.pads[i].val;
1738 			if (v != value) {
1739 				writel(v, reg);
1740 				dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v);
1741 			}
1742 		}
1743 	}
1744 
1745 	raw_spin_unlock_irqrestore(&byt_lock, flags);
1746 	return 0;
1747 }
1748 
1749 static const struct dev_pm_ops byt_gpio_pm_ops = {
1750 	LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1751 };
1752 
1753 static struct platform_driver byt_gpio_driver = {
1754 	.probe          = byt_pinctrl_probe,
1755 	.driver         = {
1756 		.name			= "byt_gpio",
1757 		.pm			= pm_sleep_ptr(&byt_gpio_pm_ops),
1758 		.acpi_match_table	= byt_gpio_acpi_match,
1759 		.suppress_bind_attrs	= true,
1760 	},
1761 };
1762 
1763 static int __init byt_gpio_init(void)
1764 {
1765 	return platform_driver_register(&byt_gpio_driver);
1766 }
1767 subsys_initcall(byt_gpio_init);
1768 
1769 MODULE_IMPORT_NS(PINCTRL_INTEL);
1770