1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pinctrl GPIO driver for Intel Baytrail 4 * 5 * Copyright (c) 2012-2013, Intel Corporation 6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/types.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/property.h> 20 #include <linux/seq_file.h> 21 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 27 #include "pinctrl-intel.h" 28 29 /* memory mapped register offsets */ 30 #define BYT_CONF0_REG 0x000 31 #define BYT_CONF1_REG 0x004 32 #define BYT_VAL_REG 0x008 33 #define BYT_DFT_REG 0x00c 34 #define BYT_INT_STAT_REG 0x800 35 #define BYT_DEBOUNCE_REG 0x9d0 36 37 /* BYT_CONF0_REG register bits */ 38 #define BYT_IODEN BIT(31) 39 #define BYT_DIRECT_IRQ_EN BIT(27) 40 #define BYT_TRIG_MASK GENMASK(26, 24) 41 #define BYT_TRIG_NEG BIT(26) 42 #define BYT_TRIG_POS BIT(25) 43 #define BYT_TRIG_LVL BIT(24) 44 #define BYT_DEBOUNCE_EN BIT(20) 45 #define BYT_GLITCH_FILTER_EN BIT(19) 46 #define BYT_GLITCH_F_SLOW_CLK BIT(17) 47 #define BYT_GLITCH_F_FAST_CLK BIT(16) 48 #define BYT_PULL_STR_SHIFT 9 49 #define BYT_PULL_STR_MASK GENMASK(10, 9) 50 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 51 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) 52 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) 53 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) 54 #define BYT_PULL_ASSIGN_SHIFT 7 55 #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7) 56 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT) 57 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT) 58 #define BYT_PIN_MUX GENMASK(2, 0) 59 60 /* BYT_VAL_REG register bits */ 61 #define BYT_DIR_MASK GENMASK(2, 1) 62 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ 63 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ 64 #define BYT_LEVEL BIT(0) 65 66 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX) 67 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL) 68 69 /* BYT_DEBOUNCE_REG bits */ 70 #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0) 71 #define BYT_DEBOUNCE_PULSE_375US 1 72 #define BYT_DEBOUNCE_PULSE_750US 2 73 #define BYT_DEBOUNCE_PULSE_1500US 3 74 #define BYT_DEBOUNCE_PULSE_3MS 4 75 #define BYT_DEBOUNCE_PULSE_6MS 5 76 #define BYT_DEBOUNCE_PULSE_12MS 6 77 #define BYT_DEBOUNCE_PULSE_24MS 7 78 79 #define BYT_NGPIO_SCORE 102 80 #define BYT_NGPIO_NCORE 28 81 #define BYT_NGPIO_SUS 44 82 83 #define BYT_SCORE_ACPI_UID "1" 84 #define BYT_NCORE_ACPI_UID "2" 85 #define BYT_SUS_ACPI_UID "3" 86 87 /* 88 * This is the function value most pins have for GPIO muxing. If the value 89 * differs from the default one, it must be explicitly mentioned. Otherwise, the 90 * pin control implementation will set the muxing value to default GPIO if it 91 * does not find a match for the requested function. 92 */ 93 #define BYT_DEFAULT_GPIO_MUX 0 94 #define BYT_ALTER_GPIO_MUX 1 95 96 struct intel_pad_context { 97 u32 conf0; 98 u32 val; 99 }; 100 101 #define COMMUNITY(p, n, map) \ 102 { \ 103 .pin_base = (p), \ 104 .npins = (n), \ 105 .pad_map = (map),\ 106 } 107 108 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */ 109 static const struct pinctrl_pin_desc byt_score_pins[] = { 110 PINCTRL_PIN(0, "SATA_GP0"), 111 PINCTRL_PIN(1, "SATA_GP1"), 112 PINCTRL_PIN(2, "SATA_LED#"), 113 PINCTRL_PIN(3, "PCIE_CLKREQ0"), 114 PINCTRL_PIN(4, "PCIE_CLKREQ1"), 115 PINCTRL_PIN(5, "PCIE_CLKREQ2"), 116 PINCTRL_PIN(6, "PCIE_CLKREQ3"), 117 PINCTRL_PIN(7, "SD3_WP"), 118 PINCTRL_PIN(8, "HDA_RST"), 119 PINCTRL_PIN(9, "HDA_SYNC"), 120 PINCTRL_PIN(10, "HDA_CLK"), 121 PINCTRL_PIN(11, "HDA_SDO"), 122 PINCTRL_PIN(12, "HDA_SDI0"), 123 PINCTRL_PIN(13, "HDA_SDI1"), 124 PINCTRL_PIN(14, "GPIO_S0_SC14"), 125 PINCTRL_PIN(15, "GPIO_S0_SC15"), 126 PINCTRL_PIN(16, "MMC1_CLK"), 127 PINCTRL_PIN(17, "MMC1_D0"), 128 PINCTRL_PIN(18, "MMC1_D1"), 129 PINCTRL_PIN(19, "MMC1_D2"), 130 PINCTRL_PIN(20, "MMC1_D3"), 131 PINCTRL_PIN(21, "MMC1_D4"), 132 PINCTRL_PIN(22, "MMC1_D5"), 133 PINCTRL_PIN(23, "MMC1_D6"), 134 PINCTRL_PIN(24, "MMC1_D7"), 135 PINCTRL_PIN(25, "MMC1_CMD"), 136 PINCTRL_PIN(26, "MMC1_RST"), 137 PINCTRL_PIN(27, "SD2_CLK"), 138 PINCTRL_PIN(28, "SD2_D0"), 139 PINCTRL_PIN(29, "SD2_D1"), 140 PINCTRL_PIN(30, "SD2_D2"), 141 PINCTRL_PIN(31, "SD2_D3_CD"), 142 PINCTRL_PIN(32, "SD2_CMD"), 143 PINCTRL_PIN(33, "SD3_CLK"), 144 PINCTRL_PIN(34, "SD3_D0"), 145 PINCTRL_PIN(35, "SD3_D1"), 146 PINCTRL_PIN(36, "SD3_D2"), 147 PINCTRL_PIN(37, "SD3_D3"), 148 PINCTRL_PIN(38, "SD3_CD"), 149 PINCTRL_PIN(39, "SD3_CMD"), 150 PINCTRL_PIN(40, "SD3_1P8EN"), 151 PINCTRL_PIN(41, "SD3_PWREN#"), 152 PINCTRL_PIN(42, "ILB_LPC_AD0"), 153 PINCTRL_PIN(43, "ILB_LPC_AD1"), 154 PINCTRL_PIN(44, "ILB_LPC_AD2"), 155 PINCTRL_PIN(45, "ILB_LPC_AD3"), 156 PINCTRL_PIN(46, "ILB_LPC_FRAME"), 157 PINCTRL_PIN(47, "ILB_LPC_CLK0"), 158 PINCTRL_PIN(48, "ILB_LPC_CLK1"), 159 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"), 160 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"), 161 PINCTRL_PIN(51, "PCU_SMB_DATA"), 162 PINCTRL_PIN(52, "PCU_SMB_CLK"), 163 PINCTRL_PIN(53, "PCU_SMB_ALERT"), 164 PINCTRL_PIN(54, "ILB_8254_SPKR"), 165 PINCTRL_PIN(55, "GPIO_S0_SC55"), 166 PINCTRL_PIN(56, "GPIO_S0_SC56"), 167 PINCTRL_PIN(57, "GPIO_S0_SC57"), 168 PINCTRL_PIN(58, "GPIO_S0_SC58"), 169 PINCTRL_PIN(59, "GPIO_S0_SC59"), 170 PINCTRL_PIN(60, "GPIO_S0_SC60"), 171 PINCTRL_PIN(61, "GPIO_S0_SC61"), 172 PINCTRL_PIN(62, "LPE_I2S2_CLK"), 173 PINCTRL_PIN(63, "LPE_I2S2_FRM"), 174 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"), 175 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"), 176 PINCTRL_PIN(66, "SIO_SPI_CS"), 177 PINCTRL_PIN(67, "SIO_SPI_MISO"), 178 PINCTRL_PIN(68, "SIO_SPI_MOSI"), 179 PINCTRL_PIN(69, "SIO_SPI_CLK"), 180 PINCTRL_PIN(70, "SIO_UART1_RXD"), 181 PINCTRL_PIN(71, "SIO_UART1_TXD"), 182 PINCTRL_PIN(72, "SIO_UART1_RTS"), 183 PINCTRL_PIN(73, "SIO_UART1_CTS"), 184 PINCTRL_PIN(74, "SIO_UART2_RXD"), 185 PINCTRL_PIN(75, "SIO_UART2_TXD"), 186 PINCTRL_PIN(76, "SIO_UART2_RTS"), 187 PINCTRL_PIN(77, "SIO_UART2_CTS"), 188 PINCTRL_PIN(78, "SIO_I2C0_DATA"), 189 PINCTRL_PIN(79, "SIO_I2C0_CLK"), 190 PINCTRL_PIN(80, "SIO_I2C1_DATA"), 191 PINCTRL_PIN(81, "SIO_I2C1_CLK"), 192 PINCTRL_PIN(82, "SIO_I2C2_DATA"), 193 PINCTRL_PIN(83, "SIO_I2C2_CLK"), 194 PINCTRL_PIN(84, "SIO_I2C3_DATA"), 195 PINCTRL_PIN(85, "SIO_I2C3_CLK"), 196 PINCTRL_PIN(86, "SIO_I2C4_DATA"), 197 PINCTRL_PIN(87, "SIO_I2C4_CLK"), 198 PINCTRL_PIN(88, "SIO_I2C5_DATA"), 199 PINCTRL_PIN(89, "SIO_I2C5_CLK"), 200 PINCTRL_PIN(90, "SIO_I2C6_DATA"), 201 PINCTRL_PIN(91, "SIO_I2C6_CLK"), 202 PINCTRL_PIN(92, "GPIO_S0_SC92"), 203 PINCTRL_PIN(93, "GPIO_S0_SC93"), 204 PINCTRL_PIN(94, "SIO_PWM0"), 205 PINCTRL_PIN(95, "SIO_PWM1"), 206 PINCTRL_PIN(96, "PMC_PLT_CLK0"), 207 PINCTRL_PIN(97, "PMC_PLT_CLK1"), 208 PINCTRL_PIN(98, "PMC_PLT_CLK2"), 209 PINCTRL_PIN(99, "PMC_PLT_CLK3"), 210 PINCTRL_PIN(100, "PMC_PLT_CLK4"), 211 PINCTRL_PIN(101, "PMC_PLT_CLK5"), 212 }; 213 214 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = { 215 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, 216 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, 217 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, 218 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, 219 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, 220 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, 221 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, 222 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, 223 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, 224 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, 225 97, 100, 226 }; 227 228 /* SCORE groups */ 229 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 }; 230 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 }; 231 232 static const unsigned int byt_score_pwm0_pins[] = { 94 }; 233 static const unsigned int byt_score_pwm1_pins[] = { 95 }; 234 235 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 }; 236 237 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 }; 238 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 }; 239 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 }; 240 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 }; 241 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 }; 242 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 }; 243 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 }; 244 245 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 }; 246 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 }; 247 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 }; 248 249 static const unsigned int byt_score_sdcard_pins[] = { 250 7, 33, 34, 35, 36, 37, 38, 39, 40, 41, 251 }; 252 static const unsigned int byt_score_sdcard_mux_values[] = { 253 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 254 }; 255 256 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 }; 257 258 static const unsigned int byt_score_emmc_pins[] = { 259 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 260 }; 261 262 static const unsigned int byt_score_ilb_lpc_pins[] = { 263 42, 43, 44, 45, 46, 47, 48, 49, 50, 264 }; 265 266 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 }; 267 268 static const unsigned int byt_score_plt_clk0_pins[] = { 96 }; 269 static const unsigned int byt_score_plt_clk1_pins[] = { 97 }; 270 static const unsigned int byt_score_plt_clk2_pins[] = { 98 }; 271 static const unsigned int byt_score_plt_clk3_pins[] = { 99 }; 272 static const unsigned int byt_score_plt_clk4_pins[] = { 100 }; 273 static const unsigned int byt_score_plt_clk5_pins[] = { 101 }; 274 275 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 }; 276 277 static const struct intel_pingroup byt_score_groups[] = { 278 PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1), 279 PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1), 280 PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1), 281 PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1), 282 PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1), 283 PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1), 284 PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1), 285 PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1), 286 PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1), 287 PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1), 288 PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1), 289 PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1), 290 PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1), 291 PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1), 292 PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1), 293 PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values), 294 PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1), 295 PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1), 296 PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1), 297 PIN_GROUP("sata_grp", byt_score_sata_pins, 1), 298 PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1), 299 PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1), 300 PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1), 301 PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1), 302 PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1), 303 PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1), 304 PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1), 305 }; 306 307 static const char * const byt_score_uart_groups[] = { 308 "uart1_grp", "uart2_grp", 309 }; 310 static const char * const byt_score_pwm_groups[] = { 311 "pwm0_grp", "pwm1_grp", 312 }; 313 static const char * const byt_score_ssp_groups[] = { 314 "ssp0_grp", "ssp1_grp", "ssp2_grp", 315 }; 316 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" }; 317 static const char * const byt_score_i2c_groups[] = { 318 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", 319 "i2c6_grp", 320 }; 321 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" }; 322 static const char * const byt_score_sdio_groups[] = { "sdio_grp" }; 323 static const char * const byt_score_emmc_groups[] = { "emmc_grp" }; 324 static const char * const byt_score_lpc_groups[] = { "lpc_grp" }; 325 static const char * const byt_score_sata_groups[] = { "sata_grp" }; 326 static const char * const byt_score_plt_clk_groups[] = { 327 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 328 "plt_clk4_grp", "plt_clk5_grp", 329 }; 330 static const char * const byt_score_smbus_groups[] = { "smbus_grp" }; 331 static const char * const byt_score_gpio_groups[] = { 332 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp", 333 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp", 334 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp", 335 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp", 336 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 337 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp", 338 }; 339 340 static const struct intel_function byt_score_functions[] = { 341 FUNCTION("uart", byt_score_uart_groups), 342 FUNCTION("pwm", byt_score_pwm_groups), 343 FUNCTION("ssp", byt_score_ssp_groups), 344 FUNCTION("spi", byt_score_spi_groups), 345 FUNCTION("i2c", byt_score_i2c_groups), 346 FUNCTION("sdcard", byt_score_sdcard_groups), 347 FUNCTION("sdio", byt_score_sdio_groups), 348 FUNCTION("emmc", byt_score_emmc_groups), 349 FUNCTION("lpc", byt_score_lpc_groups), 350 FUNCTION("sata", byt_score_sata_groups), 351 FUNCTION("plt_clk", byt_score_plt_clk_groups), 352 FUNCTION("smbus", byt_score_smbus_groups), 353 FUNCTION("gpio", byt_score_gpio_groups), 354 }; 355 356 static const struct intel_community byt_score_communities[] = { 357 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map), 358 }; 359 360 static const struct intel_pinctrl_soc_data byt_score_soc_data = { 361 .uid = BYT_SCORE_ACPI_UID, 362 .pins = byt_score_pins, 363 .npins = ARRAY_SIZE(byt_score_pins), 364 .groups = byt_score_groups, 365 .ngroups = ARRAY_SIZE(byt_score_groups), 366 .functions = byt_score_functions, 367 .nfunctions = ARRAY_SIZE(byt_score_functions), 368 .communities = byt_score_communities, 369 .ncommunities = ARRAY_SIZE(byt_score_communities), 370 }; 371 372 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */ 373 static const struct pinctrl_pin_desc byt_sus_pins[] = { 374 PINCTRL_PIN(0, "GPIO_S50"), 375 PINCTRL_PIN(1, "GPIO_S51"), 376 PINCTRL_PIN(2, "GPIO_S52"), 377 PINCTRL_PIN(3, "GPIO_S53"), 378 PINCTRL_PIN(4, "GPIO_S54"), 379 PINCTRL_PIN(5, "GPIO_S55"), 380 PINCTRL_PIN(6, "GPIO_S56"), 381 PINCTRL_PIN(7, "GPIO_S57"), 382 PINCTRL_PIN(8, "GPIO_S58"), 383 PINCTRL_PIN(9, "GPIO_S59"), 384 PINCTRL_PIN(10, "GPIO_S510"), 385 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"), 386 PINCTRL_PIN(12, "PMC_SUSCLK0"), 387 PINCTRL_PIN(13, "GPIO_S513"), 388 PINCTRL_PIN(14, "USB_ULPI_RST"), 389 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"), 390 PINCTRL_PIN(16, "PMC_PWRBTN"), 391 PINCTRL_PIN(17, "GPIO_S517"), 392 PINCTRL_PIN(18, "PMC_SUS_STAT"), 393 PINCTRL_PIN(19, "USB_OC0"), 394 PINCTRL_PIN(20, "USB_OC1"), 395 PINCTRL_PIN(21, "PCU_SPI_CS1"), 396 PINCTRL_PIN(22, "GPIO_S522"), 397 PINCTRL_PIN(23, "GPIO_S523"), 398 PINCTRL_PIN(24, "GPIO_S524"), 399 PINCTRL_PIN(25, "GPIO_S525"), 400 PINCTRL_PIN(26, "GPIO_S526"), 401 PINCTRL_PIN(27, "GPIO_S527"), 402 PINCTRL_PIN(28, "GPIO_S528"), 403 PINCTRL_PIN(29, "GPIO_S529"), 404 PINCTRL_PIN(30, "GPIO_S530"), 405 PINCTRL_PIN(31, "USB_ULPI_CLK"), 406 PINCTRL_PIN(32, "USB_ULPI_DATA0"), 407 PINCTRL_PIN(33, "USB_ULPI_DATA1"), 408 PINCTRL_PIN(34, "USB_ULPI_DATA2"), 409 PINCTRL_PIN(35, "USB_ULPI_DATA3"), 410 PINCTRL_PIN(36, "USB_ULPI_DATA4"), 411 PINCTRL_PIN(37, "USB_ULPI_DATA5"), 412 PINCTRL_PIN(38, "USB_ULPI_DATA6"), 413 PINCTRL_PIN(39, "USB_ULPI_DATA7"), 414 PINCTRL_PIN(40, "USB_ULPI_DIR"), 415 PINCTRL_PIN(41, "USB_ULPI_NXT"), 416 PINCTRL_PIN(42, "USB_ULPI_STP"), 417 PINCTRL_PIN(43, "USB_ULPI_REFCLK"), 418 }; 419 420 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = { 421 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 422 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 423 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 424 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 425 52, 53, 59, 40, 426 }; 427 428 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 }; 429 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 }; 430 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 }; 431 432 static const unsigned int byt_sus_usb_ulpi_pins[] = { 433 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 434 }; 435 static const unsigned int byt_sus_usb_ulpi_mode_values[] = { 436 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 437 }; 438 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = { 439 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 440 }; 441 442 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 }; 443 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 }; 444 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 }; 445 446 static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 }; 447 static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 }; 448 449 static const struct intel_pingroup byt_sus_groups[] = { 450 PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values), 451 PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values), 452 PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values), 453 PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values), 454 PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values), 455 PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values), 456 PIN_GROUP("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1), 457 PIN_GROUP("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1), 458 }; 459 460 static const char * const byt_sus_usb_groups[] = { 461 "usb_oc_grp", "usb_ulpi_grp", 462 }; 463 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" }; 464 static const char * const byt_sus_pmu_clk_groups[] = { 465 "pmu_clk1_grp", "pmu_clk2_grp", 466 }; 467 static const char * const byt_sus_gpio_groups[] = { 468 "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio", 469 "pmu_clk1_grp", "pmu_clk2_grp", 470 }; 471 472 static const struct intel_function byt_sus_functions[] = { 473 FUNCTION("usb", byt_sus_usb_groups), 474 FUNCTION("spi", byt_sus_spi_groups), 475 FUNCTION("gpio", byt_sus_gpio_groups), 476 FUNCTION("pmu_clk", byt_sus_pmu_clk_groups), 477 }; 478 479 static const struct intel_community byt_sus_communities[] = { 480 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map), 481 }; 482 483 static const struct intel_pinctrl_soc_data byt_sus_soc_data = { 484 .uid = BYT_SUS_ACPI_UID, 485 .pins = byt_sus_pins, 486 .npins = ARRAY_SIZE(byt_sus_pins), 487 .groups = byt_sus_groups, 488 .ngroups = ARRAY_SIZE(byt_sus_groups), 489 .functions = byt_sus_functions, 490 .nfunctions = ARRAY_SIZE(byt_sus_functions), 491 .communities = byt_sus_communities, 492 .ncommunities = ARRAY_SIZE(byt_sus_communities), 493 }; 494 495 static const struct pinctrl_pin_desc byt_ncore_pins[] = { 496 PINCTRL_PIN(0, "HV_DDI0_HPD"), 497 PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"), 498 PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"), 499 PINCTRL_PIN(3, "PANEL0_VDDEN"), 500 PINCTRL_PIN(4, "PANEL0_BKLTEN"), 501 PINCTRL_PIN(5, "PANEL0_BKLTCTL"), 502 PINCTRL_PIN(6, "HV_DDI1_HPD"), 503 PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"), 504 PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"), 505 PINCTRL_PIN(9, "PANEL1_VDDEN"), 506 PINCTRL_PIN(10, "PANEL1_BKLTEN"), 507 PINCTRL_PIN(11, "PANEL1_BKLTCTL"), 508 PINCTRL_PIN(12, "GP_INTD_DSI_TE1"), 509 PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"), 510 PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"), 511 PINCTRL_PIN(15, "GP_CAMERASB00"), 512 PINCTRL_PIN(16, "GP_CAMERASB01"), 513 PINCTRL_PIN(17, "GP_CAMERASB02"), 514 PINCTRL_PIN(18, "GP_CAMERASB03"), 515 PINCTRL_PIN(19, "GP_CAMERASB04"), 516 PINCTRL_PIN(20, "GP_CAMERASB05"), 517 PINCTRL_PIN(21, "GP_CAMERASB06"), 518 PINCTRL_PIN(22, "GP_CAMERASB07"), 519 PINCTRL_PIN(23, "GP_CAMERASB08"), 520 PINCTRL_PIN(24, "GP_CAMERASB09"), 521 PINCTRL_PIN(25, "GP_CAMERASB10"), 522 PINCTRL_PIN(26, "GP_CAMERASB11"), 523 PINCTRL_PIN(27, "GP_INTD_DSI_TE2"), 524 }; 525 526 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = { 527 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 528 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 529 3, 6, 10, 13, 2, 5, 9, 7, 530 }; 531 532 static const struct intel_community byt_ncore_communities[] = { 533 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map), 534 }; 535 536 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = { 537 .uid = BYT_NCORE_ACPI_UID, 538 .pins = byt_ncore_pins, 539 .npins = ARRAY_SIZE(byt_ncore_pins), 540 .communities = byt_ncore_communities, 541 .ncommunities = ARRAY_SIZE(byt_ncore_communities), 542 }; 543 544 static const struct intel_pinctrl_soc_data *byt_soc_data[] = { 545 &byt_score_soc_data, 546 &byt_sus_soc_data, 547 &byt_ncore_soc_data, 548 NULL 549 }; 550 551 static DEFINE_RAW_SPINLOCK(byt_lock); 552 553 static struct intel_community *byt_get_community(struct intel_pinctrl *vg, 554 unsigned int pin) 555 { 556 struct intel_community *comm; 557 int i; 558 559 for (i = 0; i < vg->ncommunities; i++) { 560 comm = vg->communities + i; 561 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) 562 return comm; 563 } 564 565 return NULL; 566 } 567 568 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, 569 int reg) 570 { 571 struct intel_community *comm = byt_get_community(vg, offset); 572 u32 reg_offset; 573 574 if (!comm) 575 return NULL; 576 577 offset -= comm->pin_base; 578 switch (reg) { 579 case BYT_INT_STAT_REG: 580 reg_offset = (offset / 32) * 4; 581 break; 582 case BYT_DEBOUNCE_REG: 583 reg_offset = 0; 584 break; 585 default: 586 reg_offset = comm->pad_map[offset] * 16; 587 break; 588 } 589 590 return comm->pad_regs + reg_offset + reg; 591 } 592 593 static int byt_get_groups_count(struct pinctrl_dev *pctldev) 594 { 595 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 596 597 return vg->soc->ngroups; 598 } 599 600 static const char *byt_get_group_name(struct pinctrl_dev *pctldev, 601 unsigned int selector) 602 { 603 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 604 605 return vg->soc->groups[selector].name; 606 } 607 608 static int byt_get_group_pins(struct pinctrl_dev *pctldev, 609 unsigned int selector, 610 const unsigned int **pins, 611 unsigned int *num_pins) 612 { 613 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 614 615 *pins = vg->soc->groups[selector].pins; 616 *num_pins = vg->soc->groups[selector].npins; 617 618 return 0; 619 } 620 621 static const struct pinctrl_ops byt_pinctrl_ops = { 622 .get_groups_count = byt_get_groups_count, 623 .get_group_name = byt_get_group_name, 624 .get_group_pins = byt_get_group_pins, 625 }; 626 627 static int byt_get_functions_count(struct pinctrl_dev *pctldev) 628 { 629 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 630 631 return vg->soc->nfunctions; 632 } 633 634 static const char *byt_get_function_name(struct pinctrl_dev *pctldev, 635 unsigned int selector) 636 { 637 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 638 639 return vg->soc->functions[selector].name; 640 } 641 642 static int byt_get_function_groups(struct pinctrl_dev *pctldev, 643 unsigned int selector, 644 const char * const **groups, 645 unsigned int *num_groups) 646 { 647 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 648 649 *groups = vg->soc->functions[selector].groups; 650 *num_groups = vg->soc->functions[selector].ngroups; 651 652 return 0; 653 } 654 655 static void byt_set_group_simple_mux(struct intel_pinctrl *vg, 656 const struct intel_pingroup group, 657 unsigned int func) 658 { 659 unsigned long flags; 660 int i; 661 662 raw_spin_lock_irqsave(&byt_lock, flags); 663 664 for (i = 0; i < group.npins; i++) { 665 void __iomem *padcfg0; 666 u32 value; 667 668 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG); 669 if (!padcfg0) { 670 dev_warn(vg->dev, 671 "Group %s, pin %i not muxed (no padcfg0)\n", 672 group.name, i); 673 continue; 674 } 675 676 value = readl(padcfg0); 677 value &= ~BYT_PIN_MUX; 678 value |= func; 679 writel(value, padcfg0); 680 } 681 682 raw_spin_unlock_irqrestore(&byt_lock, flags); 683 } 684 685 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg, 686 const struct intel_pingroup group, 687 const unsigned int *func) 688 { 689 unsigned long flags; 690 int i; 691 692 raw_spin_lock_irqsave(&byt_lock, flags); 693 694 for (i = 0; i < group.npins; i++) { 695 void __iomem *padcfg0; 696 u32 value; 697 698 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG); 699 if (!padcfg0) { 700 dev_warn(vg->dev, 701 "Group %s, pin %i not muxed (no padcfg0)\n", 702 group.name, i); 703 continue; 704 } 705 706 value = readl(padcfg0); 707 value &= ~BYT_PIN_MUX; 708 value |= func[i]; 709 writel(value, padcfg0); 710 } 711 712 raw_spin_unlock_irqrestore(&byt_lock, flags); 713 } 714 715 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 716 unsigned int group_selector) 717 { 718 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 719 const struct intel_function func = vg->soc->functions[func_selector]; 720 const struct intel_pingroup group = vg->soc->groups[group_selector]; 721 722 if (group.modes) 723 byt_set_group_mixed_mux(vg, group, group.modes); 724 else if (!strcmp(func.name, "gpio")) 725 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX); 726 else 727 byt_set_group_simple_mux(vg, group, group.mode); 728 729 return 0; 730 } 731 732 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset) 733 { 734 /* SCORE pin 92-93 */ 735 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) && 736 offset >= 92 && offset <= 93) 737 return BYT_ALTER_GPIO_MUX; 738 739 /* SUS pin 11-21 */ 740 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) && 741 offset >= 11 && offset <= 21) 742 return BYT_ALTER_GPIO_MUX; 743 744 return BYT_DEFAULT_GPIO_MUX; 745 } 746 747 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset) 748 { 749 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 750 unsigned long flags; 751 u32 value; 752 753 raw_spin_lock_irqsave(&byt_lock, flags); 754 value = readl(reg); 755 756 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */ 757 if (value & BYT_DIRECT_IRQ_EN) 758 /* nothing to do */ ; 759 else 760 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 761 762 writel(value, reg); 763 raw_spin_unlock_irqrestore(&byt_lock, flags); 764 } 765 766 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, 767 struct pinctrl_gpio_range *range, 768 unsigned int offset) 769 { 770 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 771 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 772 u32 value, gpio_mux; 773 unsigned long flags; 774 775 raw_spin_lock_irqsave(&byt_lock, flags); 776 777 /* 778 * In most cases, func pin mux 000 means GPIO function. 779 * But, some pins may have func pin mux 001 represents 780 * GPIO function. 781 * 782 * Because there are devices out there where some pins were not 783 * configured correctly we allow changing the mux value from 784 * request (but print out warning about that). 785 */ 786 value = readl(reg) & BYT_PIN_MUX; 787 gpio_mux = byt_get_gpio_mux(vg, offset); 788 if (gpio_mux != value) { 789 value = readl(reg) & ~BYT_PIN_MUX; 790 value |= gpio_mux; 791 writel(value, reg); 792 793 dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset); 794 } 795 796 raw_spin_unlock_irqrestore(&byt_lock, flags); 797 798 pm_runtime_get(vg->dev); 799 800 return 0; 801 } 802 803 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, 804 struct pinctrl_gpio_range *range, 805 unsigned int offset) 806 { 807 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 808 809 byt_gpio_clear_triggering(vg, offset); 810 pm_runtime_put(vg->dev); 811 } 812 813 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg, 814 unsigned int offset) 815 { 816 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 817 818 /* 819 * Before making any direction modifications, do a check if gpio is set 820 * for direct IRQ. On Bay Trail, setting GPIO to output does not make 821 * sense, so let's at least inform the caller before they shoot 822 * themselves in the foot. 823 */ 824 if (readl(conf_reg) & BYT_DIRECT_IRQ_EN) 825 dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output"); 826 } 827 828 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, 829 struct pinctrl_gpio_range *range, 830 unsigned int offset, 831 bool input) 832 { 833 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 834 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 835 unsigned long flags; 836 u32 value; 837 838 raw_spin_lock_irqsave(&byt_lock, flags); 839 840 value = readl(val_reg); 841 value &= ~BYT_DIR_MASK; 842 if (input) 843 value |= BYT_OUTPUT_EN; 844 else 845 byt_gpio_direct_irq_check(vg, offset); 846 847 writel(value, val_reg); 848 849 raw_spin_unlock_irqrestore(&byt_lock, flags); 850 851 return 0; 852 } 853 854 static const struct pinmux_ops byt_pinmux_ops = { 855 .get_functions_count = byt_get_functions_count, 856 .get_function_name = byt_get_function_name, 857 .get_function_groups = byt_get_function_groups, 858 .set_mux = byt_set_mux, 859 .gpio_request_enable = byt_gpio_request_enable, 860 .gpio_disable_free = byt_gpio_disable_free, 861 .gpio_set_direction = byt_gpio_set_direction, 862 }; 863 864 static void byt_get_pull_strength(u32 reg, u16 *strength) 865 { 866 switch (reg & BYT_PULL_STR_MASK) { 867 case BYT_PULL_STR_2K: 868 *strength = 2000; 869 break; 870 case BYT_PULL_STR_10K: 871 *strength = 10000; 872 break; 873 case BYT_PULL_STR_20K: 874 *strength = 20000; 875 break; 876 case BYT_PULL_STR_40K: 877 *strength = 40000; 878 break; 879 } 880 } 881 882 static int byt_set_pull_strength(u32 *reg, u16 strength) 883 { 884 *reg &= ~BYT_PULL_STR_MASK; 885 886 switch (strength) { 887 case 2000: 888 *reg |= BYT_PULL_STR_2K; 889 break; 890 case 10000: 891 *reg |= BYT_PULL_STR_10K; 892 break; 893 case 20000: 894 *reg |= BYT_PULL_STR_20K; 895 break; 896 case 40000: 897 *reg |= BYT_PULL_STR_40K; 898 break; 899 default: 900 return -EINVAL; 901 } 902 903 return 0; 904 } 905 906 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, 907 unsigned long *config) 908 { 909 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 910 enum pin_config_param param = pinconf_to_config_param(*config); 911 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 912 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 913 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 914 unsigned long flags; 915 u32 conf, pull, val, debounce; 916 u16 arg = 0; 917 918 raw_spin_lock_irqsave(&byt_lock, flags); 919 conf = readl(conf_reg); 920 pull = conf & BYT_PULL_ASSIGN_MASK; 921 val = readl(val_reg); 922 raw_spin_unlock_irqrestore(&byt_lock, flags); 923 924 switch (param) { 925 case PIN_CONFIG_BIAS_DISABLE: 926 if (pull) 927 return -EINVAL; 928 break; 929 case PIN_CONFIG_BIAS_PULL_DOWN: 930 /* Pull assignment is only applicable in input mode */ 931 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN) 932 return -EINVAL; 933 934 byt_get_pull_strength(conf, &arg); 935 936 break; 937 case PIN_CONFIG_BIAS_PULL_UP: 938 /* Pull assignment is only applicable in input mode */ 939 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP) 940 return -EINVAL; 941 942 byt_get_pull_strength(conf, &arg); 943 944 break; 945 case PIN_CONFIG_INPUT_DEBOUNCE: 946 if (!(conf & BYT_DEBOUNCE_EN)) 947 return -EINVAL; 948 949 raw_spin_lock_irqsave(&byt_lock, flags); 950 debounce = readl(db_reg); 951 raw_spin_unlock_irqrestore(&byt_lock, flags); 952 953 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) { 954 case BYT_DEBOUNCE_PULSE_375US: 955 arg = 375; 956 break; 957 case BYT_DEBOUNCE_PULSE_750US: 958 arg = 750; 959 break; 960 case BYT_DEBOUNCE_PULSE_1500US: 961 arg = 1500; 962 break; 963 case BYT_DEBOUNCE_PULSE_3MS: 964 arg = 3000; 965 break; 966 case BYT_DEBOUNCE_PULSE_6MS: 967 arg = 6000; 968 break; 969 case BYT_DEBOUNCE_PULSE_12MS: 970 arg = 12000; 971 break; 972 case BYT_DEBOUNCE_PULSE_24MS: 973 arg = 24000; 974 break; 975 default: 976 return -EINVAL; 977 } 978 979 break; 980 default: 981 return -ENOTSUPP; 982 } 983 984 *config = pinconf_to_config_packed(param, arg); 985 986 return 0; 987 } 988 989 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 990 unsigned int offset, 991 unsigned long *configs, 992 unsigned int num_configs) 993 { 994 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 995 unsigned int param, arg; 996 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 997 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 998 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 999 unsigned long flags; 1000 u32 conf, val, debounce; 1001 int i, ret = 0; 1002 1003 raw_spin_lock_irqsave(&byt_lock, flags); 1004 1005 conf = readl(conf_reg); 1006 val = readl(val_reg); 1007 1008 for (i = 0; i < num_configs; i++) { 1009 param = pinconf_to_config_param(configs[i]); 1010 arg = pinconf_to_config_argument(configs[i]); 1011 1012 switch (param) { 1013 case PIN_CONFIG_BIAS_DISABLE: 1014 conf &= ~BYT_PULL_ASSIGN_MASK; 1015 break; 1016 case PIN_CONFIG_BIAS_PULL_DOWN: 1017 /* Set default strength value in case none is given */ 1018 if (arg == 1) 1019 arg = 2000; 1020 1021 /* 1022 * Pull assignment is only applicable in input mode. If 1023 * chip is not in input mode, set it and warn about it. 1024 */ 1025 if (val & BYT_INPUT_EN) { 1026 val &= ~BYT_INPUT_EN; 1027 writel(val, val_reg); 1028 dev_warn(vg->dev, 1029 "pin %u forcibly set to input mode\n", 1030 offset); 1031 } 1032 1033 conf &= ~BYT_PULL_ASSIGN_MASK; 1034 conf |= BYT_PULL_ASSIGN_DOWN; 1035 ret = byt_set_pull_strength(&conf, arg); 1036 1037 break; 1038 case PIN_CONFIG_BIAS_PULL_UP: 1039 /* Set default strength value in case none is given */ 1040 if (arg == 1) 1041 arg = 2000; 1042 1043 /* 1044 * Pull assignment is only applicable in input mode. If 1045 * chip is not in input mode, set it and warn about it. 1046 */ 1047 if (val & BYT_INPUT_EN) { 1048 val &= ~BYT_INPUT_EN; 1049 writel(val, val_reg); 1050 dev_warn(vg->dev, 1051 "pin %u forcibly set to input mode\n", 1052 offset); 1053 } 1054 1055 conf &= ~BYT_PULL_ASSIGN_MASK; 1056 conf |= BYT_PULL_ASSIGN_UP; 1057 ret = byt_set_pull_strength(&conf, arg); 1058 1059 break; 1060 case PIN_CONFIG_INPUT_DEBOUNCE: 1061 debounce = readl(db_reg); 1062 1063 if (arg) 1064 conf |= BYT_DEBOUNCE_EN; 1065 else 1066 conf &= ~BYT_DEBOUNCE_EN; 1067 1068 switch (arg) { 1069 case 375: 1070 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1071 debounce |= BYT_DEBOUNCE_PULSE_375US; 1072 break; 1073 case 750: 1074 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1075 debounce |= BYT_DEBOUNCE_PULSE_750US; 1076 break; 1077 case 1500: 1078 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1079 debounce |= BYT_DEBOUNCE_PULSE_1500US; 1080 break; 1081 case 3000: 1082 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1083 debounce |= BYT_DEBOUNCE_PULSE_3MS; 1084 break; 1085 case 6000: 1086 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1087 debounce |= BYT_DEBOUNCE_PULSE_6MS; 1088 break; 1089 case 12000: 1090 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1091 debounce |= BYT_DEBOUNCE_PULSE_12MS; 1092 break; 1093 case 24000: 1094 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1095 debounce |= BYT_DEBOUNCE_PULSE_24MS; 1096 break; 1097 default: 1098 if (arg) 1099 ret = -EINVAL; 1100 break; 1101 } 1102 1103 if (!ret) 1104 writel(debounce, db_reg); 1105 break; 1106 default: 1107 ret = -ENOTSUPP; 1108 } 1109 1110 if (ret) 1111 break; 1112 } 1113 1114 if (!ret) 1115 writel(conf, conf_reg); 1116 1117 raw_spin_unlock_irqrestore(&byt_lock, flags); 1118 1119 return ret; 1120 } 1121 1122 static const struct pinconf_ops byt_pinconf_ops = { 1123 .is_generic = true, 1124 .pin_config_get = byt_pin_config_get, 1125 .pin_config_set = byt_pin_config_set, 1126 }; 1127 1128 static const struct pinctrl_desc byt_pinctrl_desc = { 1129 .pctlops = &byt_pinctrl_ops, 1130 .pmxops = &byt_pinmux_ops, 1131 .confops = &byt_pinconf_ops, 1132 .owner = THIS_MODULE, 1133 }; 1134 1135 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) 1136 { 1137 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1138 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1139 unsigned long flags; 1140 u32 val; 1141 1142 raw_spin_lock_irqsave(&byt_lock, flags); 1143 val = readl(reg); 1144 raw_spin_unlock_irqrestore(&byt_lock, flags); 1145 1146 return !!(val & BYT_LEVEL); 1147 } 1148 1149 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1150 { 1151 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1152 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1153 unsigned long flags; 1154 u32 old_val; 1155 1156 if (!reg) 1157 return; 1158 1159 raw_spin_lock_irqsave(&byt_lock, flags); 1160 old_val = readl(reg); 1161 if (value) 1162 writel(old_val | BYT_LEVEL, reg); 1163 else 1164 writel(old_val & ~BYT_LEVEL, reg); 1165 raw_spin_unlock_irqrestore(&byt_lock, flags); 1166 } 1167 1168 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1169 { 1170 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1171 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1172 unsigned long flags; 1173 u32 value; 1174 1175 if (!reg) 1176 return -EINVAL; 1177 1178 raw_spin_lock_irqsave(&byt_lock, flags); 1179 value = readl(reg); 1180 raw_spin_unlock_irqrestore(&byt_lock, flags); 1181 1182 if (!(value & BYT_OUTPUT_EN)) 1183 return GPIO_LINE_DIRECTION_OUT; 1184 if (!(value & BYT_INPUT_EN)) 1185 return GPIO_LINE_DIRECTION_IN; 1186 1187 return -EINVAL; 1188 } 1189 1190 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1191 { 1192 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1193 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1194 unsigned long flags; 1195 u32 reg; 1196 1197 raw_spin_lock_irqsave(&byt_lock, flags); 1198 1199 reg = readl(val_reg); 1200 reg &= ~BYT_DIR_MASK; 1201 reg |= BYT_OUTPUT_EN; 1202 writel(reg, val_reg); 1203 1204 raw_spin_unlock_irqrestore(&byt_lock, flags); 1205 return 0; 1206 } 1207 1208 /* 1209 * Note despite the temptation this MUST NOT be converted into a call to 1210 * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this 1211 * MUST be done as a single BYT_VAL_REG register write. 1212 * See the commit message of the commit adding this comment for details. 1213 */ 1214 static int byt_gpio_direction_output(struct gpio_chip *chip, 1215 unsigned int offset, int value) 1216 { 1217 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1218 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1219 unsigned long flags; 1220 u32 reg; 1221 1222 raw_spin_lock_irqsave(&byt_lock, flags); 1223 1224 byt_gpio_direct_irq_check(vg, offset); 1225 1226 reg = readl(val_reg); 1227 reg &= ~BYT_DIR_MASK; 1228 if (value) 1229 reg |= BYT_LEVEL; 1230 else 1231 reg &= ~BYT_LEVEL; 1232 1233 writel(reg, val_reg); 1234 1235 raw_spin_unlock_irqrestore(&byt_lock, flags); 1236 return 0; 1237 } 1238 1239 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1240 { 1241 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1242 int i; 1243 u32 conf0, val; 1244 1245 for (i = 0; i < vg->soc->npins; i++) { 1246 const struct intel_community *comm; 1247 const char *pull_str = NULL; 1248 const char *pull = NULL; 1249 void __iomem *reg; 1250 unsigned long flags; 1251 const char *label; 1252 unsigned int pin; 1253 1254 raw_spin_lock_irqsave(&byt_lock, flags); 1255 pin = vg->soc->pins[i].number; 1256 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1257 if (!reg) { 1258 seq_printf(s, 1259 "Could not retrieve pin %i conf0 reg\n", 1260 pin); 1261 raw_spin_unlock_irqrestore(&byt_lock, flags); 1262 continue; 1263 } 1264 conf0 = readl(reg); 1265 1266 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1267 if (!reg) { 1268 seq_printf(s, 1269 "Could not retrieve pin %i val reg\n", pin); 1270 raw_spin_unlock_irqrestore(&byt_lock, flags); 1271 continue; 1272 } 1273 val = readl(reg); 1274 raw_spin_unlock_irqrestore(&byt_lock, flags); 1275 1276 comm = byt_get_community(vg, pin); 1277 if (!comm) { 1278 seq_printf(s, 1279 "Could not get community for pin %i\n", pin); 1280 continue; 1281 } 1282 label = gpiochip_is_requested(chip, i); 1283 if (!label) 1284 label = "Unrequested"; 1285 1286 switch (conf0 & BYT_PULL_ASSIGN_MASK) { 1287 case BYT_PULL_ASSIGN_UP: 1288 pull = "up"; 1289 break; 1290 case BYT_PULL_ASSIGN_DOWN: 1291 pull = "down"; 1292 break; 1293 } 1294 1295 switch (conf0 & BYT_PULL_STR_MASK) { 1296 case BYT_PULL_STR_2K: 1297 pull_str = "2k"; 1298 break; 1299 case BYT_PULL_STR_10K: 1300 pull_str = "10k"; 1301 break; 1302 case BYT_PULL_STR_20K: 1303 pull_str = "20k"; 1304 break; 1305 case BYT_PULL_STR_40K: 1306 pull_str = "40k"; 1307 break; 1308 } 1309 1310 seq_printf(s, 1311 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", 1312 pin, 1313 label, 1314 val & BYT_INPUT_EN ? " " : "in", 1315 val & BYT_OUTPUT_EN ? " " : "out", 1316 val & BYT_LEVEL ? "hi" : "lo", 1317 comm->pad_map[i], comm->pad_map[i] * 16, 1318 conf0 & 0x7, 1319 conf0 & BYT_TRIG_NEG ? " fall" : " ", 1320 conf0 & BYT_TRIG_POS ? " rise" : " ", 1321 conf0 & BYT_TRIG_LVL ? " level" : " "); 1322 1323 if (pull && pull_str) 1324 seq_printf(s, " %-4s %-3s", pull, pull_str); 1325 else 1326 seq_puts(s, " "); 1327 1328 if (conf0 & BYT_IODEN) 1329 seq_puts(s, " open-drain"); 1330 1331 seq_puts(s, "\n"); 1332 } 1333 } 1334 1335 static const struct gpio_chip byt_gpio_chip = { 1336 .owner = THIS_MODULE, 1337 .request = gpiochip_generic_request, 1338 .free = gpiochip_generic_free, 1339 .get_direction = byt_gpio_get_direction, 1340 .direction_input = byt_gpio_direction_input, 1341 .direction_output = byt_gpio_direction_output, 1342 .get = byt_gpio_get, 1343 .set = byt_gpio_set, 1344 .set_config = gpiochip_generic_config, 1345 .dbg_show = byt_gpio_dbg_show, 1346 }; 1347 1348 static void byt_irq_ack(struct irq_data *d) 1349 { 1350 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1351 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1352 unsigned int offset = irqd_to_hwirq(d); 1353 void __iomem *reg; 1354 1355 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG); 1356 if (!reg) 1357 return; 1358 1359 raw_spin_lock(&byt_lock); 1360 writel(BIT(offset % 32), reg); 1361 raw_spin_unlock(&byt_lock); 1362 } 1363 1364 static void byt_irq_mask(struct irq_data *d) 1365 { 1366 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1367 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1368 1369 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d)); 1370 } 1371 1372 static void byt_irq_unmask(struct irq_data *d) 1373 { 1374 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1375 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1376 unsigned int offset = irqd_to_hwirq(d); 1377 unsigned long flags; 1378 void __iomem *reg; 1379 u32 value; 1380 1381 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1382 if (!reg) 1383 return; 1384 1385 raw_spin_lock_irqsave(&byt_lock, flags); 1386 value = readl(reg); 1387 1388 switch (irqd_get_trigger_type(d)) { 1389 case IRQ_TYPE_LEVEL_HIGH: 1390 value |= BYT_TRIG_LVL; 1391 fallthrough; 1392 case IRQ_TYPE_EDGE_RISING: 1393 value |= BYT_TRIG_POS; 1394 break; 1395 case IRQ_TYPE_LEVEL_LOW: 1396 value |= BYT_TRIG_LVL; 1397 fallthrough; 1398 case IRQ_TYPE_EDGE_FALLING: 1399 value |= BYT_TRIG_NEG; 1400 break; 1401 case IRQ_TYPE_EDGE_BOTH: 1402 value |= (BYT_TRIG_NEG | BYT_TRIG_POS); 1403 break; 1404 } 1405 1406 writel(value, reg); 1407 1408 raw_spin_unlock_irqrestore(&byt_lock, flags); 1409 } 1410 1411 static int byt_irq_type(struct irq_data *d, unsigned int type) 1412 { 1413 struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1414 u32 offset = irqd_to_hwirq(d); 1415 u32 value; 1416 unsigned long flags; 1417 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 1418 1419 if (!reg || offset >= vg->chip.ngpio) 1420 return -EINVAL; 1421 1422 raw_spin_lock_irqsave(&byt_lock, flags); 1423 value = readl(reg); 1424 1425 WARN(value & BYT_DIRECT_IRQ_EN, 1426 "Bad pad config for io mode, force direct_irq_en bit clearing"); 1427 1428 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 1429 * are used to indicate high and low level triggering 1430 */ 1431 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 1432 BYT_TRIG_LVL); 1433 /* Enable glitch filtering */ 1434 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK | 1435 BYT_GLITCH_F_FAST_CLK; 1436 1437 writel(value, reg); 1438 1439 if (type & IRQ_TYPE_EDGE_BOTH) 1440 irq_set_handler_locked(d, handle_edge_irq); 1441 else if (type & IRQ_TYPE_LEVEL_MASK) 1442 irq_set_handler_locked(d, handle_level_irq); 1443 1444 raw_spin_unlock_irqrestore(&byt_lock, flags); 1445 1446 return 0; 1447 } 1448 1449 static void byt_gpio_irq_handler(struct irq_desc *desc) 1450 { 1451 struct irq_data *data = irq_desc_get_irq_data(desc); 1452 struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc)); 1453 struct irq_chip *chip = irq_data_get_irq_chip(data); 1454 u32 base, pin; 1455 void __iomem *reg; 1456 unsigned long pending; 1457 1458 /* check from GPIO controller which pin triggered the interrupt */ 1459 for (base = 0; base < vg->chip.ngpio; base += 32) { 1460 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1461 1462 if (!reg) { 1463 dev_warn(vg->dev, 1464 "Pin %i: could not retrieve interrupt status register\n", 1465 base); 1466 continue; 1467 } 1468 1469 raw_spin_lock(&byt_lock); 1470 pending = readl(reg); 1471 raw_spin_unlock(&byt_lock); 1472 for_each_set_bit(pin, &pending, 32) 1473 generic_handle_domain_irq(vg->chip.irq.domain, base + pin); 1474 } 1475 chip->irq_eoi(data); 1476 } 1477 1478 static void byt_init_irq_valid_mask(struct gpio_chip *chip, 1479 unsigned long *valid_mask, 1480 unsigned int ngpios) 1481 { 1482 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1483 void __iomem *reg; 1484 u32 value; 1485 int i; 1486 1487 /* 1488 * Clear interrupt triggers for all pins that are GPIOs and 1489 * do not use direct IRQ mode. This will prevent spurious 1490 * interrupts from misconfigured pins. 1491 */ 1492 for (i = 0; i < vg->soc->npins; i++) { 1493 unsigned int pin = vg->soc->pins[i].number; 1494 1495 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1496 if (!reg) { 1497 dev_warn(vg->dev, 1498 "Pin %i: could not retrieve conf0 register\n", 1499 i); 1500 continue; 1501 } 1502 1503 value = readl(reg); 1504 if (value & BYT_DIRECT_IRQ_EN) { 1505 clear_bit(i, valid_mask); 1506 dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i); 1507 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { 1508 byt_gpio_clear_triggering(vg, i); 1509 dev_dbg(vg->dev, "disabling GPIO %d\n", i); 1510 } 1511 } 1512 } 1513 1514 static int byt_gpio_irq_init_hw(struct gpio_chip *chip) 1515 { 1516 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1517 void __iomem *reg; 1518 u32 base, value; 1519 1520 /* clear interrupt status trigger registers */ 1521 for (base = 0; base < vg->soc->npins; base += 32) { 1522 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1523 1524 if (!reg) { 1525 dev_warn(vg->dev, 1526 "Pin %i: could not retrieve irq status reg\n", 1527 base); 1528 continue; 1529 } 1530 1531 writel(0xffffffff, reg); 1532 /* make sure trigger bits are cleared, if not then a pin 1533 might be misconfigured in bios */ 1534 value = readl(reg); 1535 if (value) 1536 dev_err(vg->dev, 1537 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n", 1538 base / 32, value); 1539 } 1540 1541 return 0; 1542 } 1543 1544 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip) 1545 { 1546 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1547 struct device *dev = vg->dev; 1548 int ret; 1549 1550 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins); 1551 if (ret) 1552 dev_err(dev, "failed to add GPIO pin range\n"); 1553 1554 return ret; 1555 } 1556 1557 static int byt_gpio_probe(struct intel_pinctrl *vg) 1558 { 1559 struct platform_device *pdev = to_platform_device(vg->dev); 1560 struct gpio_chip *gc; 1561 int irq, ret; 1562 1563 /* Set up gpio chip */ 1564 vg->chip = byt_gpio_chip; 1565 gc = &vg->chip; 1566 gc->label = dev_name(vg->dev); 1567 gc->base = -1; 1568 gc->can_sleep = false; 1569 gc->add_pin_ranges = byt_gpio_add_pin_ranges; 1570 gc->parent = vg->dev; 1571 gc->ngpio = vg->soc->npins; 1572 1573 #ifdef CONFIG_PM_SLEEP 1574 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads), 1575 GFP_KERNEL); 1576 if (!vg->context.pads) 1577 return -ENOMEM; 1578 #endif 1579 1580 /* set up interrupts */ 1581 irq = platform_get_irq_optional(pdev, 0); 1582 if (irq > 0) { 1583 struct gpio_irq_chip *girq; 1584 1585 vg->irqchip.name = "BYT-GPIO", 1586 vg->irqchip.irq_ack = byt_irq_ack, 1587 vg->irqchip.irq_mask = byt_irq_mask, 1588 vg->irqchip.irq_unmask = byt_irq_unmask, 1589 vg->irqchip.irq_set_type = byt_irq_type, 1590 vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED, 1591 1592 girq = &gc->irq; 1593 girq->chip = &vg->irqchip; 1594 girq->init_hw = byt_gpio_irq_init_hw; 1595 girq->init_valid_mask = byt_init_irq_valid_mask; 1596 girq->parent_handler = byt_gpio_irq_handler; 1597 girq->num_parents = 1; 1598 girq->parents = devm_kcalloc(vg->dev, girq->num_parents, 1599 sizeof(*girq->parents), GFP_KERNEL); 1600 if (!girq->parents) 1601 return -ENOMEM; 1602 girq->parents[0] = irq; 1603 girq->default_type = IRQ_TYPE_NONE; 1604 girq->handler = handle_bad_irq; 1605 } 1606 1607 ret = devm_gpiochip_add_data(vg->dev, gc, vg); 1608 if (ret) { 1609 dev_err(vg->dev, "failed adding byt-gpio chip\n"); 1610 return ret; 1611 } 1612 1613 return ret; 1614 } 1615 1616 static int byt_set_soc_data(struct intel_pinctrl *vg, 1617 const struct intel_pinctrl_soc_data *soc) 1618 { 1619 struct platform_device *pdev = to_platform_device(vg->dev); 1620 int i; 1621 1622 vg->soc = soc; 1623 1624 vg->ncommunities = vg->soc->ncommunities; 1625 vg->communities = devm_kcalloc(vg->dev, vg->ncommunities, 1626 sizeof(*vg->communities), GFP_KERNEL); 1627 if (!vg->communities) 1628 return -ENOMEM; 1629 1630 for (i = 0; i < vg->soc->ncommunities; i++) { 1631 struct intel_community *comm = vg->communities + i; 1632 1633 *comm = vg->soc->communities[i]; 1634 1635 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0); 1636 if (IS_ERR(comm->pad_regs)) 1637 return PTR_ERR(comm->pad_regs); 1638 } 1639 1640 return 0; 1641 } 1642 1643 static const struct acpi_device_id byt_gpio_acpi_match[] = { 1644 { "INT33B2", (kernel_ulong_t)byt_soc_data }, 1645 { "INT33FC", (kernel_ulong_t)byt_soc_data }, 1646 { } 1647 }; 1648 1649 static int byt_pinctrl_probe(struct platform_device *pdev) 1650 { 1651 const struct intel_pinctrl_soc_data *soc_data; 1652 struct device *dev = &pdev->dev; 1653 struct intel_pinctrl *vg; 1654 int ret; 1655 1656 soc_data = intel_pinctrl_get_soc_data(pdev); 1657 if (IS_ERR(soc_data)) 1658 return PTR_ERR(soc_data); 1659 1660 vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL); 1661 if (!vg) 1662 return -ENOMEM; 1663 1664 vg->dev = dev; 1665 ret = byt_set_soc_data(vg, soc_data); 1666 if (ret) { 1667 dev_err(dev, "failed to set soc data\n"); 1668 return ret; 1669 } 1670 1671 vg->pctldesc = byt_pinctrl_desc; 1672 vg->pctldesc.name = dev_name(dev); 1673 vg->pctldesc.pins = vg->soc->pins; 1674 vg->pctldesc.npins = vg->soc->npins; 1675 1676 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg); 1677 if (IS_ERR(vg->pctldev)) { 1678 dev_err(dev, "failed to register pinctrl driver\n"); 1679 return PTR_ERR(vg->pctldev); 1680 } 1681 1682 ret = byt_gpio_probe(vg); 1683 if (ret) 1684 return ret; 1685 1686 platform_set_drvdata(pdev, vg); 1687 pm_runtime_enable(dev); 1688 1689 return 0; 1690 } 1691 1692 #ifdef CONFIG_PM_SLEEP 1693 static int byt_gpio_suspend(struct device *dev) 1694 { 1695 struct intel_pinctrl *vg = dev_get_drvdata(dev); 1696 unsigned long flags; 1697 int i; 1698 1699 raw_spin_lock_irqsave(&byt_lock, flags); 1700 1701 for (i = 0; i < vg->soc->npins; i++) { 1702 void __iomem *reg; 1703 u32 value; 1704 unsigned int pin = vg->soc->pins[i].number; 1705 1706 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1707 if (!reg) { 1708 dev_warn(vg->dev, 1709 "Pin %i: could not retrieve conf0 register\n", 1710 i); 1711 continue; 1712 } 1713 value = readl(reg) & BYT_CONF0_RESTORE_MASK; 1714 vg->context.pads[i].conf0 = value; 1715 1716 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1717 value = readl(reg) & BYT_VAL_RESTORE_MASK; 1718 vg->context.pads[i].val = value; 1719 } 1720 1721 raw_spin_unlock_irqrestore(&byt_lock, flags); 1722 return 0; 1723 } 1724 1725 static int byt_gpio_resume(struct device *dev) 1726 { 1727 struct intel_pinctrl *vg = dev_get_drvdata(dev); 1728 unsigned long flags; 1729 int i; 1730 1731 raw_spin_lock_irqsave(&byt_lock, flags); 1732 1733 for (i = 0; i < vg->soc->npins; i++) { 1734 void __iomem *reg; 1735 u32 value; 1736 unsigned int pin = vg->soc->pins[i].number; 1737 1738 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1739 if (!reg) { 1740 dev_warn(vg->dev, 1741 "Pin %i: could not retrieve conf0 register\n", 1742 i); 1743 continue; 1744 } 1745 value = readl(reg); 1746 if ((value & BYT_CONF0_RESTORE_MASK) != 1747 vg->context.pads[i].conf0) { 1748 value &= ~BYT_CONF0_RESTORE_MASK; 1749 value |= vg->context.pads[i].conf0; 1750 writel(value, reg); 1751 dev_info(dev, "restored pin %d conf0 %#08x", i, value); 1752 } 1753 1754 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1755 value = readl(reg); 1756 if ((value & BYT_VAL_RESTORE_MASK) != 1757 vg->context.pads[i].val) { 1758 u32 v; 1759 1760 v = value & ~BYT_VAL_RESTORE_MASK; 1761 v |= vg->context.pads[i].val; 1762 if (v != value) { 1763 writel(v, reg); 1764 dev_dbg(dev, "restored pin %d val %#08x\n", 1765 i, v); 1766 } 1767 } 1768 } 1769 1770 raw_spin_unlock_irqrestore(&byt_lock, flags); 1771 return 0; 1772 } 1773 #endif 1774 1775 #ifdef CONFIG_PM 1776 static int byt_gpio_runtime_suspend(struct device *dev) 1777 { 1778 return 0; 1779 } 1780 1781 static int byt_gpio_runtime_resume(struct device *dev) 1782 { 1783 return 0; 1784 } 1785 #endif 1786 1787 static const struct dev_pm_ops byt_gpio_pm_ops = { 1788 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) 1789 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, 1790 NULL) 1791 }; 1792 1793 static struct platform_driver byt_gpio_driver = { 1794 .probe = byt_pinctrl_probe, 1795 .driver = { 1796 .name = "byt_gpio", 1797 .pm = &byt_gpio_pm_ops, 1798 .acpi_match_table = byt_gpio_acpi_match, 1799 .suppress_bind_attrs = true, 1800 }, 1801 }; 1802 1803 static int __init byt_gpio_init(void) 1804 { 1805 return platform_driver_register(&byt_gpio_driver); 1806 } 1807 subsys_initcall(byt_gpio_init); 1808