1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Alder Lake PCH pinctrl/GPIO driver 4 * 5 * Copyright (C) 2020, Intel Corporation 6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7 */ 8 9 #include <linux/mod_devicetable.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 13 #include <linux/pinctrl/pinctrl.h> 14 15 #include "pinctrl-intel.h" 16 17 #define ADL_PAD_OWN 0x0a0 18 #define ADL_PADCFGLOCK 0x110 19 #define ADL_HOSTSW_OWN 0x150 20 #define ADL_GPI_IS 0x200 21 #define ADL_GPI_IE 0x220 22 23 #define ADL_GPP(r, s, e, g) \ 24 { \ 25 .reg_num = (r), \ 26 .base = (s), \ 27 .size = ((e) - (s) + 1), \ 28 .gpio_base = (g), \ 29 } 30 31 #define ADL_COMMUNITY(b, s, e, g) \ 32 { \ 33 .barno = (b), \ 34 .padown_offset = ADL_PAD_OWN, \ 35 .padcfglock_offset = ADL_PADCFGLOCK, \ 36 .hostown_offset = ADL_HOSTSW_OWN, \ 37 .is_offset = ADL_GPI_IS, \ 38 .ie_offset = ADL_GPI_IE, \ 39 .pin_base = (s), \ 40 .npins = ((e) - (s) + 1), \ 41 .gpps = (g), \ 42 .ngpps = ARRAY_SIZE(g), \ 43 } 44 45 /* Alder Lake-S */ 46 static const struct pinctrl_pin_desc adls_pins[] = { 47 /* GPP_I */ 48 PINCTRL_PIN(0, "EXT_PWR_GATEB"), 49 PINCTRL_PIN(1, "DDSP_HPD_1"), 50 PINCTRL_PIN(2, "DDSP_HPD_2"), 51 PINCTRL_PIN(3, "DDSP_HPD_3"), 52 PINCTRL_PIN(4, "DDSP_HPD_4"), 53 PINCTRL_PIN(5, "DDPB_CTRLCLK"), 54 PINCTRL_PIN(6, "DDPB_CTRLDATA"), 55 PINCTRL_PIN(7, "DDPC_CTRLCLK"), 56 PINCTRL_PIN(8, "DDPC_CTRLDATA"), 57 PINCTRL_PIN(9, "GSPI0_CS1B"), 58 PINCTRL_PIN(10, "GSPI1_CS1B"), 59 PINCTRL_PIN(11, "USB2_OCB_4"), 60 PINCTRL_PIN(12, "USB2_OCB_5"), 61 PINCTRL_PIN(13, "USB2_OCB_6"), 62 PINCTRL_PIN(14, "USB2_OCB_7"), 63 PINCTRL_PIN(15, "GSPI0_CS0B"), 64 PINCTRL_PIN(16, "GSPI0_CLK"), 65 PINCTRL_PIN(17, "GSPI0_MISO"), 66 PINCTRL_PIN(18, "GSPI0_MOSI"), 67 PINCTRL_PIN(19, "GSPI1_CS0B"), 68 PINCTRL_PIN(20, "GSPI1_CLK"), 69 PINCTRL_PIN(21, "GSPI1_MISO"), 70 PINCTRL_PIN(22, "GSPI1_MOSI"), 71 PINCTRL_PIN(23, "GSPI0_CLK_LOOPBK"), 72 PINCTRL_PIN(24, "GSPI1_CLK_LOOPBK"), 73 /* GPP_R */ 74 PINCTRL_PIN(25, "HDA_BCLK"), 75 PINCTRL_PIN(26, "HDA_SYNC"), 76 PINCTRL_PIN(27, "HDA_SDO"), 77 PINCTRL_PIN(28, "HDA_SDI_0"), 78 PINCTRL_PIN(29, "HDA_RSTB"), 79 PINCTRL_PIN(30, "HDA_SDI_1"), 80 PINCTRL_PIN(31, "GPP_R_6"), 81 PINCTRL_PIN(32, "GPP_R_7"), 82 PINCTRL_PIN(33, "GPP_R_8"), 83 PINCTRL_PIN(34, "DDSP_HPD_A"), 84 PINCTRL_PIN(35, "DDSP_HPD_B"), 85 PINCTRL_PIN(36, "DDSP_HPD_C"), 86 PINCTRL_PIN(37, "ISH_SPI_CSB"), 87 PINCTRL_PIN(38, "ISH_SPI_CLK"), 88 PINCTRL_PIN(39, "ISH_SPI_MISO"), 89 PINCTRL_PIN(40, "ISH_SPI_MOSI"), 90 PINCTRL_PIN(41, "DDP1_CTRLCLK"), 91 PINCTRL_PIN(42, "DDP1_CTRLDATA"), 92 PINCTRL_PIN(43, "DDP2_CTRLCLK"), 93 PINCTRL_PIN(44, "DDP2_CTRLDATA"), 94 PINCTRL_PIN(45, "DDPA_CTRLCLK"), 95 PINCTRL_PIN(46, "DDPA_CTRLDATA"), 96 PINCTRL_PIN(47, "GSPI2_CLK_LOOPBK"), 97 /* GPP_J */ 98 PINCTRL_PIN(48, "CNV_PA_BLANKING"), 99 PINCTRL_PIN(49, "CPU_C10_GATEB"), 100 PINCTRL_PIN(50, "CNV_BRI_DT"), 101 PINCTRL_PIN(51, "CNV_BRI_RSP"), 102 PINCTRL_PIN(52, "CNV_RGI_DT"), 103 PINCTRL_PIN(53, "CNV_RGI_RSP"), 104 PINCTRL_PIN(54, "CNV_MFUART2_RXD"), 105 PINCTRL_PIN(55, "CNV_MFUART2_TXD"), 106 PINCTRL_PIN(56, "SRCCLKREQB_16"), 107 PINCTRL_PIN(57, "SRCCLKREQB_17"), 108 PINCTRL_PIN(58, "BSSB_LS_RX"), 109 PINCTRL_PIN(59, "BSSB_LS_TX"), 110 /* vGPIO */ 111 PINCTRL_PIN(60, "CNV_BTEN"), 112 PINCTRL_PIN(61, "CNV_BT_HOST_WAKEB"), 113 PINCTRL_PIN(62, "CNV_BT_IF_SELECT"), 114 PINCTRL_PIN(63, "vCNV_BT_UART_TXD"), 115 PINCTRL_PIN(64, "vCNV_BT_UART_RXD"), 116 PINCTRL_PIN(65, "vCNV_BT_UART_CTS_B"), 117 PINCTRL_PIN(66, "vCNV_BT_UART_RTS_B"), 118 PINCTRL_PIN(67, "vCNV_MFUART1_TXD"), 119 PINCTRL_PIN(68, "vCNV_MFUART1_RXD"), 120 PINCTRL_PIN(69, "vCNV_MFUART1_CTS_B"), 121 PINCTRL_PIN(70, "vCNV_MFUART1_RTS_B"), 122 PINCTRL_PIN(71, "vUART0_TXD"), 123 PINCTRL_PIN(72, "vUART0_RXD"), 124 PINCTRL_PIN(73, "vUART0_CTS_B"), 125 PINCTRL_PIN(74, "vUART0_RTS_B"), 126 PINCTRL_PIN(75, "vISH_UART0_TXD"), 127 PINCTRL_PIN(76, "vISH_UART0_RXD"), 128 PINCTRL_PIN(77, "vISH_UART0_CTS_B"), 129 PINCTRL_PIN(78, "vISH_UART0_RTS_B"), 130 PINCTRL_PIN(79, "vCNV_BT_I2S_BCLK"), 131 PINCTRL_PIN(80, "vCNV_BT_I2S_WS_SYNC"), 132 PINCTRL_PIN(81, "vCNV_BT_I2S_SDO"), 133 PINCTRL_PIN(82, "vCNV_BT_I2S_SDI"), 134 PINCTRL_PIN(83, "vI2S2_SCLK"), 135 PINCTRL_PIN(84, "vI2S2_SFRM"), 136 PINCTRL_PIN(85, "vI2S2_TXD"), 137 PINCTRL_PIN(86, "vI2S2_RXD"), 138 /* vGPIO_0 */ 139 PINCTRL_PIN(87, "ESPI_USB_OCB_0"), 140 PINCTRL_PIN(88, "ESPI_USB_OCB_1"), 141 PINCTRL_PIN(89, "ESPI_USB_OCB_2"), 142 PINCTRL_PIN(90, "ESPI_USB_OCB_3"), 143 PINCTRL_PIN(91, "USB_CPU_OCB_0"), 144 PINCTRL_PIN(92, "USB_CPU_OCB_1"), 145 PINCTRL_PIN(93, "USB_CPU_OCB_2"), 146 PINCTRL_PIN(94, "USB_CPU_OCB_3"), 147 /* GPP_B */ 148 PINCTRL_PIN(95, "PCIE_LNK_DOWN"), 149 PINCTRL_PIN(96, "ISH_UART0_RTSB"), 150 PINCTRL_PIN(97, "VRALERTB"), 151 PINCTRL_PIN(98, "CPU_GP_2"), 152 PINCTRL_PIN(99, "CPU_GP_3"), 153 PINCTRL_PIN(100, "SX_EXIT_HOLDOFFB"), 154 PINCTRL_PIN(101, "CLKOUT_48"), 155 PINCTRL_PIN(102, "ISH_GP_7"), 156 PINCTRL_PIN(103, "ISH_GP_0"), 157 PINCTRL_PIN(104, "ISH_GP_1"), 158 PINCTRL_PIN(105, "ISH_GP_2"), 159 PINCTRL_PIN(106, "I2S_MCLK"), 160 PINCTRL_PIN(107, "SLP_S0B"), 161 PINCTRL_PIN(108, "PLTRSTB"), 162 PINCTRL_PIN(109, "SPKR"), 163 PINCTRL_PIN(110, "ISH_GP_3"), 164 PINCTRL_PIN(111, "ISH_GP_4"), 165 PINCTRL_PIN(112, "ISH_GP_5"), 166 PINCTRL_PIN(113, "PMCALERTB"), 167 PINCTRL_PIN(114, "FUSA_DIAGTEST_EN"), 168 PINCTRL_PIN(115, "FUSA_DIAGTEST_MODE"), 169 PINCTRL_PIN(116, "GPP_B_21"), 170 PINCTRL_PIN(117, "GPP_B_22"), 171 PINCTRL_PIN(118, "SML1ALERTB"), 172 /* GPP_G */ 173 PINCTRL_PIN(119, "GPP_G_0"), 174 PINCTRL_PIN(120, "GPP_G_1"), 175 PINCTRL_PIN(121, "DNX_FORCE_RELOAD"), 176 PINCTRL_PIN(122, "GMII_MDC_0"), 177 PINCTRL_PIN(123, "GMII_MDIO_0"), 178 PINCTRL_PIN(124, "SLP_DRAMB"), 179 PINCTRL_PIN(125, "GPP_G_6"), 180 PINCTRL_PIN(126, "GPP_G_7"), 181 /* GPP_H */ 182 PINCTRL_PIN(127, "SRCCLKREQB_18"), 183 PINCTRL_PIN(128, "GPP_H_1"), 184 PINCTRL_PIN(129, "SRCCLKREQB_8"), 185 PINCTRL_PIN(130, "SRCCLKREQB_9"), 186 PINCTRL_PIN(131, "SRCCLKREQB_10"), 187 PINCTRL_PIN(132, "SRCCLKREQB_11"), 188 PINCTRL_PIN(133, "SRCCLKREQB_12"), 189 PINCTRL_PIN(134, "SRCCLKREQB_13"), 190 PINCTRL_PIN(135, "SRCCLKREQB_14"), 191 PINCTRL_PIN(136, "SRCCLKREQB_15"), 192 PINCTRL_PIN(137, "SML2CLK"), 193 PINCTRL_PIN(138, "SML2DATA"), 194 PINCTRL_PIN(139, "SML2ALERTB"), 195 PINCTRL_PIN(140, "SML3CLK"), 196 PINCTRL_PIN(141, "SML3DATA"), 197 PINCTRL_PIN(142, "SML3ALERTB"), 198 PINCTRL_PIN(143, "SML4CLK"), 199 PINCTRL_PIN(144, "SML4DATA"), 200 PINCTRL_PIN(145, "SML4ALERTB"), 201 PINCTRL_PIN(146, "ISH_I2C0_SDA"), 202 PINCTRL_PIN(147, "ISH_I2C0_SCL"), 203 PINCTRL_PIN(148, "ISH_I2C1_SDA"), 204 PINCTRL_PIN(149, "ISH_I2C1_SCL"), 205 PINCTRL_PIN(150, "TIME_SYNC_0"), 206 /* SPI0 */ 207 PINCTRL_PIN(151, "SPI0_IO_2"), 208 PINCTRL_PIN(152, "SPI0_IO_3"), 209 PINCTRL_PIN(153, "SPI0_MOSI_IO_0"), 210 PINCTRL_PIN(154, "SPI0_MISO_IO_1"), 211 PINCTRL_PIN(155, "SPI0_TPM_CSB"), 212 PINCTRL_PIN(156, "SPI0_FLASH_0_CSB"), 213 PINCTRL_PIN(157, "SPI0_FLASH_1_CSB"), 214 PINCTRL_PIN(158, "SPI0_CLK"), 215 PINCTRL_PIN(159, "SPI0_CLK_LOOPBK"), 216 /* GPP_A */ 217 PINCTRL_PIN(160, "ESPI_IO_0"), 218 PINCTRL_PIN(161, "ESPI_IO_1"), 219 PINCTRL_PIN(162, "ESPI_IO_2"), 220 PINCTRL_PIN(163, "ESPI_IO_3"), 221 PINCTRL_PIN(164, "ESPI_CS0B"), 222 PINCTRL_PIN(165, "ESPI_CLK"), 223 PINCTRL_PIN(166, "ESPI_RESETB"), 224 PINCTRL_PIN(167, "ESPI_CS1B"), 225 PINCTRL_PIN(168, "ESPI_CS2B"), 226 PINCTRL_PIN(169, "ESPI_CS3B"), 227 PINCTRL_PIN(170, "ESPI_ALERT0B"), 228 PINCTRL_PIN(171, "ESPI_ALERT1B"), 229 PINCTRL_PIN(172, "ESPI_ALERT2B"), 230 PINCTRL_PIN(173, "ESPI_ALERT3B"), 231 PINCTRL_PIN(174, "GPP_A_14"), 232 PINCTRL_PIN(175, "ESPI_CLK_LOOPBK"), 233 /* GPP_C */ 234 PINCTRL_PIN(176, "SMBCLK"), 235 PINCTRL_PIN(177, "SMBDATA"), 236 PINCTRL_PIN(178, "SMBALERTB"), 237 PINCTRL_PIN(179, "ISH_UART0_RXD"), 238 PINCTRL_PIN(180, "ISH_UART0_TXD"), 239 PINCTRL_PIN(181, "SML0ALERTB"), 240 PINCTRL_PIN(182, "ISH_I2C2_SDA"), 241 PINCTRL_PIN(183, "ISH_I2C2_SCL"), 242 PINCTRL_PIN(184, "UART0_RXD"), 243 PINCTRL_PIN(185, "UART0_TXD"), 244 PINCTRL_PIN(186, "UART0_RTSB"), 245 PINCTRL_PIN(187, "UART0_CTSB"), 246 PINCTRL_PIN(188, "UART1_RXD"), 247 PINCTRL_PIN(189, "UART1_TXD"), 248 PINCTRL_PIN(190, "UART1_RTSB"), 249 PINCTRL_PIN(191, "UART1_CTSB"), 250 PINCTRL_PIN(192, "I2C0_SDA"), 251 PINCTRL_PIN(193, "I2C0_SCL"), 252 PINCTRL_PIN(194, "I2C1_SDA"), 253 PINCTRL_PIN(195, "I2C1_SCL"), 254 PINCTRL_PIN(196, "UART2_RXD"), 255 PINCTRL_PIN(197, "UART2_TXD"), 256 PINCTRL_PIN(198, "UART2_RTSB"), 257 PINCTRL_PIN(199, "UART2_CTSB"), 258 /* GPP_S */ 259 PINCTRL_PIN(200, "SNDW1_CLK"), 260 PINCTRL_PIN(201, "SNDW1_DATA"), 261 PINCTRL_PIN(202, "SNDW2_CLK"), 262 PINCTRL_PIN(203, "SNDW2_DATA"), 263 PINCTRL_PIN(204, "SNDW3_CLK"), 264 PINCTRL_PIN(205, "SNDW3_DATA"), 265 PINCTRL_PIN(206, "SNDW4_CLK"), 266 PINCTRL_PIN(207, "SNDW4_DATA"), 267 /* GPP_E */ 268 PINCTRL_PIN(208, "SATAXPCIE_0"), 269 PINCTRL_PIN(209, "SATAXPCIE_1"), 270 PINCTRL_PIN(210, "SATAXPCIE_2"), 271 PINCTRL_PIN(211, "CPU_GP_0"), 272 PINCTRL_PIN(212, "SATA_DEVSLP_0"), 273 PINCTRL_PIN(213, "SATA_DEVSLP_1"), 274 PINCTRL_PIN(214, "SATA_DEVSLP_2"), 275 PINCTRL_PIN(215, "CPU_GP_1"), 276 PINCTRL_PIN(216, "SATA_LEDB"), 277 PINCTRL_PIN(217, "USB2_OCB_0"), 278 PINCTRL_PIN(218, "USB2_OCB_1"), 279 PINCTRL_PIN(219, "USB2_OCB_2"), 280 PINCTRL_PIN(220, "USB2_OCB_3"), 281 PINCTRL_PIN(221, "SPI1_CSB"), 282 PINCTRL_PIN(222, "SPI1_CLK"), 283 PINCTRL_PIN(223, "SPI1_MISO_IO_1"), 284 PINCTRL_PIN(224, "SPI1_MOSI_IO_0"), 285 PINCTRL_PIN(225, "SPI1_IO_2"), 286 PINCTRL_PIN(226, "SPI1_IO_3"), 287 PINCTRL_PIN(227, "GPP_E_19"), 288 PINCTRL_PIN(228, "GPP_E_20"), 289 PINCTRL_PIN(229, "ISH_UART0_CTSB"), 290 PINCTRL_PIN(230, "SPI1_CLK_LOOPBK"), 291 /* GPP_K */ 292 PINCTRL_PIN(231, "GSXDOUT"), 293 PINCTRL_PIN(232, "GSXSLOAD"), 294 PINCTRL_PIN(233, "GSXDIN"), 295 PINCTRL_PIN(234, "GSXSRESETB"), 296 PINCTRL_PIN(235, "GSXCLK"), 297 PINCTRL_PIN(236, "ADR_COMPLETE"), 298 PINCTRL_PIN(237, "GPP_K_6"), 299 PINCTRL_PIN(238, "GPP_K_7"), 300 PINCTRL_PIN(239, "CORE_VID_0"), 301 PINCTRL_PIN(240, "CORE_VID_1"), 302 PINCTRL_PIN(241, "GPP_K_10"), 303 PINCTRL_PIN(242, "GPP_K_11"), 304 PINCTRL_PIN(243, "SYS_PWROK"), 305 PINCTRL_PIN(244, "SYS_RESETB"), 306 PINCTRL_PIN(245, "MLK_RSTB"), 307 /* GPP_F */ 308 PINCTRL_PIN(246, "SATAXPCIE_3"), 309 PINCTRL_PIN(247, "SATAXPCIE_4"), 310 PINCTRL_PIN(248, "SATAXPCIE_5"), 311 PINCTRL_PIN(249, "SATAXPCIE_6"), 312 PINCTRL_PIN(250, "SATAXPCIE_7"), 313 PINCTRL_PIN(251, "SATA_DEVSLP_3"), 314 PINCTRL_PIN(252, "SATA_DEVSLP_4"), 315 PINCTRL_PIN(253, "SATA_DEVSLP_5"), 316 PINCTRL_PIN(254, "SATA_DEVSLP_6"), 317 PINCTRL_PIN(255, "SATA_DEVSLP_7"), 318 PINCTRL_PIN(256, "SATA_SCLOCK"), 319 PINCTRL_PIN(257, "SATA_SLOAD"), 320 PINCTRL_PIN(258, "SATA_SDATAOUT1"), 321 PINCTRL_PIN(259, "SATA_SDATAOUT0"), 322 PINCTRL_PIN(260, "PS_ONB"), 323 PINCTRL_PIN(261, "M2_SKT2_CFG_0"), 324 PINCTRL_PIN(262, "M2_SKT2_CFG_1"), 325 PINCTRL_PIN(263, "M2_SKT2_CFG_2"), 326 PINCTRL_PIN(264, "M2_SKT2_CFG_3"), 327 PINCTRL_PIN(265, "L_VDDEN"), 328 PINCTRL_PIN(266, "L_BKLTEN"), 329 PINCTRL_PIN(267, "L_BKLTCTL"), 330 PINCTRL_PIN(268, "VNN_CTRL"), 331 PINCTRL_PIN(269, "GPP_F_23"), 332 /* GPP_D */ 333 PINCTRL_PIN(270, "SRCCLKREQB_0"), 334 PINCTRL_PIN(271, "SRCCLKREQB_1"), 335 PINCTRL_PIN(272, "SRCCLKREQB_2"), 336 PINCTRL_PIN(273, "SRCCLKREQB_3"), 337 PINCTRL_PIN(274, "SML1CLK"), 338 PINCTRL_PIN(275, "I2S2_SFRM"), 339 PINCTRL_PIN(276, "I2S2_TXD"), 340 PINCTRL_PIN(277, "I2S2_RXD"), 341 PINCTRL_PIN(278, "I2S2_SCLK"), 342 PINCTRL_PIN(279, "SML0CLK"), 343 PINCTRL_PIN(280, "SML0DATA"), 344 PINCTRL_PIN(281, "SRCCLKREQB_4"), 345 PINCTRL_PIN(282, "SRCCLKREQB_5"), 346 PINCTRL_PIN(283, "SRCCLKREQB_6"), 347 PINCTRL_PIN(284, "SRCCLKREQB_7"), 348 PINCTRL_PIN(285, "SML1DATA"), 349 PINCTRL_PIN(286, "GSPI3_CS0B"), 350 PINCTRL_PIN(287, "GSPI3_CLK"), 351 PINCTRL_PIN(288, "GSPI3_MISO"), 352 PINCTRL_PIN(289, "GSPI3_MOSI"), 353 PINCTRL_PIN(290, "UART3_RXD"), 354 PINCTRL_PIN(291, "UART3_TXD"), 355 PINCTRL_PIN(292, "UART3_RTSB"), 356 PINCTRL_PIN(293, "UART3_CTSB"), 357 PINCTRL_PIN(294, "GSPI3_CLK_LOOPBK"), 358 /* JTAG */ 359 PINCTRL_PIN(295, "JTAG_TDO"), 360 PINCTRL_PIN(296, "JTAGX"), 361 PINCTRL_PIN(297, "PRDYB"), 362 PINCTRL_PIN(298, "PREQB"), 363 PINCTRL_PIN(299, "JTAG_TDI"), 364 PINCTRL_PIN(300, "JTAG_TMS"), 365 PINCTRL_PIN(301, "JTAG_TCK"), 366 PINCTRL_PIN(302, "DBG_PMODE"), 367 PINCTRL_PIN(303, "CPU_TRSTB"), 368 }; 369 370 static const struct intel_padgroup adls_community0_gpps[] = { 371 ADL_GPP(0, 0, 24, 0), /* GPP_I */ 372 ADL_GPP(1, 25, 47, 32), /* GPP_R */ 373 ADL_GPP(2, 48, 59, 64), /* GPP_J */ 374 ADL_GPP(3, 60, 86, 96), /* vGPIO */ 375 ADL_GPP(4, 87, 94, 128), /* vGPIO_0 */ 376 }; 377 378 static const struct intel_padgroup adls_community1_gpps[] = { 379 ADL_GPP(0, 95, 118, 160), /* GPP_B */ 380 ADL_GPP(1, 119, 126, 192), /* GPP_G */ 381 ADL_GPP(2, 127, 150, 224), /* GPP_H */ 382 }; 383 384 static const struct intel_padgroup adls_community3_gpps[] = { 385 ADL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */ 386 ADL_GPP(1, 160, 175, 256), /* GPP_A */ 387 ADL_GPP(2, 176, 199, 288), /* GPP_C */ 388 }; 389 390 static const struct intel_padgroup adls_community4_gpps[] = { 391 ADL_GPP(0, 200, 207, 320), /* GPP_S */ 392 ADL_GPP(1, 208, 230, 352), /* GPP_E */ 393 ADL_GPP(2, 231, 245, 384), /* GPP_K */ 394 ADL_GPP(3, 246, 269, 416), /* GPP_F */ 395 }; 396 397 static const struct intel_padgroup adls_community5_gpps[] = { 398 ADL_GPP(0, 270, 294, 448), /* GPP_D */ 399 ADL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 400 }; 401 402 static const struct intel_community adls_communities[] = { 403 ADL_COMMUNITY(0, 0, 94, adls_community0_gpps), 404 ADL_COMMUNITY(1, 95, 150, adls_community1_gpps), 405 ADL_COMMUNITY(2, 151, 199, adls_community3_gpps), 406 ADL_COMMUNITY(3, 200, 269, adls_community4_gpps), 407 ADL_COMMUNITY(4, 270, 303, adls_community5_gpps), 408 }; 409 410 static const struct intel_pinctrl_soc_data adls_soc_data = { 411 .pins = adls_pins, 412 .npins = ARRAY_SIZE(adls_pins), 413 .communities = adls_communities, 414 .ncommunities = ARRAY_SIZE(adls_communities), 415 }; 416 417 static const struct acpi_device_id adl_pinctrl_acpi_match[] = { 418 { "INTC1056", (kernel_ulong_t)&adls_soc_data }, 419 { } 420 }; 421 MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match); 422 423 static INTEL_PINCTRL_PM_OPS(adl_pinctrl_pm_ops); 424 425 static struct platform_driver adl_pinctrl_driver = { 426 .probe = intel_pinctrl_probe_by_hid, 427 .driver = { 428 .name = "alderlake-pinctrl", 429 .acpi_match_table = adl_pinctrl_acpi_match, 430 .pm = &adl_pinctrl_pm_ops, 431 }, 432 }; 433 module_platform_driver(adl_pinctrl_driver); 434 435 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 436 MODULE_DESCRIPTION("Intel Alder Lake PCH pinctrl/GPIO driver"); 437 MODULE_LICENSE("GPL v2"); 438