1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2017-2018 NXP 4 */ 5 6 #include <linux/err.h> 7 #include <linux/init.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/pinctrl/pinctrl.h> 11 #include <linux/platform_device.h> 12 13 #include "pinctrl-imx.h" 14 15 enum imx8mm_pads { 16 MX8MM_PAD_RESERVE0 = 0, 17 MX8MM_PAD_RESERVE1 = 1, 18 MX8MM_PAD_RESERVE2 = 2, 19 MX8MM_PAD_RESERVE3 = 3, 20 MX8MM_PAD_RESERVE4 = 4, 21 MX8MM_PAD_RESERVE5 = 5, 22 MX8MM_PAD_RESERVE6 = 6, 23 MX8MM_PAD_RESERVE7 = 7, 24 MX8MM_PAD_RESERVE8 = 8, 25 MX8MM_PAD_RESERVE9 = 9, 26 MX8MM_IOMUXC_GPIO1_IO00 = 10, 27 MX8MM_IOMUXC_GPIO1_IO01 = 11, 28 MX8MM_IOMUXC_GPIO1_IO02 = 12, 29 MX8MM_IOMUXC_GPIO1_IO03 = 13, 30 MX8MM_IOMUXC_GPIO1_IO04 = 14, 31 MX8MM_IOMUXC_GPIO1_IO05 = 15, 32 MX8MM_IOMUXC_GPIO1_IO06 = 16, 33 MX8MM_IOMUXC_GPIO1_IO07 = 17, 34 MX8MM_IOMUXC_GPIO1_IO08 = 18, 35 MX8MM_IOMUXC_GPIO1_IO09 = 19, 36 MX8MM_IOMUXC_GPIO1_IO10 = 20, 37 MX8MM_IOMUXC_GPIO1_IO11 = 21, 38 MX8MM_IOMUXC_GPIO1_IO12 = 22, 39 MX8MM_IOMUXC_GPIO1_IO13 = 23, 40 MX8MM_IOMUXC_GPIO1_IO14 = 24, 41 MX8MM_IOMUXC_GPIO1_IO15 = 25, 42 MX8MM_IOMUXC_ENET_MDC = 26, 43 MX8MM_IOMUXC_ENET_MDIO = 27, 44 MX8MM_IOMUXC_ENET_TD3 = 28, 45 MX8MM_IOMUXC_ENET_TD2 = 29, 46 MX8MM_IOMUXC_ENET_TD1 = 30, 47 MX8MM_IOMUXC_ENET_TD0 = 31, 48 MX8MM_IOMUXC_ENET_TX_CTL = 32, 49 MX8MM_IOMUXC_ENET_TXC = 33, 50 MX8MM_IOMUXC_ENET_RX_CTL = 34, 51 MX8MM_IOMUXC_ENET_RXC = 35, 52 MX8MM_IOMUXC_ENET_RD0 = 36, 53 MX8MM_IOMUXC_ENET_RD1 = 37, 54 MX8MM_IOMUXC_ENET_RD2 = 38, 55 MX8MM_IOMUXC_ENET_RD3 = 39, 56 MX8MM_IOMUXC_SD1_CLK = 40, 57 MX8MM_IOMUXC_SD1_CMD = 41, 58 MX8MM_IOMUXC_SD1_DATA0 = 42, 59 MX8MM_IOMUXC_SD1_DATA1 = 43, 60 MX8MM_IOMUXC_SD1_DATA2 = 44, 61 MX8MM_IOMUXC_SD1_DATA3 = 45, 62 MX8MM_IOMUXC_SD1_DATA4 = 46, 63 MX8MM_IOMUXC_SD1_DATA5 = 47, 64 MX8MM_IOMUXC_SD1_DATA6 = 48, 65 MX8MM_IOMUXC_SD1_DATA7 = 49, 66 MX8MM_IOMUXC_SD1_RESET_B = 50, 67 MX8MM_IOMUXC_SD1_STROBE = 51, 68 MX8MM_IOMUXC_SD2_CD_B = 52, 69 MX8MM_IOMUXC_SD2_CLK = 53, 70 MX8MM_IOMUXC_SD2_CMD = 54, 71 MX8MM_IOMUXC_SD2_DATA0 = 55, 72 MX8MM_IOMUXC_SD2_DATA1 = 56, 73 MX8MM_IOMUXC_SD2_DATA2 = 57, 74 MX8MM_IOMUXC_SD2_DATA3 = 58, 75 MX8MM_IOMUXC_SD2_RESET_B = 59, 76 MX8MM_IOMUXC_SD2_WP = 60, 77 MX8MM_IOMUXC_NAND_ALE = 61, 78 MX8MM_IOMUXC_NAND_CE0 = 62, 79 MX8MM_IOMUXC_NAND_CE1 = 63, 80 MX8MM_IOMUXC_NAND_CE2 = 64, 81 MX8MM_IOMUXC_NAND_CE3 = 65, 82 MX8MM_IOMUXC_NAND_CLE = 66, 83 MX8MM_IOMUXC_NAND_DATA00 = 67, 84 MX8MM_IOMUXC_NAND_DATA01 = 68, 85 MX8MM_IOMUXC_NAND_DATA02 = 69, 86 MX8MM_IOMUXC_NAND_DATA03 = 70, 87 MX8MM_IOMUXC_NAND_DATA04 = 71, 88 MX8MM_IOMUXC_NAND_DATA05 = 72, 89 MX8MM_IOMUXC_NAND_DATA06 = 73, 90 MX8MM_IOMUXC_NAND_DATA07 = 74, 91 MX8MM_IOMUXC_NAND_DQS = 75, 92 MX8MM_IOMUXC_NAND_RE_B = 76, 93 MX8MM_IOMUXC_NAND_READY_B = 77, 94 MX8MM_IOMUXC_NAND_WE_B = 78, 95 MX8MM_IOMUXC_NAND_WP_B = 79, 96 MX8MM_IOMUXC_SAI5_RXFS = 80, 97 MX8MM_IOMUXC_SAI5_RXC = 81, 98 MX8MM_IOMUXC_SAI5_RXD0 = 82, 99 MX8MM_IOMUXC_SAI5_RXD1 = 83, 100 MX8MM_IOMUXC_SAI5_RXD2 = 84, 101 MX8MM_IOMUXC_SAI5_RXD3 = 85, 102 MX8MM_IOMUXC_SAI5_MCLK = 86, 103 MX8MM_IOMUXC_SAI1_RXFS = 87, 104 MX8MM_IOMUXC_SAI1_RXC = 88, 105 MX8MM_IOMUXC_SAI1_RXD0 = 89, 106 MX8MM_IOMUXC_SAI1_RXD1 = 90, 107 MX8MM_IOMUXC_SAI1_RXD2 = 91, 108 MX8MM_IOMUXC_SAI1_RXD3 = 92, 109 MX8MM_IOMUXC_SAI1_RXD4 = 93, 110 MX8MM_IOMUXC_SAI1_RXD5 = 94, 111 MX8MM_IOMUXC_SAI1_RXD6 = 95, 112 MX8MM_IOMUXC_SAI1_RXD7 = 96, 113 MX8MM_IOMUXC_SAI1_TXFS = 97, 114 MX8MM_IOMUXC_SAI1_TXC = 98, 115 MX8MM_IOMUXC_SAI1_TXD0 = 99, 116 MX8MM_IOMUXC_SAI1_TXD1 = 100, 117 MX8MM_IOMUXC_SAI1_TXD2 = 101, 118 MX8MM_IOMUXC_SAI1_TXD3 = 102, 119 MX8MM_IOMUXC_SAI1_TXD4 = 103, 120 MX8MM_IOMUXC_SAI1_TXD5 = 104, 121 MX8MM_IOMUXC_SAI1_TXD6 = 105, 122 MX8MM_IOMUXC_SAI1_TXD7 = 106, 123 MX8MM_IOMUXC_SAI1_MCLK = 107, 124 MX8MM_IOMUXC_SAI2_RXFS = 108, 125 MX8MM_IOMUXC_SAI2_RXC = 109, 126 MX8MM_IOMUXC_SAI2_RXD0 = 110, 127 MX8MM_IOMUXC_SAI2_TXFS = 111, 128 MX8MM_IOMUXC_SAI2_TXC = 112, 129 MX8MM_IOMUXC_SAI2_TXD0 = 113, 130 MX8MM_IOMUXC_SAI2_MCLK = 114, 131 MX8MM_IOMUXC_SAI3_RXFS = 115, 132 MX8MM_IOMUXC_SAI3_RXC = 116, 133 MX8MM_IOMUXC_SAI3_RXD = 117, 134 MX8MM_IOMUXC_SAI3_TXFS = 118, 135 MX8MM_IOMUXC_SAI3_TXC = 119, 136 MX8MM_IOMUXC_SAI3_TXD = 120, 137 MX8MM_IOMUXC_SAI3_MCLK = 121, 138 MX8MM_IOMUXC_SPDIF_TX = 122, 139 MX8MM_IOMUXC_SPDIF_RX = 123, 140 MX8MM_IOMUXC_SPDIF_EXT_CLK = 124, 141 MX8MM_IOMUXC_ECSPI1_SCLK = 125, 142 MX8MM_IOMUXC_ECSPI1_MOSI = 126, 143 MX8MM_IOMUXC_ECSPI1_MISO = 127, 144 MX8MM_IOMUXC_ECSPI1_SS0 = 128, 145 MX8MM_IOMUXC_ECSPI2_SCLK = 129, 146 MX8MM_IOMUXC_ECSPI2_MOSI = 130, 147 MX8MM_IOMUXC_ECSPI2_MISO = 131, 148 MX8MM_IOMUXC_ECSPI2_SS0 = 132, 149 MX8MM_IOMUXC_I2C1_SCL = 133, 150 MX8MM_IOMUXC_I2C1_SDA = 134, 151 MX8MM_IOMUXC_I2C2_SCL = 135, 152 MX8MM_IOMUXC_I2C2_SDA = 136, 153 MX8MM_IOMUXC_I2C3_SCL = 137, 154 MX8MM_IOMUXC_I2C3_SDA = 138, 155 MX8MM_IOMUXC_I2C4_SCL = 139, 156 MX8MM_IOMUXC_I2C4_SDA = 140, 157 MX8MM_IOMUXC_UART1_RXD = 141, 158 MX8MM_IOMUXC_UART1_TXD = 142, 159 MX8MM_IOMUXC_UART2_RXD = 143, 160 MX8MM_IOMUXC_UART2_TXD = 144, 161 MX8MM_IOMUXC_UART3_RXD = 145, 162 MX8MM_IOMUXC_UART3_TXD = 146, 163 MX8MM_IOMUXC_UART4_RXD = 147, 164 MX8MM_IOMUXC_UART4_TXD = 148, 165 }; 166 167 /* Pad names for the pinmux subsystem */ 168 static const struct pinctrl_pin_desc imx8mm_pinctrl_pads[] = { 169 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE0), 170 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE1), 171 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE2), 172 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE3), 173 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE4), 174 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE5), 175 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE6), 176 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE7), 177 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE8), 178 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE9), 179 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO00), 180 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO01), 181 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO02), 182 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO03), 183 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO04), 184 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO05), 185 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO06), 186 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO07), 187 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO08), 188 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO09), 189 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO10), 190 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO11), 191 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO12), 192 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO13), 193 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO14), 194 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO15), 195 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDC), 196 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDIO), 197 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD3), 198 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD2), 199 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD1), 200 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD0), 201 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TX_CTL), 202 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TXC), 203 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RX_CTL), 204 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RXC), 205 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD0), 206 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD1), 207 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD2), 208 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD3), 209 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CLK), 210 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CMD), 211 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA0), 212 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA1), 213 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA2), 214 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA3), 215 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA4), 216 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA5), 217 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA6), 218 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA7), 219 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_RESET_B), 220 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_STROBE), 221 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CD_B), 222 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CLK), 223 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CMD), 224 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA0), 225 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA1), 226 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA2), 227 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA3), 228 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_RESET_B), 229 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_WP), 230 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_ALE), 231 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE0), 232 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE1), 233 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE2), 234 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE3), 235 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CLE), 236 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA00), 237 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA01), 238 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA02), 239 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA03), 240 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA04), 241 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA05), 242 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA06), 243 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA07), 244 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DQS), 245 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_RE_B), 246 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_READY_B), 247 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WE_B), 248 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WP_B), 249 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXFS), 250 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXC), 251 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD0), 252 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD1), 253 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD2), 254 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD3), 255 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_MCLK), 256 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXFS), 257 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXC), 258 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD0), 259 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD1), 260 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD2), 261 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD3), 262 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD4), 263 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD5), 264 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD6), 265 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD7), 266 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXFS), 267 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXC), 268 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD0), 269 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD1), 270 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD2), 271 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD3), 272 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD4), 273 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD5), 274 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD6), 275 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD7), 276 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_MCLK), 277 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXFS), 278 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXC), 279 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXD0), 280 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXFS), 281 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXC), 282 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXD0), 283 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_MCLK), 284 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXFS), 285 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXC), 286 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXD), 287 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXFS), 288 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXC), 289 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXD), 290 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_MCLK), 291 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_TX), 292 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_RX), 293 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_EXT_CLK), 294 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SCLK), 295 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MOSI), 296 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MISO), 297 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SS0), 298 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SCLK), 299 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MOSI), 300 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MISO), 301 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SS0), 302 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SCL), 303 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SDA), 304 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SCL), 305 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SDA), 306 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SCL), 307 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SDA), 308 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SCL), 309 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SDA), 310 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_RXD), 311 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_TXD), 312 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_RXD), 313 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_TXD), 314 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_RXD), 315 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_TXD), 316 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_RXD), 317 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_TXD), 318 }; 319 320 static const struct imx_pinctrl_soc_info imx8mm_pinctrl_info = { 321 .pins = imx8mm_pinctrl_pads, 322 .npins = ARRAY_SIZE(imx8mm_pinctrl_pads), 323 .gpr_compatible = "fsl,imx8mm-iomuxc-gpr", 324 }; 325 326 static const struct of_device_id imx8mm_pinctrl_of_match[] = { 327 { .compatible = "fsl,imx8mm-iomuxc", .data = &imx8mm_pinctrl_info, }, 328 { /* sentinel */ } 329 }; 330 MODULE_DEVICE_TABLE(of, imx8mm_pinctrl_of_match); 331 332 static int imx8mm_pinctrl_probe(struct platform_device *pdev) 333 { 334 return imx_pinctrl_probe(pdev, &imx8mm_pinctrl_info); 335 } 336 337 static struct platform_driver imx8mm_pinctrl_driver = { 338 .driver = { 339 .name = "imx8mm-pinctrl", 340 .of_match_table = imx8mm_pinctrl_of_match, 341 .suppress_bind_attrs = true, 342 }, 343 .probe = imx8mm_pinctrl_probe, 344 }; 345 346 static int __init imx8mm_pinctrl_init(void) 347 { 348 return platform_driver_register(&imx8mm_pinctrl_driver); 349 } 350 arch_initcall(imx8mm_pinctrl_init); 351 352 MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>"); 353 MODULE_DESCRIPTION("NXP i.MX8MM pinctrl driver"); 354 MODULE_LICENSE("GPL v2"); 355