1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/err.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/pinctrl/pinctrl.h> 16 17 #include "pinctrl-imx.h" 18 19 enum imx6ul_pads { 20 MX6UL_PAD_RESERVE0 = 0, 21 MX6UL_PAD_RESERVE1 = 1, 22 MX6UL_PAD_RESERVE2 = 2, 23 MX6UL_PAD_RESERVE3 = 3, 24 MX6UL_PAD_RESERVE4 = 4, 25 MX6UL_PAD_RESERVE5 = 5, 26 MX6UL_PAD_RESERVE6 = 6, 27 MX6UL_PAD_RESERVE7 = 7, 28 MX6UL_PAD_RESERVE8 = 8, 29 MX6UL_PAD_RESERVE9 = 9, 30 MX6UL_PAD_RESERVE10 = 10, 31 MX6UL_PAD_SNVS_TAMPER4 = 11, 32 MX6UL_PAD_RESERVE12 = 12, 33 MX6UL_PAD_RESERVE13 = 13, 34 MX6UL_PAD_RESERVE14 = 14, 35 MX6UL_PAD_RESERVE15 = 15, 36 MX6UL_PAD_RESERVE16 = 16, 37 MX6UL_PAD_JTAG_MOD = 17, 38 MX6UL_PAD_JTAG_TMS = 18, 39 MX6UL_PAD_JTAG_TDO = 19, 40 MX6UL_PAD_JTAG_TDI = 20, 41 MX6UL_PAD_JTAG_TCK = 21, 42 MX6UL_PAD_JTAG_TRST_B = 22, 43 MX6UL_PAD_GPIO1_IO00 = 23, 44 MX6UL_PAD_GPIO1_IO01 = 24, 45 MX6UL_PAD_GPIO1_IO02 = 25, 46 MX6UL_PAD_GPIO1_IO03 = 26, 47 MX6UL_PAD_GPIO1_IO04 = 27, 48 MX6UL_PAD_GPIO1_IO05 = 28, 49 MX6UL_PAD_GPIO1_IO06 = 29, 50 MX6UL_PAD_GPIO1_IO07 = 30, 51 MX6UL_PAD_GPIO1_IO08 = 31, 52 MX6UL_PAD_GPIO1_IO09 = 32, 53 MX6UL_PAD_UART1_TX_DATA = 33, 54 MX6UL_PAD_UART1_RX_DATA = 34, 55 MX6UL_PAD_UART1_CTS_B = 35, 56 MX6UL_PAD_UART1_RTS_B = 36, 57 MX6UL_PAD_UART2_TX_DATA = 37, 58 MX6UL_PAD_UART2_RX_DATA = 38, 59 MX6UL_PAD_UART2_CTS_B = 39, 60 MX6UL_PAD_UART2_RTS_B = 40, 61 MX6UL_PAD_UART3_TX_DATA = 41, 62 MX6UL_PAD_UART3_RX_DATA = 42, 63 MX6UL_PAD_UART3_CTS_B = 43, 64 MX6UL_PAD_UART3_RTS_B = 44, 65 MX6UL_PAD_UART4_TX_DATA = 45, 66 MX6UL_PAD_UART4_RX_DATA = 46, 67 MX6UL_PAD_UART5_TX_DATA = 47, 68 MX6UL_PAD_UART5_RX_DATA = 48, 69 MX6UL_PAD_ENET1_RX_DATA0 = 49, 70 MX6UL_PAD_ENET1_RX_DATA1 = 50, 71 MX6UL_PAD_ENET1_RX_EN = 51, 72 MX6UL_PAD_ENET1_TX_DATA0 = 52, 73 MX6UL_PAD_ENET1_TX_DATA1 = 53, 74 MX6UL_PAD_ENET1_TX_EN = 54, 75 MX6UL_PAD_ENET1_TX_CLK = 55, 76 MX6UL_PAD_ENET1_RX_ER = 56, 77 MX6UL_PAD_ENET2_RX_DATA0 = 57, 78 MX6UL_PAD_ENET2_RX_DATA1 = 58, 79 MX6UL_PAD_ENET2_RX_EN = 59, 80 MX6UL_PAD_ENET2_TX_DATA0 = 60, 81 MX6UL_PAD_ENET2_TX_DATA1 = 61, 82 MX6UL_PAD_ENET2_TX_EN = 62, 83 MX6UL_PAD_ENET2_TX_CLK = 63, 84 MX6UL_PAD_ENET2_RX_ER = 64, 85 MX6UL_PAD_LCD_CLK = 65, 86 MX6UL_PAD_LCD_ENABLE = 66, 87 MX6UL_PAD_LCD_HSYNC = 67, 88 MX6UL_PAD_LCD_VSYNC = 68, 89 MX6UL_PAD_LCD_RESET = 69, 90 MX6UL_PAD_LCD_DATA00 = 70, 91 MX6UL_PAD_LCD_DATA01 = 71, 92 MX6UL_PAD_LCD_DATA02 = 72, 93 MX6UL_PAD_LCD_DATA03 = 73, 94 MX6UL_PAD_LCD_DATA04 = 74, 95 MX6UL_PAD_LCD_DATA05 = 75, 96 MX6UL_PAD_LCD_DATA06 = 76, 97 MX6UL_PAD_LCD_DATA07 = 77, 98 MX6UL_PAD_LCD_DATA08 = 78, 99 MX6UL_PAD_LCD_DATA09 = 79, 100 MX6UL_PAD_LCD_DATA10 = 80, 101 MX6UL_PAD_LCD_DATA11 = 81, 102 MX6UL_PAD_LCD_DATA12 = 82, 103 MX6UL_PAD_LCD_DATA13 = 83, 104 MX6UL_PAD_LCD_DATA14 = 84, 105 MX6UL_PAD_LCD_DATA15 = 85, 106 MX6UL_PAD_LCD_DATA16 = 86, 107 MX6UL_PAD_LCD_DATA17 = 87, 108 MX6UL_PAD_LCD_DATA18 = 88, 109 MX6UL_PAD_LCD_DATA19 = 89, 110 MX6UL_PAD_LCD_DATA20 = 90, 111 MX6UL_PAD_LCD_DATA21 = 91, 112 MX6UL_PAD_LCD_DATA22 = 92, 113 MX6UL_PAD_LCD_DATA23 = 93, 114 MX6UL_PAD_NAND_RE_B = 94, 115 MX6UL_PAD_NAND_WE_B = 95, 116 MX6UL_PAD_NAND_DATA00 = 96, 117 MX6UL_PAD_NAND_DATA01 = 97, 118 MX6UL_PAD_NAND_DATA02 = 98, 119 MX6UL_PAD_NAND_DATA03 = 99, 120 MX6UL_PAD_NAND_DATA04 = 100, 121 MX6UL_PAD_NAND_DATA05 = 101, 122 MX6UL_PAD_NAND_DATA06 = 102, 123 MX6UL_PAD_NAND_DATA07 = 103, 124 MX6UL_PAD_NAND_ALE = 104, 125 MX6UL_PAD_NAND_WP_B = 105, 126 MX6UL_PAD_NAND_READY_B = 106, 127 MX6UL_PAD_NAND_CE0_B = 107, 128 MX6UL_PAD_NAND_CE1_B = 108, 129 MX6UL_PAD_NAND_CLE = 109, 130 MX6UL_PAD_NAND_DQS = 110, 131 MX6UL_PAD_SD1_CMD = 111, 132 MX6UL_PAD_SD1_CLK = 112, 133 MX6UL_PAD_SD1_DATA0 = 113, 134 MX6UL_PAD_SD1_DATA1 = 114, 135 MX6UL_PAD_SD1_DATA2 = 115, 136 MX6UL_PAD_SD1_DATA3 = 116, 137 MX6UL_PAD_CSI_MCLK = 117, 138 MX6UL_PAD_CSI_PIXCLK = 118, 139 MX6UL_PAD_CSI_VSYNC = 119, 140 MX6UL_PAD_CSI_HSYNC = 120, 141 MX6UL_PAD_CSI_DATA00 = 121, 142 MX6UL_PAD_CSI_DATA01 = 122, 143 MX6UL_PAD_CSI_DATA02 = 123, 144 MX6UL_PAD_CSI_DATA03 = 124, 145 MX6UL_PAD_CSI_DATA04 = 125, 146 MX6UL_PAD_CSI_DATA05 = 126, 147 MX6UL_PAD_CSI_DATA06 = 127, 148 MX6UL_PAD_CSI_DATA07 = 128, 149 }; 150 151 /* Pad names for the pinmux subsystem */ 152 static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = { 153 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0), 154 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE1), 155 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE2), 156 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE3), 157 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE4), 158 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE5), 159 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE6), 160 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE7), 161 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE8), 162 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE9), 163 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE10), 164 IMX_PINCTRL_PIN(MX6UL_PAD_SNVS_TAMPER4), 165 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE12), 166 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE13), 167 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE14), 168 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE15), 169 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE16), 170 IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_MOD), 171 IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TMS), 172 IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDO), 173 IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDI), 174 IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TCK), 175 IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TRST_B), 176 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO00), 177 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO01), 178 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO02), 179 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO03), 180 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO04), 181 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO05), 182 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO06), 183 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO07), 184 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO08), 185 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO09), 186 IMX_PINCTRL_PIN(MX6UL_PAD_UART1_TX_DATA), 187 IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RX_DATA), 188 IMX_PINCTRL_PIN(MX6UL_PAD_UART1_CTS_B), 189 IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RTS_B), 190 IMX_PINCTRL_PIN(MX6UL_PAD_UART2_TX_DATA), 191 IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RX_DATA), 192 IMX_PINCTRL_PIN(MX6UL_PAD_UART2_CTS_B), 193 IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RTS_B), 194 IMX_PINCTRL_PIN(MX6UL_PAD_UART3_TX_DATA), 195 IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RX_DATA), 196 IMX_PINCTRL_PIN(MX6UL_PAD_UART3_CTS_B), 197 IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RTS_B), 198 IMX_PINCTRL_PIN(MX6UL_PAD_UART4_TX_DATA), 199 IMX_PINCTRL_PIN(MX6UL_PAD_UART4_RX_DATA), 200 IMX_PINCTRL_PIN(MX6UL_PAD_UART5_TX_DATA), 201 IMX_PINCTRL_PIN(MX6UL_PAD_UART5_RX_DATA), 202 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA0), 203 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA1), 204 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_EN), 205 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA0), 206 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA1), 207 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_EN), 208 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_CLK), 209 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_ER), 210 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA0), 211 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA1), 212 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_EN), 213 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA0), 214 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA1), 215 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_EN), 216 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_CLK), 217 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_ER), 218 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_CLK), 219 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_ENABLE), 220 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_HSYNC), 221 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_VSYNC), 222 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_RESET), 223 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA00), 224 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA01), 225 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA02), 226 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA03), 227 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA04), 228 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA05), 229 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA06), 230 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA07), 231 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA08), 232 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA09), 233 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA10), 234 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA11), 235 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA12), 236 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA13), 237 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA14), 238 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA15), 239 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA16), 240 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA17), 241 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA18), 242 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA19), 243 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA20), 244 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA21), 245 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA22), 246 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA23), 247 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_RE_B), 248 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WE_B), 249 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA00), 250 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA01), 251 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA02), 252 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA03), 253 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA04), 254 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA05), 255 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA06), 256 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA07), 257 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_ALE), 258 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WP_B), 259 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_READY_B), 260 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE0_B), 261 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE1_B), 262 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CLE), 263 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DQS), 264 IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CMD), 265 IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CLK), 266 IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA0), 267 IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA1), 268 IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA2), 269 IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA3), 270 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_MCLK), 271 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_PIXCLK), 272 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_VSYNC), 273 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_HSYNC), 274 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA00), 275 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA01), 276 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA02), 277 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA03), 278 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA04), 279 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA05), 280 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA06), 281 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07), 282 }; 283 284 static struct imx_pinctrl_soc_info imx6ul_pinctrl_info = { 285 .pins = imx6ul_pinctrl_pads, 286 .npins = ARRAY_SIZE(imx6ul_pinctrl_pads), 287 }; 288 289 static struct of_device_id imx6ul_pinctrl_of_match[] = { 290 { .compatible = "fsl,imx6ul-iomuxc", }, 291 { /* sentinel */ } 292 }; 293 294 static int imx6ul_pinctrl_probe(struct platform_device *pdev) 295 { 296 return imx_pinctrl_probe(pdev, &imx6ul_pinctrl_info); 297 } 298 299 static struct platform_driver imx6ul_pinctrl_driver = { 300 .driver = { 301 .name = "imx6ul-pinctrl", 302 .of_match_table = of_match_ptr(imx6ul_pinctrl_of_match), 303 }, 304 .probe = imx6ul_pinctrl_probe, 305 .remove = imx_pinctrl_remove, 306 }; 307 308 static int __init imx6ul_pinctrl_init(void) 309 { 310 return platform_driver_register(&imx6ul_pinctrl_driver); 311 } 312 arch_initcall(imx6ul_pinctrl_init); 313 314 static void __exit imx6ul_pinctrl_exit(void) 315 { 316 platform_driver_unregister(&imx6ul_pinctrl_driver); 317 } 318 module_exit(imx6ul_pinctrl_exit); 319 320 MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>"); 321 MODULE_DESCRIPTION("Freescale imx6ul pinctrl driver"); 322 MODULE_LICENSE("GPL v2"); 323