1c2b39decSFabio Estevam // SPDX-License-Identifier: GPL-2.0+
2c2b39decSFabio Estevam //
3c2b39decSFabio Estevam // imx50 pinctrl driver based on imx pinmux core
4c2b39decSFabio Estevam //
5c2b39decSFabio Estevam // Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
6c2b39decSFabio Estevam // Copyright (C) 2012 Freescale Semiconductor, Inc.
7c2b39decSFabio Estevam // Copyright (C) 2012 Linaro, Inc.
8edad3b2aSLinus Walleij
9edad3b2aSLinus Walleij #include <linux/err.h>
10edad3b2aSLinus Walleij #include <linux/init.h>
11edad3b2aSLinus Walleij #include <linux/io.h>
12*060f03e9SRob Herring #include <linux/mod_devicetable.h>
13*060f03e9SRob Herring #include <linux/platform_device.h>
14edad3b2aSLinus Walleij #include <linux/pinctrl/pinctrl.h>
15edad3b2aSLinus Walleij
16edad3b2aSLinus Walleij #include "pinctrl-imx.h"
17edad3b2aSLinus Walleij
18edad3b2aSLinus Walleij enum imx50_pads {
19edad3b2aSLinus Walleij MX50_PAD_RESERVE0 = 0,
20edad3b2aSLinus Walleij MX50_PAD_RESERVE1 = 1,
21edad3b2aSLinus Walleij MX50_PAD_RESERVE2 = 2,
22edad3b2aSLinus Walleij MX50_PAD_RESERVE3 = 3,
23edad3b2aSLinus Walleij MX50_PAD_RESERVE4 = 4,
24edad3b2aSLinus Walleij MX50_PAD_RESERVE5 = 5,
25edad3b2aSLinus Walleij MX50_PAD_RESERVE6 = 6,
26edad3b2aSLinus Walleij MX50_PAD_RESERVE7 = 7,
27edad3b2aSLinus Walleij MX50_PAD_KEY_COL0 = 8,
28edad3b2aSLinus Walleij MX50_PAD_KEY_ROW0 = 9,
29edad3b2aSLinus Walleij MX50_PAD_KEY_COL1 = 10,
30edad3b2aSLinus Walleij MX50_PAD_KEY_ROW1 = 11,
31edad3b2aSLinus Walleij MX50_PAD_KEY_COL2 = 12,
32edad3b2aSLinus Walleij MX50_PAD_KEY_ROW2 = 13,
33edad3b2aSLinus Walleij MX50_PAD_KEY_COL3 = 14,
34edad3b2aSLinus Walleij MX50_PAD_KEY_ROW3 = 15,
35edad3b2aSLinus Walleij MX50_PAD_I2C1_SCL = 16,
36edad3b2aSLinus Walleij MX50_PAD_I2C1_SDA = 17,
37edad3b2aSLinus Walleij MX50_PAD_I2C2_SCL = 18,
38edad3b2aSLinus Walleij MX50_PAD_I2C2_SDA = 19,
39edad3b2aSLinus Walleij MX50_PAD_I2C3_SCL = 20,
40edad3b2aSLinus Walleij MX50_PAD_I2C3_SDA = 21,
41edad3b2aSLinus Walleij MX50_PAD_PWM1 = 22,
42edad3b2aSLinus Walleij MX50_PAD_PWM2 = 23,
43edad3b2aSLinus Walleij MX50_PAD_0WIRE = 24,
44edad3b2aSLinus Walleij MX50_PAD_EPITO = 25,
45edad3b2aSLinus Walleij MX50_PAD_WDOG = 26,
46edad3b2aSLinus Walleij MX50_PAD_SSI_TXFS = 27,
47edad3b2aSLinus Walleij MX50_PAD_SSI_TXC = 28,
48edad3b2aSLinus Walleij MX50_PAD_SSI_TXD = 29,
49edad3b2aSLinus Walleij MX50_PAD_SSI_RXD = 30,
50edad3b2aSLinus Walleij MX50_PAD_SSI_RXF = 31,
51edad3b2aSLinus Walleij MX50_PAD_SSI_RXC = 32,
52edad3b2aSLinus Walleij MX50_PAD_UART1_TXD = 33,
53edad3b2aSLinus Walleij MX50_PAD_UART1_RXD = 34,
54edad3b2aSLinus Walleij MX50_PAD_UART1_CTS = 35,
55edad3b2aSLinus Walleij MX50_PAD_UART1_RTS = 36,
56edad3b2aSLinus Walleij MX50_PAD_UART2_TXD = 37,
57edad3b2aSLinus Walleij MX50_PAD_UART2_RXD = 38,
58edad3b2aSLinus Walleij MX50_PAD_UART2_CTS = 39,
59edad3b2aSLinus Walleij MX50_PAD_UART2_RTS = 40,
60edad3b2aSLinus Walleij MX50_PAD_UART3_TXD = 41,
61edad3b2aSLinus Walleij MX50_PAD_UART3_RXD = 42,
62edad3b2aSLinus Walleij MX50_PAD_UART4_TXD = 43,
63edad3b2aSLinus Walleij MX50_PAD_UART4_RXD = 44,
64edad3b2aSLinus Walleij MX50_PAD_CSPI_CLK = 45,
65edad3b2aSLinus Walleij MX50_PAD_CSPI_MOSI = 46,
66edad3b2aSLinus Walleij MX50_PAD_CSPI_MISO = 47,
67edad3b2aSLinus Walleij MX50_PAD_CSPI_SS0 = 48,
68edad3b2aSLinus Walleij MX50_PAD_ECSPI1_CLK = 49,
69edad3b2aSLinus Walleij MX50_PAD_ECSPI1_MOSI = 50,
70edad3b2aSLinus Walleij MX50_PAD_ECSPI1_MISO = 51,
71edad3b2aSLinus Walleij MX50_PAD_ECSPI1_SS0 = 52,
72edad3b2aSLinus Walleij MX50_PAD_ECSPI2_CLK = 53,
73edad3b2aSLinus Walleij MX50_PAD_ECSPI2_MOSI = 54,
74edad3b2aSLinus Walleij MX50_PAD_ECSPI2_MISO = 55,
75edad3b2aSLinus Walleij MX50_PAD_ECSPI2_SS0 = 56,
76edad3b2aSLinus Walleij MX50_PAD_SD1_CLK = 57,
77edad3b2aSLinus Walleij MX50_PAD_SD1_CMD = 58,
78edad3b2aSLinus Walleij MX50_PAD_SD1_D0 = 59,
79edad3b2aSLinus Walleij MX50_PAD_SD1_D1 = 60,
80edad3b2aSLinus Walleij MX50_PAD_SD1_D2 = 61,
81edad3b2aSLinus Walleij MX50_PAD_SD1_D3 = 62,
82edad3b2aSLinus Walleij MX50_PAD_SD2_CLK = 63,
83edad3b2aSLinus Walleij MX50_PAD_SD2_CMD = 64,
84edad3b2aSLinus Walleij MX50_PAD_SD2_D0 = 65,
85edad3b2aSLinus Walleij MX50_PAD_SD2_D1 = 66,
86edad3b2aSLinus Walleij MX50_PAD_SD2_D2 = 67,
87edad3b2aSLinus Walleij MX50_PAD_SD2_D3 = 68,
88edad3b2aSLinus Walleij MX50_PAD_SD2_D4 = 69,
89edad3b2aSLinus Walleij MX50_PAD_SD2_D5 = 70,
90edad3b2aSLinus Walleij MX50_PAD_SD2_D6 = 71,
91edad3b2aSLinus Walleij MX50_PAD_SD2_D7 = 72,
92edad3b2aSLinus Walleij MX50_PAD_SD2_WP = 73,
93edad3b2aSLinus Walleij MX50_PAD_SD2_CD = 74,
94edad3b2aSLinus Walleij MX50_PAD_DISP_D0 = 75,
95edad3b2aSLinus Walleij MX50_PAD_DISP_D1 = 76,
96edad3b2aSLinus Walleij MX50_PAD_DISP_D2 = 77,
97edad3b2aSLinus Walleij MX50_PAD_DISP_D3 = 78,
98edad3b2aSLinus Walleij MX50_PAD_DISP_D4 = 79,
99edad3b2aSLinus Walleij MX50_PAD_DISP_D5 = 80,
100edad3b2aSLinus Walleij MX50_PAD_DISP_D6 = 81,
101edad3b2aSLinus Walleij MX50_PAD_DISP_D7 = 82,
102edad3b2aSLinus Walleij MX50_PAD_DISP_WR = 83,
103edad3b2aSLinus Walleij MX50_PAD_DISP_RD = 84,
104edad3b2aSLinus Walleij MX50_PAD_DISP_RS = 85,
105edad3b2aSLinus Walleij MX50_PAD_DISP_CS = 86,
106edad3b2aSLinus Walleij MX50_PAD_DISP_BUSY = 87,
107edad3b2aSLinus Walleij MX50_PAD_DISP_RESET = 88,
108edad3b2aSLinus Walleij MX50_PAD_SD3_CLK = 89,
109edad3b2aSLinus Walleij MX50_PAD_SD3_CMD = 90,
110edad3b2aSLinus Walleij MX50_PAD_SD3_D0 = 91,
111edad3b2aSLinus Walleij MX50_PAD_SD3_D1 = 92,
112edad3b2aSLinus Walleij MX50_PAD_SD3_D2 = 93,
113edad3b2aSLinus Walleij MX50_PAD_SD3_D3 = 94,
114edad3b2aSLinus Walleij MX50_PAD_SD3_D4 = 95,
115edad3b2aSLinus Walleij MX50_PAD_SD3_D5 = 96,
116edad3b2aSLinus Walleij MX50_PAD_SD3_D6 = 97,
117edad3b2aSLinus Walleij MX50_PAD_SD3_D7 = 98,
118edad3b2aSLinus Walleij MX50_PAD_SD3_WP = 99,
119edad3b2aSLinus Walleij MX50_PAD_DISP_D8 = 100,
120edad3b2aSLinus Walleij MX50_PAD_DISP_D9 = 101,
121edad3b2aSLinus Walleij MX50_PAD_DISP_D10 = 102,
122edad3b2aSLinus Walleij MX50_PAD_DISP_D11 = 103,
123edad3b2aSLinus Walleij MX50_PAD_DISP_D12 = 104,
124edad3b2aSLinus Walleij MX50_PAD_DISP_D13 = 105,
125edad3b2aSLinus Walleij MX50_PAD_DISP_D14 = 106,
126edad3b2aSLinus Walleij MX50_PAD_DISP_D15 = 107,
127edad3b2aSLinus Walleij MX50_PAD_EPDC_D0 = 108,
128edad3b2aSLinus Walleij MX50_PAD_EPDC_D1 = 109,
129edad3b2aSLinus Walleij MX50_PAD_EPDC_D2 = 110,
130edad3b2aSLinus Walleij MX50_PAD_EPDC_D3 = 111,
131edad3b2aSLinus Walleij MX50_PAD_EPDC_D4 = 112,
132edad3b2aSLinus Walleij MX50_PAD_EPDC_D5 = 113,
133edad3b2aSLinus Walleij MX50_PAD_EPDC_D6 = 114,
134edad3b2aSLinus Walleij MX50_PAD_EPDC_D7 = 115,
135edad3b2aSLinus Walleij MX50_PAD_EPDC_D8 = 116,
136edad3b2aSLinus Walleij MX50_PAD_EPDC_D9 = 117,
137edad3b2aSLinus Walleij MX50_PAD_EPDC_D10 = 118,
138edad3b2aSLinus Walleij MX50_PAD_EPDC_D11 = 119,
139edad3b2aSLinus Walleij MX50_PAD_EPDC_D12 = 120,
140edad3b2aSLinus Walleij MX50_PAD_EPDC_D13 = 121,
141edad3b2aSLinus Walleij MX50_PAD_EPDC_D14 = 122,
142edad3b2aSLinus Walleij MX50_PAD_EPDC_D15 = 123,
143edad3b2aSLinus Walleij MX50_PAD_EPDC_GDCLK = 124,
144edad3b2aSLinus Walleij MX50_PAD_EPDC_GDSP = 125,
145edad3b2aSLinus Walleij MX50_PAD_EPDC_GDOE = 126,
146edad3b2aSLinus Walleij MX50_PAD_EPDC_GDRL = 127,
147edad3b2aSLinus Walleij MX50_PAD_EPDC_SDCLK = 128,
148edad3b2aSLinus Walleij MX50_PAD_EPDC_SDOEZ = 129,
149edad3b2aSLinus Walleij MX50_PAD_EPDC_SDOED = 130,
150edad3b2aSLinus Walleij MX50_PAD_EPDC_SDOE = 131,
151edad3b2aSLinus Walleij MX50_PAD_EPDC_SDLE = 132,
152edad3b2aSLinus Walleij MX50_PAD_EPDC_SDCLKN = 133,
153edad3b2aSLinus Walleij MX50_PAD_EPDC_SDSHR = 134,
154edad3b2aSLinus Walleij MX50_PAD_EPDC_PWRCOM = 135,
155edad3b2aSLinus Walleij MX50_PAD_EPDC_PWRSTAT = 136,
156edad3b2aSLinus Walleij MX50_PAD_EPDC_PWRCTRL0 = 137,
157edad3b2aSLinus Walleij MX50_PAD_EPDC_PWRCTRL1 = 138,
158edad3b2aSLinus Walleij MX50_PAD_EPDC_PWRCTRL2 = 139,
159edad3b2aSLinus Walleij MX50_PAD_EPDC_PWRCTRL3 = 140,
160edad3b2aSLinus Walleij MX50_PAD_EPDC_VCOM0 = 141,
161edad3b2aSLinus Walleij MX50_PAD_EPDC_VCOM1 = 142,
162edad3b2aSLinus Walleij MX50_PAD_EPDC_BDR0 = 143,
163edad3b2aSLinus Walleij MX50_PAD_EPDC_BDR1 = 144,
164edad3b2aSLinus Walleij MX50_PAD_EPDC_SDCE0 = 145,
165edad3b2aSLinus Walleij MX50_PAD_EPDC_SDCE1 = 146,
166edad3b2aSLinus Walleij MX50_PAD_EPDC_SDCE2 = 147,
167edad3b2aSLinus Walleij MX50_PAD_EPDC_SDCE3 = 148,
168edad3b2aSLinus Walleij MX50_PAD_EPDC_SDCE4 = 149,
169edad3b2aSLinus Walleij MX50_PAD_EPDC_SDCE5 = 150,
170edad3b2aSLinus Walleij MX50_PAD_EIM_DA0 = 151,
171edad3b2aSLinus Walleij MX50_PAD_EIM_DA1 = 152,
172edad3b2aSLinus Walleij MX50_PAD_EIM_DA2 = 153,
173edad3b2aSLinus Walleij MX50_PAD_EIM_DA3 = 154,
174edad3b2aSLinus Walleij MX50_PAD_EIM_DA4 = 155,
175edad3b2aSLinus Walleij MX50_PAD_EIM_DA5 = 156,
176edad3b2aSLinus Walleij MX50_PAD_EIM_DA6 = 157,
177edad3b2aSLinus Walleij MX50_PAD_EIM_DA7 = 158,
178edad3b2aSLinus Walleij MX50_PAD_EIM_DA8 = 159,
179edad3b2aSLinus Walleij MX50_PAD_EIM_DA9 = 160,
180edad3b2aSLinus Walleij MX50_PAD_EIM_DA10 = 161,
181edad3b2aSLinus Walleij MX50_PAD_EIM_DA11 = 162,
182edad3b2aSLinus Walleij MX50_PAD_EIM_DA12 = 163,
183edad3b2aSLinus Walleij MX50_PAD_EIM_DA13 = 164,
184edad3b2aSLinus Walleij MX50_PAD_EIM_DA14 = 165,
185edad3b2aSLinus Walleij MX50_PAD_EIM_DA15 = 166,
186edad3b2aSLinus Walleij MX50_PAD_EIM_CS2 = 167,
187edad3b2aSLinus Walleij MX50_PAD_EIM_CS1 = 168,
188edad3b2aSLinus Walleij MX50_PAD_EIM_CS0 = 169,
189edad3b2aSLinus Walleij MX50_PAD_EIM_EB0 = 170,
190edad3b2aSLinus Walleij MX50_PAD_EIM_EB1 = 171,
191edad3b2aSLinus Walleij MX50_PAD_EIM_WAIT = 172,
192edad3b2aSLinus Walleij MX50_PAD_EIM_BCLK = 173,
193edad3b2aSLinus Walleij MX50_PAD_EIM_RDY = 174,
194edad3b2aSLinus Walleij MX50_PAD_EIM_OE = 175,
195edad3b2aSLinus Walleij MX50_PAD_EIM_RW = 176,
196edad3b2aSLinus Walleij MX50_PAD_EIM_LBA = 177,
197edad3b2aSLinus Walleij MX50_PAD_EIM_CRE = 178,
198edad3b2aSLinus Walleij };
199edad3b2aSLinus Walleij
200edad3b2aSLinus Walleij /* Pad names for the pinmux subsystem */
201edad3b2aSLinus Walleij static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
202edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
203edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
204edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
205edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
206edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
207edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
208edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
209edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
210edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
211edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
212edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
213edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
214edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
215edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
216edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
217edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
218edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL),
219edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA),
220edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL),
221edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA),
222edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL),
223edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA),
224edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_PWM1),
225edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_PWM2),
226edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_0WIRE),
227edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPITO),
228edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_WDOG),
229edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS),
230edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC),
231edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD),
232edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD),
233edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF),
234edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC),
235edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD),
236edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD),
237edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS),
238edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS),
239edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD),
240edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD),
241edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS),
242edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS),
243edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD),
244edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD),
245edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD),
246edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD),
247edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK),
248edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI),
249edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO),
250edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0),
251edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK),
252edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI),
253edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO),
254edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0),
255edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK),
256edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI),
257edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO),
258edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0),
259edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK),
260edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD),
261edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD1_D0),
262edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD1_D1),
263edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD1_D2),
264edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD1_D3),
265edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK),
266edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD),
267edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD2_D0),
268edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD2_D1),
269edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD2_D2),
270edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD2_D3),
271edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD2_D4),
272edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD2_D5),
273edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD2_D6),
274edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD2_D7),
275edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD2_WP),
276edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD2_CD),
277edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D0),
278edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D1),
279edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D2),
280edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D3),
281edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D4),
282edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D5),
283edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D6),
284edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D7),
285edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_WR),
286edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_RD),
287edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_RS),
288edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_CS),
289edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY),
290edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET),
291edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK),
292edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD),
293edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD3_D0),
294edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD3_D1),
295edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD3_D2),
296edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD3_D3),
297edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD3_D4),
298edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD3_D5),
299edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD3_D6),
300edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD3_D7),
301edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_SD3_WP),
302edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D8),
303edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D9),
304edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D10),
305edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D11),
306edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D12),
307edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D13),
308edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D14),
309edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_DISP_D15),
310edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0),
311edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1),
312edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2),
313edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3),
314edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4),
315edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5),
316edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6),
317edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7),
318edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8),
319edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9),
320edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10),
321edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11),
322edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12),
323edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13),
324edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14),
325edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15),
326edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK),
327edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP),
328edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE),
329edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL),
330edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK),
331edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ),
332edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED),
333edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE),
334edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE),
335edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN),
336edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR),
337edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM),
338edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT),
339edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0),
340edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1),
341edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2),
342edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3),
343edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0),
344edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1),
345edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0),
346edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1),
347edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0),
348edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1),
349edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2),
350edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3),
351edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4),
352edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5),
353edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0),
354edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1),
355edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2),
356edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3),
357edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4),
358edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5),
359edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6),
360edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7),
361edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8),
362edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9),
363edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10),
364edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11),
365edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12),
366edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13),
367edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14),
368edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15),
369edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2),
370edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1),
371edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0),
372edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0),
373edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1),
374edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT),
375edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK),
376edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY),
377edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_OE),
378edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_RW),
379edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA),
380edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
381edad3b2aSLinus Walleij };
382edad3b2aSLinus Walleij
3837c017687SStefan Agner static const struct imx_pinctrl_soc_info imx50_pinctrl_info = {
384edad3b2aSLinus Walleij .pins = imx50_pinctrl_pads,
385edad3b2aSLinus Walleij .npins = ARRAY_SIZE(imx50_pinctrl_pads),
3868626ada8SPhilipp Zabel .gpr_compatible = "fsl,imx50-iomuxc-gpr",
387edad3b2aSLinus Walleij };
388edad3b2aSLinus Walleij
389edad3b2aSLinus Walleij static const struct of_device_id imx50_pinctrl_of_match[] = {
390edad3b2aSLinus Walleij { .compatible = "fsl,imx50-iomuxc", },
391edad3b2aSLinus Walleij { /* sentinel */ }
392edad3b2aSLinus Walleij };
393edad3b2aSLinus Walleij
imx50_pinctrl_probe(struct platform_device * pdev)394edad3b2aSLinus Walleij static int imx50_pinctrl_probe(struct platform_device *pdev)
395edad3b2aSLinus Walleij {
396edad3b2aSLinus Walleij return imx_pinctrl_probe(pdev, &imx50_pinctrl_info);
397edad3b2aSLinus Walleij }
398edad3b2aSLinus Walleij
399edad3b2aSLinus Walleij static struct platform_driver imx50_pinctrl_driver = {
400edad3b2aSLinus Walleij .driver = {
401edad3b2aSLinus Walleij .name = "imx50-pinctrl",
402f6b6db2dSFabio Estevam .of_match_table = imx50_pinctrl_of_match,
4038a83ecd8SFabio Estevam .suppress_bind_attrs = true,
404edad3b2aSLinus Walleij },
405edad3b2aSLinus Walleij .probe = imx50_pinctrl_probe,
406edad3b2aSLinus Walleij };
407edad3b2aSLinus Walleij
imx50_pinctrl_init(void)408edad3b2aSLinus Walleij static int __init imx50_pinctrl_init(void)
409edad3b2aSLinus Walleij {
410edad3b2aSLinus Walleij return platform_driver_register(&imx50_pinctrl_driver);
411edad3b2aSLinus Walleij }
412edad3b2aSLinus Walleij arch_initcall(imx50_pinctrl_init);
413