1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Core driver for the imx pin controller in imx1/21/27 4 // 5 // Copyright (C) 2013 Pengutronix 6 // Author: Markus Pargmann <mpa@pengutronix.de> 7 // 8 // Based on pinctrl-imx.c: 9 // Author: Dong Aisheng <dong.aisheng@linaro.org> 10 // Copyright (C) 2012 Freescale Semiconductor, Inc. 11 // Copyright (C) 2012 Linaro Ltd. 12 13 #include <linux/bitops.h> 14 #include <linux/err.h> 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/of.h> 18 #include <linux/of_platform.h> 19 #include <linux/platform_device.h> 20 #include <linux/seq_file.h> 21 #include <linux/slab.h> 22 23 #include <linux/pinctrl/machine.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 28 #include "../core.h" 29 #include "pinctrl-imx1.h" 30 31 struct imx1_pinctrl { 32 struct device *dev; 33 struct pinctrl_dev *pctl; 34 void __iomem *base; 35 const struct imx1_pinctrl_soc_info *info; 36 }; 37 38 /* 39 * MX1 register offsets 40 */ 41 42 #define MX1_DDIR 0x00 43 #define MX1_OCR 0x04 44 #define MX1_ICONFA 0x0c 45 #define MX1_ICONFB 0x14 46 #define MX1_GIUS 0x20 47 #define MX1_GPR 0x38 48 #define MX1_PUEN 0x40 49 50 #define MX1_PORT_STRIDE 0x100 51 52 53 /* 54 * MUX_ID format defines 55 */ 56 #define MX1_MUX_FUNCTION(val) (BIT(0) & val) 57 #define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1) 58 #define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2) 59 #define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4) 60 #define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8) 61 #define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10) 62 63 64 /* 65 * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX 66 * control registers are separated into function, output configuration, input 67 * configuration A, input configuration B, GPIO in use and data direction. 68 * 69 * Those controls that are represented by 1 bit have a direct mapping between 70 * bit position and pin id. If they are represented by 2 bit, the lower 16 pins 71 * are in the first register and the upper 16 pins in the second (next) 72 * register. pin_id is stored in bit (pin_id%16)*2 and the bit above. 73 */ 74 75 /* 76 * Calculates the register offset from a pin_id 77 */ 78 static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id) 79 { 80 unsigned int port = pin_id / 32; 81 return ipctl->base + port * MX1_PORT_STRIDE; 82 } 83 84 /* 85 * Write to a register with 2 bits per pin. The function will automatically 86 * use the next register if the pin is managed in the second register. 87 */ 88 static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, 89 u32 value, u32 reg_offset) 90 { 91 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; 92 int offset = (pin_id % 16) * 2; /* offset, regardless of register used */ 93 int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */ 94 u32 old_val; 95 u32 new_val; 96 97 /* Use the next register if the pin's port pin number is >=16 */ 98 if (pin_id % 32 >= 16) 99 reg += 0x04; 100 101 dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n", 102 reg, offset, value); 103 104 /* Get current state of pins */ 105 old_val = readl(reg); 106 old_val &= mask; 107 108 new_val = value & 0x3; /* Make sure value is really 2 bit */ 109 new_val <<= offset; 110 new_val |= old_val;/* Set new state for pin_id */ 111 112 writel(new_val, reg); 113 } 114 115 static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, 116 u32 value, u32 reg_offset) 117 { 118 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; 119 int offset = pin_id % 32; 120 int mask = ~BIT_MASK(offset); 121 u32 old_val; 122 u32 new_val; 123 124 /* Get current state of pins */ 125 old_val = readl(reg); 126 old_val &= mask; 127 128 new_val = value & 0x1; /* Make sure value is really 1 bit */ 129 new_val <<= offset; 130 new_val |= old_val;/* Set new state for pin_id */ 131 132 writel(new_val, reg); 133 } 134 135 static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, 136 u32 reg_offset) 137 { 138 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; 139 int offset = (pin_id % 16) * 2; 140 141 /* Use the next register if the pin's port pin number is >=16 */ 142 if (pin_id % 32 >= 16) 143 reg += 0x04; 144 145 return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset; 146 } 147 148 static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, 149 u32 reg_offset) 150 { 151 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; 152 int offset = pin_id % 32; 153 154 return !!(readl(reg) & BIT(offset)); 155 } 156 157 static inline const struct imx1_pin_group *imx1_pinctrl_find_group_by_name( 158 const struct imx1_pinctrl_soc_info *info, 159 const char *name) 160 { 161 const struct imx1_pin_group *grp = NULL; 162 int i; 163 164 for (i = 0; i < info->ngroups; i++) { 165 if (!strcmp(info->groups[i].name, name)) { 166 grp = &info->groups[i]; 167 break; 168 } 169 } 170 171 return grp; 172 } 173 174 static int imx1_get_groups_count(struct pinctrl_dev *pctldev) 175 { 176 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 177 const struct imx1_pinctrl_soc_info *info = ipctl->info; 178 179 return info->ngroups; 180 } 181 182 static const char *imx1_get_group_name(struct pinctrl_dev *pctldev, 183 unsigned selector) 184 { 185 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 186 const struct imx1_pinctrl_soc_info *info = ipctl->info; 187 188 return info->groups[selector].name; 189 } 190 191 static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 192 const unsigned int **pins, 193 unsigned *npins) 194 { 195 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 196 const struct imx1_pinctrl_soc_info *info = ipctl->info; 197 198 if (selector >= info->ngroups) 199 return -EINVAL; 200 201 *pins = info->groups[selector].pin_ids; 202 *npins = info->groups[selector].npins; 203 204 return 0; 205 } 206 207 static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 208 unsigned offset) 209 { 210 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 211 212 seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d", 213 imx1_read_bit(ipctl, offset, MX1_GIUS), 214 imx1_read_bit(ipctl, offset, MX1_GPR), 215 imx1_read_bit(ipctl, offset, MX1_DDIR), 216 imx1_read_2bit(ipctl, offset, MX1_OCR), 217 imx1_read_2bit(ipctl, offset, MX1_ICONFA), 218 imx1_read_2bit(ipctl, offset, MX1_ICONFB)); 219 } 220 221 static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev, 222 struct device_node *np, 223 struct pinctrl_map **map, unsigned *num_maps) 224 { 225 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 226 const struct imx1_pinctrl_soc_info *info = ipctl->info; 227 const struct imx1_pin_group *grp; 228 struct pinctrl_map *new_map; 229 struct device_node *parent; 230 int map_num = 1; 231 int i, j; 232 233 /* 234 * first find the group of this node and check if we need create 235 * config maps for pins 236 */ 237 grp = imx1_pinctrl_find_group_by_name(info, np->name); 238 if (!grp) { 239 dev_err(info->dev, "unable to find group for node %pOFn\n", 240 np); 241 return -EINVAL; 242 } 243 244 for (i = 0; i < grp->npins; i++) 245 map_num++; 246 247 new_map = kmalloc_objs(struct pinctrl_map, map_num); 248 if (!new_map) 249 return -ENOMEM; 250 251 *map = new_map; 252 *num_maps = map_num; 253 254 /* create mux map */ 255 parent = of_get_parent(np); 256 if (!parent) { 257 kfree(new_map); 258 return -EINVAL; 259 } 260 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 261 new_map[0].data.mux.function = parent->name; 262 new_map[0].data.mux.group = np->name; 263 of_node_put(parent); 264 265 /* create config map */ 266 new_map++; 267 for (i = j = 0; i < grp->npins; i++) { 268 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; 269 new_map[j].data.configs.group_or_pin = 270 pin_get_name(pctldev, grp->pins[i].pin_id); 271 new_map[j].data.configs.configs = &grp->pins[i].config; 272 new_map[j].data.configs.num_configs = 1; 273 j++; 274 } 275 276 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 277 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 278 279 return 0; 280 } 281 282 static void imx1_dt_free_map(struct pinctrl_dev *pctldev, 283 struct pinctrl_map *map, unsigned num_maps) 284 { 285 kfree(map); 286 } 287 288 static const struct pinctrl_ops imx1_pctrl_ops = { 289 .get_groups_count = imx1_get_groups_count, 290 .get_group_name = imx1_get_group_name, 291 .get_group_pins = imx1_get_group_pins, 292 .pin_dbg_show = imx1_pin_dbg_show, 293 .dt_node_to_map = imx1_dt_node_to_map, 294 .dt_free_map = imx1_dt_free_map, 295 }; 296 297 static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 298 unsigned group) 299 { 300 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 301 const struct imx1_pinctrl_soc_info *info = ipctl->info; 302 const struct imx1_pin *pins; 303 unsigned int npins; 304 int i; 305 306 /* 307 * Configure the mux mode for each pin in the group for a specific 308 * function. 309 */ 310 pins = info->groups[group].pins; 311 npins = info->groups[group].npins; 312 313 WARN_ON(!pins || !npins); 314 315 dev_dbg(ipctl->dev, "enable function %s group %s\n", 316 info->functions[selector].name, info->groups[group].name); 317 318 for (i = 0; i < npins; i++) { 319 unsigned int mux = pins[i].mux_id; 320 unsigned int pin_id = pins[i].pin_id; 321 unsigned int afunction = MX1_MUX_FUNCTION(mux); 322 unsigned int gpio_in_use = MX1_MUX_GPIO(mux); 323 unsigned int direction = MX1_MUX_DIR(mux); 324 unsigned int gpio_oconf = MX1_MUX_OCONF(mux); 325 unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux); 326 unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux); 327 328 dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n", 329 __func__, pin_id, afunction, gpio_in_use, 330 direction, gpio_oconf, gpio_iconfa, 331 gpio_iconfb); 332 333 imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS); 334 imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR); 335 336 if (gpio_in_use) { 337 imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR); 338 imx1_write_2bit(ipctl, pin_id, gpio_iconfa, 339 MX1_ICONFA); 340 imx1_write_2bit(ipctl, pin_id, gpio_iconfb, 341 MX1_ICONFB); 342 } else { 343 imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR); 344 } 345 } 346 347 return 0; 348 } 349 350 static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 351 { 352 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 353 const struct imx1_pinctrl_soc_info *info = ipctl->info; 354 355 return info->nfunctions; 356 } 357 358 static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev, 359 unsigned selector) 360 { 361 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 362 const struct imx1_pinctrl_soc_info *info = ipctl->info; 363 364 return info->functions[selector].name; 365 } 366 367 static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 368 const char * const **groups, 369 unsigned * const num_groups) 370 { 371 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 372 const struct imx1_pinctrl_soc_info *info = ipctl->info; 373 374 *groups = info->functions[selector].groups; 375 *num_groups = info->functions[selector].num_groups; 376 377 return 0; 378 } 379 380 static const struct pinmux_ops imx1_pmx_ops = { 381 .get_functions_count = imx1_pmx_get_funcs_count, 382 .get_function_name = imx1_pmx_get_func_name, 383 .get_function_groups = imx1_pmx_get_groups, 384 .set_mux = imx1_pmx_set, 385 }; 386 387 static int imx1_pinconf_get(struct pinctrl_dev *pctldev, 388 unsigned pin_id, unsigned long *config) 389 { 390 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 391 392 *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN); 393 394 return 0; 395 } 396 397 static int imx1_pinconf_set(struct pinctrl_dev *pctldev, 398 unsigned pin_id, unsigned long *configs, 399 unsigned num_configs) 400 { 401 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 402 int i; 403 404 for (i = 0; i != num_configs; ++i) { 405 imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN); 406 407 dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n", 408 pin_desc_get(pctldev, pin_id)->name); 409 } 410 411 return 0; 412 } 413 414 static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev, 415 struct seq_file *s, unsigned pin_id) 416 { 417 unsigned long config; 418 419 imx1_pinconf_get(pctldev, pin_id, &config); 420 seq_printf(s, "0x%lx", config); 421 } 422 423 static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 424 struct seq_file *s, unsigned group) 425 { 426 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 427 const struct imx1_pinctrl_soc_info *info = ipctl->info; 428 struct imx1_pin_group *grp; 429 unsigned long config; 430 const char *name; 431 int i, ret; 432 433 if (group >= info->ngroups) 434 return; 435 436 seq_puts(s, "\n"); 437 grp = &info->groups[group]; 438 for (i = 0; i < grp->npins; i++) { 439 name = pin_get_name(pctldev, grp->pins[i].pin_id); 440 ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config); 441 if (ret) 442 return; 443 seq_printf(s, "%s: 0x%lx", name, config); 444 } 445 } 446 447 static const struct pinconf_ops imx1_pinconf_ops = { 448 .pin_config_get = imx1_pinconf_get, 449 .pin_config_set = imx1_pinconf_set, 450 .pin_config_dbg_show = imx1_pinconf_dbg_show, 451 .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show, 452 }; 453 454 static struct pinctrl_desc imx1_pinctrl_desc = { 455 .pctlops = &imx1_pctrl_ops, 456 .pmxops = &imx1_pmx_ops, 457 .confops = &imx1_pinconf_ops, 458 .owner = THIS_MODULE, 459 }; 460 461 static int imx1_pinctrl_parse_groups(struct device_node *np, 462 struct imx1_pin_group *grp, 463 struct imx1_pinctrl_soc_info *info, 464 u32 index) 465 { 466 int size; 467 const __be32 *list; 468 int i; 469 470 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); 471 472 /* Initialise group */ 473 grp->name = np->name; 474 475 /* 476 * the binding format is fsl,pins = <PIN MUX_ID CONFIG> 477 */ 478 list = of_get_property(np, "fsl,pins", &size); 479 /* we do not check return since it's safe node passed down */ 480 if (!size || size % 12) { 481 dev_notice(info->dev, "Not a valid fsl,pins property (%pOFn)\n", 482 np); 483 return -EINVAL; 484 } 485 486 grp->npins = size / 12; 487 grp->pins = devm_kcalloc(info->dev, 488 grp->npins, sizeof(struct imx1_pin), GFP_KERNEL); 489 grp->pin_ids = devm_kcalloc(info->dev, 490 grp->npins, sizeof(unsigned int), GFP_KERNEL); 491 492 if (!grp->pins || !grp->pin_ids) 493 return -ENOMEM; 494 495 for (i = 0; i < grp->npins; i++) { 496 grp->pins[i].pin_id = be32_to_cpu(*list++); 497 grp->pins[i].mux_id = be32_to_cpu(*list++); 498 grp->pins[i].config = be32_to_cpu(*list++); 499 500 grp->pin_ids[i] = grp->pins[i].pin_id; 501 } 502 503 return 0; 504 } 505 506 static int imx1_pinctrl_parse_functions(struct device_node *np, 507 struct imx1_pinctrl_soc_info *info, 508 u32 index) 509 { 510 struct imx1_pmx_func *func; 511 struct imx1_pin_group *grp; 512 int ret; 513 static u32 grp_index; 514 u32 i = 0; 515 516 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); 517 518 func = &info->functions[index]; 519 520 /* Initialise function */ 521 func->name = np->name; 522 func->num_groups = of_get_child_count(np); 523 if (func->num_groups == 0) 524 return -EINVAL; 525 526 func->groups = devm_kcalloc(info->dev, 527 func->num_groups, sizeof(char *), GFP_KERNEL); 528 529 if (!func->groups) 530 return -ENOMEM; 531 532 for_each_child_of_node_scoped(np, child) { 533 func->groups[i] = child->name; 534 grp = &info->groups[grp_index++]; 535 ret = imx1_pinctrl_parse_groups(child, grp, info, i++); 536 if (ret == -ENOMEM) 537 return ret; 538 } 539 540 return 0; 541 } 542 543 static int imx1_pinctrl_parse_dt(struct platform_device *pdev, 544 struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info) 545 { 546 struct device_node *np = pdev->dev.of_node; 547 int ret; 548 u32 nfuncs = 0; 549 u32 ngroups = 0; 550 u32 ifunc = 0; 551 552 if (!np) 553 return -ENODEV; 554 555 for_each_child_of_node_scoped(np, child) { 556 ++nfuncs; 557 ngroups += of_get_child_count(child); 558 } 559 560 if (!nfuncs) { 561 dev_err(&pdev->dev, "No pin functions defined\n"); 562 return -EINVAL; 563 } 564 565 info->nfunctions = nfuncs; 566 info->functions = devm_kcalloc(&pdev->dev, 567 nfuncs, sizeof(struct imx1_pmx_func), GFP_KERNEL); 568 569 info->ngroups = ngroups; 570 info->groups = devm_kcalloc(&pdev->dev, 571 ngroups, sizeof(struct imx1_pin_group), GFP_KERNEL); 572 573 574 if (!info->functions || !info->groups) 575 return -ENOMEM; 576 577 for_each_child_of_node_scoped(np, child) { 578 ret = imx1_pinctrl_parse_functions(child, info, ifunc++); 579 if (ret == -ENOMEM) 580 return -ENOMEM; 581 } 582 583 return 0; 584 } 585 586 int imx1_pinctrl_core_probe(struct platform_device *pdev, 587 struct imx1_pinctrl_soc_info *info) 588 { 589 struct imx1_pinctrl *ipctl; 590 struct resource *res; 591 struct pinctrl_desc *pctl_desc; 592 int ret; 593 594 if (!info || !info->pins || !info->npins) { 595 dev_err(&pdev->dev, "wrong pinctrl info\n"); 596 return -EINVAL; 597 } 598 info->dev = &pdev->dev; 599 600 /* Create state holders etc for this driver */ 601 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 602 if (!ipctl) 603 return -ENOMEM; 604 605 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 606 if (!res) 607 return -ENOENT; 608 609 ipctl->base = devm_ioremap(&pdev->dev, res->start, 610 resource_size(res)); 611 if (!ipctl->base) 612 return -ENOMEM; 613 614 pctl_desc = &imx1_pinctrl_desc; 615 pctl_desc->name = dev_name(&pdev->dev); 616 pctl_desc->pins = info->pins; 617 pctl_desc->npins = info->npins; 618 619 ret = imx1_pinctrl_parse_dt(pdev, ipctl, info); 620 if (ret) { 621 dev_err(&pdev->dev, "fail to probe dt properties\n"); 622 return ret; 623 } 624 625 ipctl->info = info; 626 ipctl->dev = info->dev; 627 platform_set_drvdata(pdev, ipctl); 628 ipctl->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, ipctl); 629 if (IS_ERR(ipctl->pctl)) { 630 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); 631 return PTR_ERR(ipctl->pctl); 632 } 633 634 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 635 if (ret) { 636 dev_err(&pdev->dev, "Failed to populate subdevices\n"); 637 return ret; 638 } 639 640 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); 641 642 return 0; 643 } 644