xref: /linux/drivers/pinctrl/freescale/pinctrl-imx.c (revision e5c86679d5e864947a52fb31e45a425dea3e7fa9)
1 /*
2  * Core driver for the imx pin controller
3  *
4  * Copyright (C) 2012 Freescale Semiconductor, Inc.
5  * Copyright (C) 2012 Linaro Ltd.
6  *
7  * Author: Dong Aisheng <dong.aisheng@linaro.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  */
14 
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/io.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/of_address.h>
22 #include <linux/pinctrl/machine.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/slab.h>
27 #include <linux/regmap.h>
28 
29 #include "../core.h"
30 #include "../pinmux.h"
31 #include "pinctrl-imx.h"
32 
33 /* The bits in CONFIG cell defined in binding doc*/
34 #define IMX_NO_PAD_CTL	0x80000000	/* no pin config need */
35 #define IMX_PAD_SION 0x40000000		/* set SION */
36 
37 /**
38  * @dev: a pointer back to containing device
39  * @base: the offset to the controller in virtual memory
40  */
41 struct imx_pinctrl {
42 	struct device *dev;
43 	struct pinctrl_dev *pctl;
44 	void __iomem *base;
45 	void __iomem *input_sel_base;
46 	struct imx_pinctrl_soc_info *info;
47 };
48 
49 static inline const struct group_desc *imx_pinctrl_find_group_by_name(
50 				struct pinctrl_dev *pctldev,
51 				const char *name)
52 {
53 	const struct group_desc *grp = NULL;
54 	int i;
55 
56 	for (i = 0; i < pctldev->num_groups; i++) {
57 		grp = pinctrl_generic_get_group(pctldev, i);
58 		if (grp && !strcmp(grp->name, name))
59 			break;
60 	}
61 
62 	return grp;
63 }
64 
65 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
66 		   unsigned offset)
67 {
68 	seq_printf(s, "%s", dev_name(pctldev->dev));
69 }
70 
71 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
72 			struct device_node *np,
73 			struct pinctrl_map **map, unsigned *num_maps)
74 {
75 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
76 	struct imx_pinctrl_soc_info *info = ipctl->info;
77 	const struct group_desc *grp;
78 	struct pinctrl_map *new_map;
79 	struct device_node *parent;
80 	int map_num = 1;
81 	int i, j;
82 
83 	/*
84 	 * first find the group of this node and check if we need create
85 	 * config maps for pins
86 	 */
87 	grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
88 	if (!grp) {
89 		dev_err(info->dev, "unable to find group for node %s\n",
90 			np->name);
91 		return -EINVAL;
92 	}
93 
94 	for (i = 0; i < grp->num_pins; i++) {
95 		struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
96 
97 		if (!(pin->config & IMX_NO_PAD_CTL))
98 			map_num++;
99 	}
100 
101 	new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
102 	if (!new_map)
103 		return -ENOMEM;
104 
105 	*map = new_map;
106 	*num_maps = map_num;
107 
108 	/* create mux map */
109 	parent = of_get_parent(np);
110 	if (!parent) {
111 		kfree(new_map);
112 		return -EINVAL;
113 	}
114 	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
115 	new_map[0].data.mux.function = parent->name;
116 	new_map[0].data.mux.group = np->name;
117 	of_node_put(parent);
118 
119 	/* create config map */
120 	new_map++;
121 	for (i = j = 0; i < grp->num_pins; i++) {
122 		struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
123 
124 		if (!(pin->config & IMX_NO_PAD_CTL)) {
125 			new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
126 			new_map[j].data.configs.group_or_pin =
127 					pin_get_name(pctldev, pin->pin);
128 			new_map[j].data.configs.configs = &pin->config;
129 			new_map[j].data.configs.num_configs = 1;
130 			j++;
131 		}
132 	}
133 
134 	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
135 		(*map)->data.mux.function, (*map)->data.mux.group, map_num);
136 
137 	return 0;
138 }
139 
140 static void imx_dt_free_map(struct pinctrl_dev *pctldev,
141 				struct pinctrl_map *map, unsigned num_maps)
142 {
143 	kfree(map);
144 }
145 
146 static const struct pinctrl_ops imx_pctrl_ops = {
147 	.get_groups_count = pinctrl_generic_get_group_count,
148 	.get_group_name = pinctrl_generic_get_group_name,
149 	.get_group_pins = pinctrl_generic_get_group_pins,
150 	.pin_dbg_show = imx_pin_dbg_show,
151 	.dt_node_to_map = imx_dt_node_to_map,
152 	.dt_free_map = imx_dt_free_map,
153 
154 };
155 
156 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
157 		       unsigned group)
158 {
159 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
160 	struct imx_pinctrl_soc_info *info = ipctl->info;
161 	const struct imx_pin_reg *pin_reg;
162 	unsigned int npins, pin_id;
163 	int i;
164 	struct group_desc *grp = NULL;
165 	struct function_desc *func = NULL;
166 
167 	/*
168 	 * Configure the mux mode for each pin in the group for a specific
169 	 * function.
170 	 */
171 	grp = pinctrl_generic_get_group(pctldev, group);
172 	if (!grp)
173 		return -EINVAL;
174 
175 	func = pinmux_generic_get_function(pctldev, selector);
176 	if (!func)
177 		return -EINVAL;
178 
179 	npins = grp->num_pins;
180 
181 	dev_dbg(ipctl->dev, "enable function %s group %s\n",
182 		func->name, grp->name);
183 
184 	for (i = 0; i < npins; i++) {
185 		struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
186 
187 		pin_id = pin->pin;
188 		pin_reg = &info->pin_regs[pin_id];
189 
190 		if (pin_reg->mux_reg == -1) {
191 			dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
192 				info->pins[pin_id].name);
193 			continue;
194 		}
195 
196 		if (info->flags & SHARE_MUX_CONF_REG) {
197 			u32 reg;
198 			reg = readl(ipctl->base + pin_reg->mux_reg);
199 			reg &= ~(0x7 << 20);
200 			reg |= (pin->mux_mode << 20);
201 			writel(reg, ipctl->base + pin_reg->mux_reg);
202 		} else {
203 			writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
204 		}
205 		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
206 			pin_reg->mux_reg, pin->mux_mode);
207 
208 		/*
209 		 * If the select input value begins with 0xff, it's a quirky
210 		 * select input and the value should be interpreted as below.
211 		 *     31     23      15      7        0
212 		 *     | 0xff | shift | width | select |
213 		 * It's used to work around the problem that the select
214 		 * input for some pin is not implemented in the select
215 		 * input register but in some general purpose register.
216 		 * We encode the select input value, width and shift of
217 		 * the bit field into input_val cell of pin function ID
218 		 * in device tree, and then decode them here for setting
219 		 * up the select input bits in general purpose register.
220 		 */
221 		if (pin->input_val >> 24 == 0xff) {
222 			u32 val = pin->input_val;
223 			u8 select = val & 0xff;
224 			u8 width = (val >> 8) & 0xff;
225 			u8 shift = (val >> 16) & 0xff;
226 			u32 mask = ((1 << width) - 1) << shift;
227 			/*
228 			 * The input_reg[i] here is actually some IOMUXC general
229 			 * purpose register, not regular select input register.
230 			 */
231 			val = readl(ipctl->base + pin->input_reg);
232 			val &= ~mask;
233 			val |= select << shift;
234 			writel(val, ipctl->base + pin->input_reg);
235 		} else if (pin->input_reg) {
236 			/*
237 			 * Regular select input register can never be at offset
238 			 * 0, and we only print register value for regular case.
239 			 */
240 			if (ipctl->input_sel_base)
241 				writel(pin->input_val, ipctl->input_sel_base +
242 						pin->input_reg);
243 			else
244 				writel(pin->input_val, ipctl->base +
245 						pin->input_reg);
246 			dev_dbg(ipctl->dev,
247 				"==>select_input: offset 0x%x val 0x%x\n",
248 				pin->input_reg, pin->input_val);
249 		}
250 	}
251 
252 	return 0;
253 }
254 
255 static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
256 			struct pinctrl_gpio_range *range, unsigned offset)
257 {
258 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
259 	struct imx_pinctrl_soc_info *info = ipctl->info;
260 	const struct imx_pin_reg *pin_reg;
261 	struct group_desc *grp;
262 	struct imx_pin *imx_pin;
263 	unsigned int pin, group;
264 	u32 reg;
265 
266 	/* Currently implementation only for shared mux/conf register */
267 	if (!(info->flags & SHARE_MUX_CONF_REG))
268 		return 0;
269 
270 	pin_reg = &info->pin_regs[offset];
271 	if (pin_reg->mux_reg == -1)
272 		return -EINVAL;
273 
274 	/* Find the pinctrl config with GPIO mux mode for the requested pin */
275 	for (group = 0; group < pctldev->num_groups; group++) {
276 		grp = pinctrl_generic_get_group(pctldev, group);
277 		if (!grp)
278 			continue;
279 		for (pin = 0; pin < grp->num_pins; pin++) {
280 			imx_pin = &((struct imx_pin *)(grp->data))[pin];
281 			if (imx_pin->pin == offset && !imx_pin->mux_mode)
282 				goto mux_pin;
283 		}
284 	}
285 
286 	return -EINVAL;
287 
288 mux_pin:
289 	reg = readl(ipctl->base + pin_reg->mux_reg);
290 	reg &= ~(0x7 << 20);
291 	reg |= imx_pin->config;
292 	writel(reg, ipctl->base + pin_reg->mux_reg);
293 
294 	return 0;
295 }
296 
297 static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
298 			struct pinctrl_gpio_range *range, unsigned offset)
299 {
300 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
301 	struct imx_pinctrl_soc_info *info = ipctl->info;
302 	const struct imx_pin_reg *pin_reg;
303 	u32 reg;
304 
305 	/*
306 	 * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
307 	 * They are part of the shared mux/conf register.
308 	 */
309 	if (!(info->flags & SHARE_MUX_CONF_REG))
310 		return;
311 
312 	pin_reg = &info->pin_regs[offset];
313 	if (pin_reg->mux_reg == -1)
314 		return;
315 
316 	/* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */
317 	reg = readl(ipctl->base + pin_reg->mux_reg);
318 	reg &= ~0x7;
319 	writel(reg, ipctl->base + pin_reg->mux_reg);
320 }
321 
322 static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
323 	   struct pinctrl_gpio_range *range, unsigned offset, bool input)
324 {
325 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
326 	struct imx_pinctrl_soc_info *info = ipctl->info;
327 	const struct imx_pin_reg *pin_reg;
328 	u32 reg;
329 
330 	/*
331 	 * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
332 	 * They are part of the shared mux/conf register.
333 	 */
334 	if (!(info->flags & SHARE_MUX_CONF_REG))
335 		return 0;
336 
337 	pin_reg = &info->pin_regs[offset];
338 	if (pin_reg->mux_reg == -1)
339 		return -EINVAL;
340 
341 	/* IBE always enabled allows us to read the value "on the wire" */
342 	reg = readl(ipctl->base + pin_reg->mux_reg);
343 	if (input)
344 		reg &= ~0x2;
345 	else
346 		reg |= 0x2;
347 	writel(reg, ipctl->base + pin_reg->mux_reg);
348 
349 	return 0;
350 }
351 
352 static const struct pinmux_ops imx_pmx_ops = {
353 	.get_functions_count = pinmux_generic_get_function_count,
354 	.get_function_name = pinmux_generic_get_function_name,
355 	.get_function_groups = pinmux_generic_get_function_groups,
356 	.set_mux = imx_pmx_set,
357 	.gpio_request_enable = imx_pmx_gpio_request_enable,
358 	.gpio_disable_free = imx_pmx_gpio_disable_free,
359 	.gpio_set_direction = imx_pmx_gpio_set_direction,
360 };
361 
362 static int imx_pinconf_get(struct pinctrl_dev *pctldev,
363 			     unsigned pin_id, unsigned long *config)
364 {
365 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
366 	struct imx_pinctrl_soc_info *info = ipctl->info;
367 	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
368 
369 	if (pin_reg->conf_reg == -1) {
370 		dev_err(info->dev, "Pin(%s) does not support config function\n",
371 			info->pins[pin_id].name);
372 		return -EINVAL;
373 	}
374 
375 	*config = readl(ipctl->base + pin_reg->conf_reg);
376 
377 	if (info->flags & SHARE_MUX_CONF_REG)
378 		*config &= 0xffff;
379 
380 	return 0;
381 }
382 
383 static int imx_pinconf_set(struct pinctrl_dev *pctldev,
384 			     unsigned pin_id, unsigned long *configs,
385 			     unsigned num_configs)
386 {
387 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
388 	struct imx_pinctrl_soc_info *info = ipctl->info;
389 	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
390 	int i;
391 
392 	if (pin_reg->conf_reg == -1) {
393 		dev_err(info->dev, "Pin(%s) does not support config function\n",
394 			info->pins[pin_id].name);
395 		return -EINVAL;
396 	}
397 
398 	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
399 		info->pins[pin_id].name);
400 
401 	for (i = 0; i < num_configs; i++) {
402 		if (info->flags & SHARE_MUX_CONF_REG) {
403 			u32 reg;
404 			reg = readl(ipctl->base + pin_reg->conf_reg);
405 			reg &= ~0xffff;
406 			reg |= configs[i];
407 			writel(reg, ipctl->base + pin_reg->conf_reg);
408 		} else {
409 			writel(configs[i], ipctl->base + pin_reg->conf_reg);
410 		}
411 		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
412 			pin_reg->conf_reg, configs[i]);
413 	} /* for each config */
414 
415 	return 0;
416 }
417 
418 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
419 				   struct seq_file *s, unsigned pin_id)
420 {
421 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
422 	struct imx_pinctrl_soc_info *info = ipctl->info;
423 	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
424 	unsigned long config;
425 
426 	if (!pin_reg || pin_reg->conf_reg == -1) {
427 		seq_printf(s, "N/A");
428 		return;
429 	}
430 
431 	config = readl(ipctl->base + pin_reg->conf_reg);
432 	seq_printf(s, "0x%lx", config);
433 }
434 
435 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
436 					 struct seq_file *s, unsigned group)
437 {
438 	struct group_desc *grp;
439 	unsigned long config;
440 	const char *name;
441 	int i, ret;
442 
443 	if (group > pctldev->num_groups)
444 		return;
445 
446 	seq_printf(s, "\n");
447 	grp = pinctrl_generic_get_group(pctldev, group);
448 	if (!grp)
449 		return;
450 
451 	for (i = 0; i < grp->num_pins; i++) {
452 		struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
453 
454 		name = pin_get_name(pctldev, pin->pin);
455 		ret = imx_pinconf_get(pctldev, pin->pin, &config);
456 		if (ret)
457 			return;
458 		seq_printf(s, "  %s: 0x%lx\n", name, config);
459 	}
460 }
461 
462 static const struct pinconf_ops imx_pinconf_ops = {
463 	.pin_config_get = imx_pinconf_get,
464 	.pin_config_set = imx_pinconf_set,
465 	.pin_config_dbg_show = imx_pinconf_dbg_show,
466 	.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
467 };
468 
469 /*
470  * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
471  * 1 u32 CONFIG, so 24 types in total for each pin.
472  */
473 #define FSL_PIN_SIZE 24
474 #define SHARE_FSL_PIN_SIZE 20
475 
476 static int imx_pinctrl_parse_groups(struct device_node *np,
477 				    struct group_desc *grp,
478 				    struct imx_pinctrl_soc_info *info,
479 				    u32 index)
480 {
481 	int size, pin_size;
482 	const __be32 *list;
483 	int i;
484 	u32 config;
485 
486 	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
487 
488 	if (info->flags & SHARE_MUX_CONF_REG)
489 		pin_size = SHARE_FSL_PIN_SIZE;
490 	else
491 		pin_size = FSL_PIN_SIZE;
492 	/* Initialise group */
493 	grp->name = np->name;
494 
495 	/*
496 	 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
497 	 * do sanity check and calculate pins number
498 	 */
499 	list = of_get_property(np, "fsl,pins", &size);
500 	if (!list) {
501 		dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
502 		return -EINVAL;
503 	}
504 
505 	/* we do not check return since it's safe node passed down */
506 	if (!size || size % pin_size) {
507 		dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
508 		return -EINVAL;
509 	}
510 
511 	grp->num_pins = size / pin_size;
512 	grp->data = devm_kzalloc(info->dev, grp->num_pins *
513 				 sizeof(struct imx_pin), GFP_KERNEL);
514 	grp->pins = devm_kzalloc(info->dev, grp->num_pins *
515 				 sizeof(unsigned int), GFP_KERNEL);
516 	if (!grp->pins || !grp->data)
517 		return -ENOMEM;
518 
519 	for (i = 0; i < grp->num_pins; i++) {
520 		u32 mux_reg = be32_to_cpu(*list++);
521 		u32 conf_reg;
522 		unsigned int pin_id;
523 		struct imx_pin_reg *pin_reg;
524 		struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
525 
526 		if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
527 			mux_reg = -1;
528 
529 		if (info->flags & SHARE_MUX_CONF_REG) {
530 			conf_reg = mux_reg;
531 		} else {
532 			conf_reg = be32_to_cpu(*list++);
533 			if (!conf_reg)
534 				conf_reg = -1;
535 		}
536 
537 		pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
538 		pin_reg = &info->pin_regs[pin_id];
539 		pin->pin = pin_id;
540 		grp->pins[i] = pin_id;
541 		pin_reg->mux_reg = mux_reg;
542 		pin_reg->conf_reg = conf_reg;
543 		pin->input_reg = be32_to_cpu(*list++);
544 		pin->mux_mode = be32_to_cpu(*list++);
545 		pin->input_val = be32_to_cpu(*list++);
546 
547 		/* SION bit is in mux register */
548 		config = be32_to_cpu(*list++);
549 		if (config & IMX_PAD_SION)
550 			pin->mux_mode |= IOMUXC_CONFIG_SION;
551 		pin->config = config & ~IMX_PAD_SION;
552 
553 		dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
554 				pin->mux_mode, pin->config);
555 	}
556 
557 	return 0;
558 }
559 
560 static int imx_pinctrl_parse_functions(struct device_node *np,
561 				       struct imx_pinctrl *ipctl,
562 				       u32 index)
563 {
564 	struct pinctrl_dev *pctl = ipctl->pctl;
565 	struct imx_pinctrl_soc_info *info = ipctl->info;
566 	struct device_node *child;
567 	struct function_desc *func;
568 	struct group_desc *grp;
569 	u32 i = 0;
570 
571 	dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
572 
573 	func = pinmux_generic_get_function(pctl, index);
574 	if (!func)
575 		return -EINVAL;
576 
577 	/* Initialise function */
578 	func->name = np->name;
579 	func->num_group_names = of_get_child_count(np);
580 	if (func->num_group_names == 0) {
581 		dev_err(info->dev, "no groups defined in %s\n", np->full_name);
582 		return -EINVAL;
583 	}
584 	func->group_names = devm_kzalloc(info->dev,
585 					 func->num_group_names *
586 					 sizeof(char *), GFP_KERNEL);
587 
588 	for_each_child_of_node(np, child) {
589 		func->group_names[i] = child->name;
590 
591 		grp = devm_kzalloc(info->dev, sizeof(struct group_desc),
592 				   GFP_KERNEL);
593 		if (!grp)
594 			return -ENOMEM;
595 
596 		mutex_lock(&info->mutex);
597 		radix_tree_insert(&pctl->pin_group_tree,
598 				  info->group_index++, grp);
599 		mutex_unlock(&info->mutex);
600 
601 		imx_pinctrl_parse_groups(child, grp, info, i++);
602 	}
603 
604 	return 0;
605 }
606 
607 /*
608  * Check if the DT contains pins in the direct child nodes. This indicates the
609  * newer DT format to store pins. This function returns true if the first found
610  * fsl,pins property is in a child of np. Otherwise false is returned.
611  */
612 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
613 {
614 	struct device_node *function_np;
615 	struct device_node *pinctrl_np;
616 
617 	for_each_child_of_node(np, function_np) {
618 		if (of_property_read_bool(function_np, "fsl,pins"))
619 			return true;
620 
621 		for_each_child_of_node(function_np, pinctrl_np) {
622 			if (of_property_read_bool(pinctrl_np, "fsl,pins"))
623 				return false;
624 		}
625 	}
626 
627 	return true;
628 }
629 
630 static int imx_pinctrl_probe_dt(struct platform_device *pdev,
631 				struct imx_pinctrl *ipctl)
632 {
633 	struct device_node *np = pdev->dev.of_node;
634 	struct device_node *child;
635 	struct pinctrl_dev *pctl = ipctl->pctl;
636 	struct imx_pinctrl_soc_info *info = ipctl->info;
637 	u32 nfuncs = 0;
638 	u32 i = 0;
639 	bool flat_funcs;
640 
641 	if (!np)
642 		return -ENODEV;
643 
644 	flat_funcs = imx_pinctrl_dt_is_flat_functions(np);
645 	if (flat_funcs) {
646 		nfuncs = 1;
647 	} else {
648 		nfuncs = of_get_child_count(np);
649 		if (nfuncs <= 0) {
650 			dev_err(&pdev->dev, "no functions defined\n");
651 			return -EINVAL;
652 		}
653 	}
654 
655 	for (i = 0; i < nfuncs; i++) {
656 		struct function_desc *function;
657 
658 		function = devm_kzalloc(&pdev->dev, sizeof(*function),
659 					GFP_KERNEL);
660 		if (!function)
661 			return -ENOMEM;
662 
663 		mutex_lock(&info->mutex);
664 		radix_tree_insert(&pctl->pin_function_tree, i, function);
665 		mutex_unlock(&info->mutex);
666 	}
667 	pctl->num_functions = nfuncs;
668 
669 	info->group_index = 0;
670 	if (flat_funcs) {
671 		pctl->num_groups = of_get_child_count(np);
672 	} else {
673 		pctl->num_groups = 0;
674 		for_each_child_of_node(np, child)
675 			pctl->num_groups += of_get_child_count(child);
676 	}
677 
678 	if (flat_funcs) {
679 		imx_pinctrl_parse_functions(np, ipctl, 0);
680 	} else {
681 		i = 0;
682 		for_each_child_of_node(np, child)
683 			imx_pinctrl_parse_functions(child, ipctl, i++);
684 	}
685 
686 	return 0;
687 }
688 
689 /*
690  * imx_free_resources() - free memory used by this driver
691  * @info: info driver instance
692  */
693 static void imx_free_resources(struct imx_pinctrl *ipctl)
694 {
695 	if (ipctl->pctl)
696 		pinctrl_unregister(ipctl->pctl);
697 }
698 
699 int imx_pinctrl_probe(struct platform_device *pdev,
700 		      struct imx_pinctrl_soc_info *info)
701 {
702 	struct regmap_config config = { .name = "gpr" };
703 	struct device_node *dev_np = pdev->dev.of_node;
704 	struct pinctrl_desc *imx_pinctrl_desc;
705 	struct device_node *np;
706 	struct imx_pinctrl *ipctl;
707 	struct resource *res;
708 	struct regmap *gpr;
709 	int ret, i;
710 
711 	if (!info || !info->pins || !info->npins) {
712 		dev_err(&pdev->dev, "wrong pinctrl info\n");
713 		return -EINVAL;
714 	}
715 	info->dev = &pdev->dev;
716 
717 	if (info->gpr_compatible) {
718 		gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
719 		if (!IS_ERR(gpr))
720 			regmap_attach_dev(&pdev->dev, gpr, &config);
721 	}
722 
723 	/* Create state holders etc for this driver */
724 	ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
725 	if (!ipctl)
726 		return -ENOMEM;
727 
728 	info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) *
729 				      info->npins, GFP_KERNEL);
730 	if (!info->pin_regs)
731 		return -ENOMEM;
732 
733 	for (i = 0; i < info->npins; i++) {
734 		info->pin_regs[i].mux_reg = -1;
735 		info->pin_regs[i].conf_reg = -1;
736 	}
737 
738 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
739 	ipctl->base = devm_ioremap_resource(&pdev->dev, res);
740 	if (IS_ERR(ipctl->base))
741 		return PTR_ERR(ipctl->base);
742 
743 	if (of_property_read_bool(dev_np, "fsl,input-sel")) {
744 		np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
745 		if (!np) {
746 			dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
747 			return -EINVAL;
748 		}
749 
750 		ipctl->input_sel_base = of_iomap(np, 0);
751 		of_node_put(np);
752 		if (!ipctl->input_sel_base) {
753 			dev_err(&pdev->dev,
754 				"iomuxc input select base address not found\n");
755 			return -ENOMEM;
756 		}
757 	}
758 
759 	imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc),
760 					GFP_KERNEL);
761 	if (!imx_pinctrl_desc)
762 		return -ENOMEM;
763 
764 	imx_pinctrl_desc->name = dev_name(&pdev->dev);
765 	imx_pinctrl_desc->pins = info->pins;
766 	imx_pinctrl_desc->npins = info->npins;
767 	imx_pinctrl_desc->pctlops = &imx_pctrl_ops;
768 	imx_pinctrl_desc->pmxops = &imx_pmx_ops;
769 	imx_pinctrl_desc->confops = &imx_pinconf_ops;
770 	imx_pinctrl_desc->owner = THIS_MODULE;
771 
772 	mutex_init(&info->mutex);
773 
774 	ipctl->info = info;
775 	ipctl->dev = info->dev;
776 	platform_set_drvdata(pdev, ipctl);
777 	ret = devm_pinctrl_register_and_init(&pdev->dev,
778 					     imx_pinctrl_desc, ipctl,
779 					     &ipctl->pctl);
780 	if (ret) {
781 		dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
782 		goto free;
783 	}
784 
785 	ret = imx_pinctrl_probe_dt(pdev, ipctl);
786 	if (ret) {
787 		dev_err(&pdev->dev, "fail to probe dt properties\n");
788 		goto free;
789 	}
790 
791 	dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
792 
793 	return pinctrl_enable(ipctl->pctl);
794 
795 free:
796 	imx_free_resources(ipctl);
797 
798 	return ret;
799 }
800