1 /* 2 * Core driver for the imx pin controller 3 * 4 * Copyright (C) 2012 Freescale Semiconductor, Inc. 5 * Copyright (C) 2012 Linaro Ltd. 6 * 7 * Author: Dong Aisheng <dong.aisheng@linaro.org> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #include <linux/err.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 #include <linux/slab.h> 26 27 #include "../core.h" 28 #include "pinctrl-imx.h" 29 30 /* The bits in CONFIG cell defined in binding doc*/ 31 #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ 32 #define IMX_PAD_SION 0x40000000 /* set SION */ 33 34 /** 35 * @dev: a pointer back to containing device 36 * @base: the offset to the controller in virtual memory 37 */ 38 struct imx_pinctrl { 39 struct device *dev; 40 struct pinctrl_dev *pctl; 41 void __iomem *base; 42 const struct imx_pinctrl_soc_info *info; 43 }; 44 45 static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name( 46 const struct imx_pinctrl_soc_info *info, 47 const char *name) 48 { 49 const struct imx_pin_group *grp = NULL; 50 int i; 51 52 for (i = 0; i < info->ngroups; i++) { 53 if (!strcmp(info->groups[i].name, name)) { 54 grp = &info->groups[i]; 55 break; 56 } 57 } 58 59 return grp; 60 } 61 62 static int imx_get_groups_count(struct pinctrl_dev *pctldev) 63 { 64 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 65 const struct imx_pinctrl_soc_info *info = ipctl->info; 66 67 return info->ngroups; 68 } 69 70 static const char *imx_get_group_name(struct pinctrl_dev *pctldev, 71 unsigned selector) 72 { 73 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 74 const struct imx_pinctrl_soc_info *info = ipctl->info; 75 76 return info->groups[selector].name; 77 } 78 79 static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 80 const unsigned **pins, 81 unsigned *npins) 82 { 83 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 84 const struct imx_pinctrl_soc_info *info = ipctl->info; 85 86 if (selector >= info->ngroups) 87 return -EINVAL; 88 89 *pins = info->groups[selector].pin_ids; 90 *npins = info->groups[selector].npins; 91 92 return 0; 93 } 94 95 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 96 unsigned offset) 97 { 98 seq_printf(s, "%s", dev_name(pctldev->dev)); 99 } 100 101 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, 102 struct device_node *np, 103 struct pinctrl_map **map, unsigned *num_maps) 104 { 105 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 106 const struct imx_pinctrl_soc_info *info = ipctl->info; 107 const struct imx_pin_group *grp; 108 struct pinctrl_map *new_map; 109 struct device_node *parent; 110 int map_num = 1; 111 int i, j; 112 113 /* 114 * first find the group of this node and check if we need create 115 * config maps for pins 116 */ 117 grp = imx_pinctrl_find_group_by_name(info, np->name); 118 if (!grp) { 119 dev_err(info->dev, "unable to find group for node %s\n", 120 np->name); 121 return -EINVAL; 122 } 123 124 for (i = 0; i < grp->npins; i++) { 125 if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) 126 map_num++; 127 } 128 129 new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); 130 if (!new_map) 131 return -ENOMEM; 132 133 *map = new_map; 134 *num_maps = map_num; 135 136 /* create mux map */ 137 parent = of_get_parent(np); 138 if (!parent) { 139 kfree(new_map); 140 return -EINVAL; 141 } 142 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 143 new_map[0].data.mux.function = parent->name; 144 new_map[0].data.mux.group = np->name; 145 of_node_put(parent); 146 147 /* create config map */ 148 new_map++; 149 for (i = j = 0; i < grp->npins; i++) { 150 if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) { 151 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; 152 new_map[j].data.configs.group_or_pin = 153 pin_get_name(pctldev, grp->pins[i].pin); 154 new_map[j].data.configs.configs = &grp->pins[i].config; 155 new_map[j].data.configs.num_configs = 1; 156 j++; 157 } 158 } 159 160 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 161 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 162 163 return 0; 164 } 165 166 static void imx_dt_free_map(struct pinctrl_dev *pctldev, 167 struct pinctrl_map *map, unsigned num_maps) 168 { 169 kfree(map); 170 } 171 172 static const struct pinctrl_ops imx_pctrl_ops = { 173 .get_groups_count = imx_get_groups_count, 174 .get_group_name = imx_get_group_name, 175 .get_group_pins = imx_get_group_pins, 176 .pin_dbg_show = imx_pin_dbg_show, 177 .dt_node_to_map = imx_dt_node_to_map, 178 .dt_free_map = imx_dt_free_map, 179 180 }; 181 182 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 183 unsigned group) 184 { 185 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 186 const struct imx_pinctrl_soc_info *info = ipctl->info; 187 const struct imx_pin_reg *pin_reg; 188 unsigned int npins, pin_id; 189 int i; 190 struct imx_pin_group *grp; 191 192 /* 193 * Configure the mux mode for each pin in the group for a specific 194 * function. 195 */ 196 grp = &info->groups[group]; 197 npins = grp->npins; 198 199 dev_dbg(ipctl->dev, "enable function %s group %s\n", 200 info->functions[selector].name, grp->name); 201 202 for (i = 0; i < npins; i++) { 203 struct imx_pin *pin = &grp->pins[i]; 204 pin_id = pin->pin; 205 pin_reg = &info->pin_regs[pin_id]; 206 207 if (pin_reg->mux_reg == -1) { 208 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", 209 info->pins[pin_id].name); 210 return -EINVAL; 211 } 212 213 if (info->flags & SHARE_MUX_CONF_REG) { 214 u32 reg; 215 reg = readl(ipctl->base + pin_reg->mux_reg); 216 reg &= ~(0x7 << 20); 217 reg |= (pin->mux_mode << 20); 218 writel(reg, ipctl->base + pin_reg->mux_reg); 219 } else { 220 writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); 221 } 222 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 223 pin_reg->mux_reg, pin->mux_mode); 224 225 /* 226 * If the select input value begins with 0xff, it's a quirky 227 * select input and the value should be interpreted as below. 228 * 31 23 15 7 0 229 * | 0xff | shift | width | select | 230 * It's used to work around the problem that the select 231 * input for some pin is not implemented in the select 232 * input register but in some general purpose register. 233 * We encode the select input value, width and shift of 234 * the bit field into input_val cell of pin function ID 235 * in device tree, and then decode them here for setting 236 * up the select input bits in general purpose register. 237 */ 238 if (pin->input_val >> 24 == 0xff) { 239 u32 val = pin->input_val; 240 u8 select = val & 0xff; 241 u8 width = (val >> 8) & 0xff; 242 u8 shift = (val >> 16) & 0xff; 243 u32 mask = ((1 << width) - 1) << shift; 244 /* 245 * The input_reg[i] here is actually some IOMUXC general 246 * purpose register, not regular select input register. 247 */ 248 val = readl(ipctl->base + pin->input_reg); 249 val &= ~mask; 250 val |= select << shift; 251 writel(val, ipctl->base + pin->input_reg); 252 } else if (pin->input_reg) { 253 /* 254 * Regular select input register can never be at offset 255 * 0, and we only print register value for regular case. 256 */ 257 writel(pin->input_val, ipctl->base + pin->input_reg); 258 dev_dbg(ipctl->dev, 259 "==>select_input: offset 0x%x val 0x%x\n", 260 pin->input_reg, pin->input_val); 261 } 262 } 263 264 return 0; 265 } 266 267 static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 268 { 269 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 270 const struct imx_pinctrl_soc_info *info = ipctl->info; 271 272 return info->nfunctions; 273 } 274 275 static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev, 276 unsigned selector) 277 { 278 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 279 const struct imx_pinctrl_soc_info *info = ipctl->info; 280 281 return info->functions[selector].name; 282 } 283 284 static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 285 const char * const **groups, 286 unsigned * const num_groups) 287 { 288 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 289 const struct imx_pinctrl_soc_info *info = ipctl->info; 290 291 *groups = info->functions[selector].groups; 292 *num_groups = info->functions[selector].num_groups; 293 294 return 0; 295 } 296 297 static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, 298 struct pinctrl_gpio_range *range, unsigned offset) 299 { 300 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 301 const struct imx_pinctrl_soc_info *info = ipctl->info; 302 const struct imx_pin_reg *pin_reg; 303 struct imx_pin_group *grp; 304 struct imx_pin *imx_pin; 305 unsigned int pin, group; 306 u32 reg; 307 308 /* Currently implementation only for shared mux/conf register */ 309 if (!(info->flags & SHARE_MUX_CONF_REG)) 310 return -EINVAL; 311 312 pin_reg = &info->pin_regs[offset]; 313 if (pin_reg->mux_reg == -1) 314 return -EINVAL; 315 316 /* Find the pinctrl config with GPIO mux mode for the requested pin */ 317 for (group = 0; group < info->ngroups; group++) { 318 grp = &info->groups[group]; 319 for (pin = 0; pin < grp->npins; pin++) { 320 imx_pin = &grp->pins[pin]; 321 if (imx_pin->pin == offset && !imx_pin->mux_mode) 322 goto mux_pin; 323 } 324 } 325 326 return -EINVAL; 327 328 mux_pin: 329 reg = readl(ipctl->base + pin_reg->mux_reg); 330 reg &= ~(0x7 << 20); 331 reg |= imx_pin->config; 332 writel(reg, ipctl->base + pin_reg->mux_reg); 333 334 return 0; 335 } 336 337 static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 338 struct pinctrl_gpio_range *range, unsigned offset, bool input) 339 { 340 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 341 const struct imx_pinctrl_soc_info *info = ipctl->info; 342 const struct imx_pin_reg *pin_reg; 343 u32 reg; 344 345 /* 346 * Only Vybrid has the input/output buffer enable flags (IBE/OBE) 347 * They are part of the shared mux/conf register. 348 */ 349 if (!(info->flags & SHARE_MUX_CONF_REG)) 350 return -EINVAL; 351 352 pin_reg = &info->pin_regs[offset]; 353 if (pin_reg->mux_reg == -1) 354 return -EINVAL; 355 356 /* IBE always enabled allows us to read the value "on the wire" */ 357 reg = readl(ipctl->base + pin_reg->mux_reg); 358 if (input) 359 reg &= ~0x2; 360 else 361 reg |= 0x2; 362 writel(reg, ipctl->base + pin_reg->mux_reg); 363 364 return 0; 365 } 366 367 static const struct pinmux_ops imx_pmx_ops = { 368 .get_functions_count = imx_pmx_get_funcs_count, 369 .get_function_name = imx_pmx_get_func_name, 370 .get_function_groups = imx_pmx_get_groups, 371 .set_mux = imx_pmx_set, 372 .gpio_request_enable = imx_pmx_gpio_request_enable, 373 .gpio_set_direction = imx_pmx_gpio_set_direction, 374 }; 375 376 static int imx_pinconf_get(struct pinctrl_dev *pctldev, 377 unsigned pin_id, unsigned long *config) 378 { 379 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 380 const struct imx_pinctrl_soc_info *info = ipctl->info; 381 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 382 383 if (pin_reg->conf_reg == -1) { 384 dev_err(info->dev, "Pin(%s) does not support config function\n", 385 info->pins[pin_id].name); 386 return -EINVAL; 387 } 388 389 *config = readl(ipctl->base + pin_reg->conf_reg); 390 391 if (info->flags & SHARE_MUX_CONF_REG) 392 *config &= 0xffff; 393 394 return 0; 395 } 396 397 static int imx_pinconf_set(struct pinctrl_dev *pctldev, 398 unsigned pin_id, unsigned long *configs, 399 unsigned num_configs) 400 { 401 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 402 const struct imx_pinctrl_soc_info *info = ipctl->info; 403 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 404 int i; 405 406 if (pin_reg->conf_reg == -1) { 407 dev_err(info->dev, "Pin(%s) does not support config function\n", 408 info->pins[pin_id].name); 409 return -EINVAL; 410 } 411 412 dev_dbg(ipctl->dev, "pinconf set pin %s\n", 413 info->pins[pin_id].name); 414 415 for (i = 0; i < num_configs; i++) { 416 if (info->flags & SHARE_MUX_CONF_REG) { 417 u32 reg; 418 reg = readl(ipctl->base + pin_reg->conf_reg); 419 reg &= ~0xffff; 420 reg |= configs[i]; 421 writel(reg, ipctl->base + pin_reg->conf_reg); 422 } else { 423 writel(configs[i], ipctl->base + pin_reg->conf_reg); 424 } 425 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", 426 pin_reg->conf_reg, configs[i]); 427 } /* for each config */ 428 429 return 0; 430 } 431 432 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 433 struct seq_file *s, unsigned pin_id) 434 { 435 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 436 const struct imx_pinctrl_soc_info *info = ipctl->info; 437 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 438 unsigned long config; 439 440 if (!pin_reg || pin_reg->conf_reg == -1) { 441 seq_printf(s, "N/A"); 442 return; 443 } 444 445 config = readl(ipctl->base + pin_reg->conf_reg); 446 seq_printf(s, "0x%lx", config); 447 } 448 449 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 450 struct seq_file *s, unsigned group) 451 { 452 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 453 const struct imx_pinctrl_soc_info *info = ipctl->info; 454 struct imx_pin_group *grp; 455 unsigned long config; 456 const char *name; 457 int i, ret; 458 459 if (group > info->ngroups) 460 return; 461 462 seq_printf(s, "\n"); 463 grp = &info->groups[group]; 464 for (i = 0; i < grp->npins; i++) { 465 struct imx_pin *pin = &grp->pins[i]; 466 name = pin_get_name(pctldev, pin->pin); 467 ret = imx_pinconf_get(pctldev, pin->pin, &config); 468 if (ret) 469 return; 470 seq_printf(s, "%s: 0x%lx", name, config); 471 } 472 } 473 474 static const struct pinconf_ops imx_pinconf_ops = { 475 .pin_config_get = imx_pinconf_get, 476 .pin_config_set = imx_pinconf_set, 477 .pin_config_dbg_show = imx_pinconf_dbg_show, 478 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, 479 }; 480 481 static struct pinctrl_desc imx_pinctrl_desc = { 482 .pctlops = &imx_pctrl_ops, 483 .pmxops = &imx_pmx_ops, 484 .confops = &imx_pinconf_ops, 485 .owner = THIS_MODULE, 486 }; 487 488 /* 489 * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and 490 * 1 u32 CONFIG, so 24 types in total for each pin. 491 */ 492 #define FSL_PIN_SIZE 24 493 #define SHARE_FSL_PIN_SIZE 20 494 495 static int imx_pinctrl_parse_groups(struct device_node *np, 496 struct imx_pin_group *grp, 497 struct imx_pinctrl_soc_info *info, 498 u32 index) 499 { 500 int size, pin_size; 501 const __be32 *list; 502 int i; 503 u32 config; 504 505 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 506 507 if (info->flags & SHARE_MUX_CONF_REG) 508 pin_size = SHARE_FSL_PIN_SIZE; 509 else 510 pin_size = FSL_PIN_SIZE; 511 /* Initialise group */ 512 grp->name = np->name; 513 514 /* 515 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, 516 * do sanity check and calculate pins number 517 */ 518 list = of_get_property(np, "fsl,pins", &size); 519 if (!list) { 520 dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name); 521 return -EINVAL; 522 } 523 524 /* we do not check return since it's safe node passed down */ 525 if (!size || size % pin_size) { 526 dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name); 527 return -EINVAL; 528 } 529 530 grp->npins = size / pin_size; 531 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin), 532 GFP_KERNEL); 533 grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 534 GFP_KERNEL); 535 if (!grp->pins || ! grp->pin_ids) 536 return -ENOMEM; 537 538 for (i = 0; i < grp->npins; i++) { 539 u32 mux_reg = be32_to_cpu(*list++); 540 u32 conf_reg; 541 unsigned int pin_id; 542 struct imx_pin_reg *pin_reg; 543 struct imx_pin *pin = &grp->pins[i]; 544 545 if (info->flags & SHARE_MUX_CONF_REG) { 546 conf_reg = mux_reg; 547 } else { 548 conf_reg = be32_to_cpu(*list++); 549 if (!conf_reg) 550 conf_reg = -1; 551 } 552 553 pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; 554 pin_reg = &info->pin_regs[pin_id]; 555 pin->pin = pin_id; 556 grp->pin_ids[i] = pin_id; 557 pin_reg->mux_reg = mux_reg; 558 pin_reg->conf_reg = conf_reg; 559 pin->input_reg = be32_to_cpu(*list++); 560 pin->mux_mode = be32_to_cpu(*list++); 561 pin->input_val = be32_to_cpu(*list++); 562 563 /* SION bit is in mux register */ 564 config = be32_to_cpu(*list++); 565 if (config & IMX_PAD_SION) 566 pin->mux_mode |= IOMUXC_CONFIG_SION; 567 pin->config = config & ~IMX_PAD_SION; 568 569 dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, 570 pin->mux_mode, pin->config); 571 } 572 573 return 0; 574 } 575 576 static int imx_pinctrl_parse_functions(struct device_node *np, 577 struct imx_pinctrl_soc_info *info, 578 u32 index) 579 { 580 struct device_node *child; 581 struct imx_pmx_func *func; 582 struct imx_pin_group *grp; 583 static u32 grp_index; 584 u32 i = 0; 585 586 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 587 588 func = &info->functions[index]; 589 590 /* Initialise function */ 591 func->name = np->name; 592 func->num_groups = of_get_child_count(np); 593 if (func->num_groups == 0) { 594 dev_err(info->dev, "no groups defined in %s\n", np->full_name); 595 return -EINVAL; 596 } 597 func->groups = devm_kzalloc(info->dev, 598 func->num_groups * sizeof(char *), GFP_KERNEL); 599 600 for_each_child_of_node(np, child) { 601 func->groups[i] = child->name; 602 grp = &info->groups[grp_index++]; 603 imx_pinctrl_parse_groups(child, grp, info, i++); 604 } 605 606 return 0; 607 } 608 609 /* 610 * Check if the DT contains pins in the direct child nodes. This indicates the 611 * newer DT format to store pins. This function returns true if the first found 612 * fsl,pins property is in a child of np. Otherwise false is returned. 613 */ 614 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) 615 { 616 struct device_node *function_np; 617 struct device_node *pinctrl_np; 618 619 for_each_child_of_node(np, function_np) { 620 if (of_property_read_bool(function_np, "fsl,pins")) 621 return true; 622 623 for_each_child_of_node(function_np, pinctrl_np) { 624 if (of_property_read_bool(pinctrl_np, "fsl,pins")) 625 return false; 626 } 627 } 628 629 return true; 630 } 631 632 static int imx_pinctrl_probe_dt(struct platform_device *pdev, 633 struct imx_pinctrl_soc_info *info) 634 { 635 struct device_node *np = pdev->dev.of_node; 636 struct device_node *child; 637 u32 nfuncs = 0; 638 u32 i = 0; 639 bool flat_funcs; 640 641 if (!np) 642 return -ENODEV; 643 644 flat_funcs = imx_pinctrl_dt_is_flat_functions(np); 645 if (flat_funcs) { 646 nfuncs = 1; 647 } else { 648 nfuncs = of_get_child_count(np); 649 if (nfuncs <= 0) { 650 dev_err(&pdev->dev, "no functions defined\n"); 651 return -EINVAL; 652 } 653 } 654 655 info->nfunctions = nfuncs; 656 info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func), 657 GFP_KERNEL); 658 if (!info->functions) 659 return -ENOMEM; 660 661 if (flat_funcs) { 662 info->ngroups = of_get_child_count(np); 663 } else { 664 info->ngroups = 0; 665 for_each_child_of_node(np, child) 666 info->ngroups += of_get_child_count(child); 667 } 668 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group), 669 GFP_KERNEL); 670 if (!info->groups) 671 return -ENOMEM; 672 673 if (flat_funcs) { 674 imx_pinctrl_parse_functions(np, info, 0); 675 } else { 676 for_each_child_of_node(np, child) 677 imx_pinctrl_parse_functions(child, info, i++); 678 } 679 680 return 0; 681 } 682 683 int imx_pinctrl_probe(struct platform_device *pdev, 684 struct imx_pinctrl_soc_info *info) 685 { 686 struct imx_pinctrl *ipctl; 687 struct resource *res; 688 int ret, i; 689 690 if (!info || !info->pins || !info->npins) { 691 dev_err(&pdev->dev, "wrong pinctrl info\n"); 692 return -EINVAL; 693 } 694 info->dev = &pdev->dev; 695 696 /* Create state holders etc for this driver */ 697 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 698 if (!ipctl) 699 return -ENOMEM; 700 701 info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) * 702 info->npins, GFP_KERNEL); 703 if (!info->pin_regs) 704 return -ENOMEM; 705 706 for (i = 0; i < info->npins; i++) { 707 info->pin_regs[i].mux_reg = -1; 708 info->pin_regs[i].conf_reg = -1; 709 } 710 711 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 712 ipctl->base = devm_ioremap_resource(&pdev->dev, res); 713 if (IS_ERR(ipctl->base)) 714 return PTR_ERR(ipctl->base); 715 716 imx_pinctrl_desc.name = dev_name(&pdev->dev); 717 imx_pinctrl_desc.pins = info->pins; 718 imx_pinctrl_desc.npins = info->npins; 719 720 ret = imx_pinctrl_probe_dt(pdev, info); 721 if (ret) { 722 dev_err(&pdev->dev, "fail to probe dt properties\n"); 723 return ret; 724 } 725 726 ipctl->info = info; 727 ipctl->dev = info->dev; 728 platform_set_drvdata(pdev, ipctl); 729 ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl); 730 if (IS_ERR(ipctl->pctl)) { 731 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); 732 return PTR_ERR(ipctl->pctl); 733 } 734 735 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); 736 737 return 0; 738 } 739 740 int imx_pinctrl_remove(struct platform_device *pdev) 741 { 742 struct imx_pinctrl *ipctl = platform_get_drvdata(pdev); 743 744 pinctrl_unregister(ipctl->pctl); 745 746 return 0; 747 } 748