1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Core driver for the imx pin controller 4 // 5 // Copyright (C) 2012 Freescale Semiconductor, Inc. 6 // Copyright (C) 2012 Linaro Ltd. 7 // 8 // Author: Dong Aisheng <dong.aisheng@linaro.org> 9 10 #include <linux/err.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/platform_device.h> 18 #include <linux/regmap.h> 19 #include <linux/seq_file.h> 20 #include <linux/slab.h> 21 22 #include <linux/pinctrl/machine.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 27 #include "../core.h" 28 #include "../pinconf.h" 29 #include "../pinmux.h" 30 #include "pinctrl-imx.h" 31 32 /* The bits in CONFIG cell defined in binding doc*/ 33 #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ 34 #define IMX_PAD_SION 0x40000000 /* set SION */ 35 36 static inline const struct group_desc *imx_pinctrl_find_group_by_name( 37 struct pinctrl_dev *pctldev, 38 const char *name) 39 { 40 const struct group_desc *grp; 41 int i; 42 43 for (i = 0; i < pctldev->num_groups; i++) { 44 grp = pinctrl_generic_get_group(pctldev, i); 45 if (grp && !strcmp(grp->grp.name, name)) 46 return grp; 47 } 48 49 return NULL; 50 } 51 52 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 53 unsigned offset) 54 { 55 seq_printf(s, "%s", dev_name(pctldev->dev)); 56 } 57 58 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, 59 struct device_node *np, 60 struct pinctrl_map **map, unsigned *num_maps) 61 { 62 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 63 const struct imx_pinctrl_soc_info *info = ipctl->info; 64 const struct group_desc *grp; 65 struct pinctrl_map *new_map; 66 struct device_node *parent; 67 struct imx_pin *pin; 68 int map_num = 1; 69 int i, j; 70 71 /* 72 * first find the group of this node and check if we need create 73 * config maps for pins 74 */ 75 grp = imx_pinctrl_find_group_by_name(pctldev, np->name); 76 if (!grp) { 77 dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np); 78 return -EINVAL; 79 } 80 81 if (info->flags & IMX_USE_SCU) { 82 map_num += grp->grp.npins; 83 } else { 84 for (i = 0; i < grp->grp.npins; i++) { 85 pin = &((struct imx_pin *)(grp->data))[i]; 86 if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) 87 map_num++; 88 } 89 } 90 91 new_map = kmalloc_objs(struct pinctrl_map, map_num); 92 if (!new_map) 93 return -ENOMEM; 94 95 *map = new_map; 96 *num_maps = map_num; 97 98 /* create mux map */ 99 parent = of_get_parent(np); 100 if (!parent) { 101 kfree(new_map); 102 return -EINVAL; 103 } 104 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 105 new_map[0].data.mux.function = parent->name; 106 new_map[0].data.mux.group = np->name; 107 of_node_put(parent); 108 109 /* create config map */ 110 new_map++; 111 for (i = j = 0; i < grp->grp.npins; i++) { 112 pin = &((struct imx_pin *)(grp->data))[i]; 113 114 /* 115 * We only create config maps for SCU pads or MMIO pads that 116 * are not using the default config(a.k.a IMX_NO_PAD_CTL) 117 */ 118 if (!(info->flags & IMX_USE_SCU) && 119 (pin->conf.mmio.config & IMX_NO_PAD_CTL)) 120 continue; 121 122 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; 123 new_map[j].data.configs.group_or_pin = 124 pin_get_name(pctldev, pin->pin); 125 126 if (info->flags & IMX_USE_SCU) { 127 /* 128 * For SCU case, we set mux and conf together 129 * in one IPC call 130 */ 131 new_map[j].data.configs.configs = 132 (unsigned long *)&pin->conf.scu; 133 new_map[j].data.configs.num_configs = 2; 134 } else { 135 new_map[j].data.configs.configs = 136 &pin->conf.mmio.config; 137 new_map[j].data.configs.num_configs = 1; 138 } 139 140 j++; 141 } 142 143 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 144 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 145 146 return 0; 147 } 148 149 static void imx_dt_free_map(struct pinctrl_dev *pctldev, 150 struct pinctrl_map *map, unsigned num_maps) 151 { 152 kfree(map); 153 } 154 155 static const struct pinctrl_ops imx_pctrl_ops = { 156 .get_groups_count = pinctrl_generic_get_group_count, 157 .get_group_name = pinctrl_generic_get_group_name, 158 .get_group_pins = pinctrl_generic_get_group_pins, 159 .pin_dbg_show = imx_pin_dbg_show, 160 .dt_node_to_map = imx_dt_node_to_map, 161 .dt_free_map = imx_dt_free_map, 162 }; 163 164 static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl, 165 struct imx_pin *pin) 166 { 167 const struct imx_pinctrl_soc_info *info = ipctl->info; 168 struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; 169 const struct imx_pin_reg *pin_reg; 170 unsigned int pin_id; 171 172 pin_id = pin->pin; 173 pin_reg = &ipctl->pin_regs[pin_id]; 174 175 if (pin_reg->mux_reg == -1) { 176 dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", 177 info->pins[pin_id].name); 178 return 0; 179 } 180 181 if (info->flags & SHARE_MUX_CONF_REG) { 182 u32 reg; 183 184 reg = readl(ipctl->base + pin_reg->mux_reg); 185 reg &= ~info->mux_mask; 186 reg |= (pin_mmio->mux_mode << info->mux_shift); 187 writel(reg, ipctl->base + pin_reg->mux_reg); 188 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 189 pin_reg->mux_reg, reg); 190 } else { 191 writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg); 192 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 193 pin_reg->mux_reg, pin_mmio->mux_mode); 194 } 195 196 /* 197 * If the select input value begins with 0xff, it's a quirky 198 * select input and the value should be interpreted as below. 199 * 31 23 15 7 0 200 * | 0xff | shift | width | select | 201 * It's used to work around the problem that the select 202 * input for some pin is not implemented in the select 203 * input register but in some general purpose register. 204 * We encode the select input value, width and shift of 205 * the bit field into input_val cell of pin function ID 206 * in device tree, and then decode them here for setting 207 * up the select input bits in general purpose register. 208 */ 209 if (pin_mmio->input_val >> 24 == 0xff) { 210 u32 val = pin_mmio->input_val; 211 u8 select = val & 0xff; 212 u8 width = (val >> 8) & 0xff; 213 u8 shift = (val >> 16) & 0xff; 214 u32 mask = ((1 << width) - 1) << shift; 215 /* 216 * The input_reg[i] here is actually some IOMUXC general 217 * purpose register, not regular select input register. 218 */ 219 val = readl(ipctl->base + pin_mmio->input_reg); 220 val &= ~mask; 221 val |= select << shift; 222 writel(val, ipctl->base + pin_mmio->input_reg); 223 } else if (pin_mmio->input_reg) { 224 /* 225 * Regular select input register can never be at offset 226 * 0, and we only print register value for regular case. 227 */ 228 if (ipctl->input_sel_base) 229 writel(pin_mmio->input_val, ipctl->input_sel_base + 230 pin_mmio->input_reg); 231 else 232 writel(pin_mmio->input_val, ipctl->base + 233 pin_mmio->input_reg); 234 dev_dbg(ipctl->dev, 235 "==>select_input: offset 0x%x val 0x%x\n", 236 pin_mmio->input_reg, pin_mmio->input_val); 237 } 238 239 return 0; 240 } 241 242 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 243 unsigned group) 244 { 245 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 246 const struct imx_pinctrl_soc_info *info = ipctl->info; 247 const struct function_desc *func; 248 struct group_desc *grp; 249 struct imx_pin *pin; 250 unsigned int npins; 251 int i, err; 252 253 /* 254 * Configure the mux mode for each pin in the group for a specific 255 * function. 256 */ 257 grp = pinctrl_generic_get_group(pctldev, group); 258 if (!grp) 259 return -EINVAL; 260 261 func = pinmux_generic_get_function(pctldev, selector); 262 if (!func) 263 return -EINVAL; 264 265 npins = grp->grp.npins; 266 267 dev_dbg(ipctl->dev, "enable function %s group %s\n", 268 func->func->name, grp->grp.name); 269 270 for (i = 0; i < npins; i++) { 271 /* 272 * For IMX_USE_SCU case, we postpone the mux setting 273 * until config is set as we can set them together 274 * in one IPC call 275 */ 276 pin = &((struct imx_pin *)(grp->data))[i]; 277 if (!(info->flags & IMX_USE_SCU)) { 278 err = imx_pmx_set_one_pin_mmio(ipctl, pin); 279 if (err) 280 return err; 281 } 282 } 283 284 return 0; 285 } 286 287 struct pinmux_ops imx_pmx_ops = { 288 .get_functions_count = pinmux_generic_get_function_count, 289 .get_function_name = pinmux_generic_get_function_name, 290 .get_function_groups = pinmux_generic_get_function_groups, 291 .set_mux = imx_pmx_set, 292 }; 293 294 static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id, 295 unsigned long *config) 296 { 297 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 298 const struct imx_pinctrl_soc_info *info = ipctl->info; 299 const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; 300 301 if (pin_reg->conf_reg == -1) { 302 dev_err(ipctl->dev, "Pin(%s) does not support config function\n", 303 info->pins[pin_id].name); 304 return -EINVAL; 305 } 306 307 *config = readl(ipctl->base + pin_reg->conf_reg); 308 309 if (info->flags & SHARE_MUX_CONF_REG) 310 *config &= ~info->mux_mask; 311 312 return 0; 313 } 314 315 static int imx_pinconf_get(struct pinctrl_dev *pctldev, 316 unsigned pin_id, unsigned long *config) 317 { 318 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 319 const struct imx_pinctrl_soc_info *info = ipctl->info; 320 321 if (info->flags & IMX_USE_SCU) 322 return info->imx_pinconf_get(pctldev, pin_id, config); 323 else 324 return imx_pinconf_get_mmio(pctldev, pin_id, config); 325 } 326 327 static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev, 328 unsigned pin_id, unsigned long *configs, 329 unsigned num_configs) 330 { 331 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 332 const struct imx_pinctrl_soc_info *info = ipctl->info; 333 const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; 334 int i; 335 336 if (pin_reg->conf_reg == -1) { 337 dev_err(ipctl->dev, "Pin(%s) does not support config function\n", 338 info->pins[pin_id].name); 339 return -EINVAL; 340 } 341 342 dev_dbg(ipctl->dev, "pinconf set pin %s\n", 343 info->pins[pin_id].name); 344 345 for (i = 0; i < num_configs; i++) { 346 if (info->flags & SHARE_MUX_CONF_REG) { 347 u32 reg; 348 reg = readl(ipctl->base + pin_reg->conf_reg); 349 reg &= info->mux_mask; 350 reg |= configs[i]; 351 writel(reg, ipctl->base + pin_reg->conf_reg); 352 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 353 pin_reg->conf_reg, reg); 354 } else { 355 writel(configs[i], ipctl->base + pin_reg->conf_reg); 356 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", 357 pin_reg->conf_reg, configs[i]); 358 } 359 } /* for each config */ 360 361 return 0; 362 } 363 364 static int imx_pinconf_set(struct pinctrl_dev *pctldev, 365 unsigned pin_id, unsigned long *configs, 366 unsigned num_configs) 367 { 368 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 369 const struct imx_pinctrl_soc_info *info = ipctl->info; 370 371 if (info->flags & IMX_USE_SCU) 372 return info->imx_pinconf_set(pctldev, pin_id, 373 configs, num_configs); 374 else 375 return imx_pinconf_set_mmio(pctldev, pin_id, 376 configs, num_configs); 377 } 378 379 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 380 struct seq_file *s, unsigned pin_id) 381 { 382 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 383 const struct imx_pinctrl_soc_info *info = ipctl->info; 384 const struct imx_pin_reg *pin_reg; 385 unsigned long config; 386 int ret; 387 388 if (info->flags & IMX_USE_SCU) { 389 ret = info->imx_pinconf_get(pctldev, pin_id, &config); 390 if (ret) { 391 dev_err(ipctl->dev, "failed to get %s pinconf\n", 392 pin_get_name(pctldev, pin_id)); 393 seq_puts(s, "N/A"); 394 return; 395 } 396 } else { 397 pin_reg = &ipctl->pin_regs[pin_id]; 398 if (pin_reg->conf_reg == -1) { 399 seq_puts(s, "N/A"); 400 return; 401 } 402 403 config = readl(ipctl->base + pin_reg->conf_reg); 404 } 405 406 seq_printf(s, "0x%lx", config); 407 } 408 409 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 410 struct seq_file *s, unsigned group) 411 { 412 struct group_desc *grp; 413 unsigned long config; 414 const char *name; 415 int i, ret; 416 417 if (group >= pctldev->num_groups) 418 return; 419 420 seq_puts(s, "\n"); 421 grp = pinctrl_generic_get_group(pctldev, group); 422 if (!grp) 423 return; 424 425 for (i = 0; i < grp->grp.npins; i++) { 426 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 427 428 name = pin_get_name(pctldev, pin->pin); 429 ret = imx_pinconf_get(pctldev, pin->pin, &config); 430 if (ret) 431 return; 432 seq_printf(s, " %s: 0x%lx\n", name, config); 433 } 434 } 435 436 static const struct pinconf_ops imx_pinconf_ops = { 437 .pin_config_get = imx_pinconf_get, 438 .pin_config_set = imx_pinconf_set, 439 .pin_config_dbg_show = imx_pinconf_dbg_show, 440 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, 441 }; 442 443 /* 444 * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID 445 * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin. 446 * 447 * PIN_FUNC_ID format: 448 * Default: 449 * <mux_reg conf_reg input_reg mux_mode input_val> 450 * SHARE_MUX_CONF_REG: 451 * <mux_conf_reg input_reg mux_mode input_val> 452 * IMX_USE_SCU: 453 * <pin_id mux_mode> 454 */ 455 #define FSL_PIN_SIZE 24 456 #define FSL_PIN_SHARE_SIZE 20 457 #define FSL_SCU_PIN_SIZE 12 458 459 static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl, 460 unsigned int *pin_id, struct imx_pin *pin, 461 const __be32 **list_p, 462 struct device_node *np) 463 { 464 const struct imx_pinctrl_soc_info *info = ipctl->info; 465 struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; 466 struct imx_pin_reg *pin_reg; 467 const __be32 *list = *list_p; 468 u32 mux_reg, conf_reg; 469 u32 config; 470 471 mux_reg = be32_to_cpu(*list++); 472 473 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) 474 mux_reg = -1; 475 476 if (info->flags & SHARE_MUX_CONF_REG) { 477 conf_reg = mux_reg; 478 } else { 479 conf_reg = be32_to_cpu(*list++); 480 if (!conf_reg) 481 conf_reg = -1; 482 } 483 484 *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; 485 pin_reg = &ipctl->pin_regs[*pin_id]; 486 pin->pin = *pin_id; 487 pin_reg->mux_reg = mux_reg; 488 pin_reg->conf_reg = conf_reg; 489 pin_mmio->input_reg = be32_to_cpu(*list++); 490 pin_mmio->mux_mode = be32_to_cpu(*list++); 491 pin_mmio->input_val = be32_to_cpu(*list++); 492 493 config = be32_to_cpu(*list++); 494 495 /* SION bit is in mux register */ 496 if (config & IMX_PAD_SION) 497 pin_mmio->mux_mode |= IOMUXC_CONFIG_SION; 498 pin_mmio->config = config & ~IMX_PAD_SION; 499 500 *list_p = list; 501 502 dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name, 503 pin_mmio->mux_mode, pin_mmio->config); 504 } 505 506 static int imx_pinctrl_parse_groups(struct device_node *np, 507 struct group_desc *grp, 508 struct imx_pinctrl *ipctl, 509 u32 index) 510 { 511 const struct imx_pinctrl_soc_info *info = ipctl->info; 512 struct imx_pin *pin; 513 unsigned int *pins; 514 int size, pin_size; 515 const __be32 *list; 516 int i; 517 518 dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np); 519 520 if (info->flags & IMX_USE_SCU) 521 pin_size = FSL_SCU_PIN_SIZE; 522 else if (info->flags & SHARE_MUX_CONF_REG) 523 pin_size = FSL_PIN_SHARE_SIZE; 524 else 525 pin_size = FSL_PIN_SIZE; 526 527 /* Initialise group */ 528 grp->grp.name = np->name; 529 530 /* 531 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, 532 * do sanity check and calculate pins number 533 * 534 * First try legacy 'fsl,pins' property, then fall back to the 535 * generic 'pinmux'. 536 * 537 * Note: for generic 'pinmux' case, there's no CONFIG part in 538 * the binding format. 539 */ 540 list = of_get_property(np, "fsl,pins", &size); 541 if (!list) { 542 list = of_get_property(np, "pinmux", &size); 543 if (!list) { 544 dev_err(ipctl->dev, 545 "no fsl,pins and pins property in node %pOF\n", np); 546 return -EINVAL; 547 } 548 } 549 550 /* we do not check return since it's safe node passed down */ 551 if (!size || size % pin_size) { 552 dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np); 553 return -EINVAL; 554 } 555 556 grp->grp.npins = size / pin_size; 557 grp->data = devm_kcalloc(ipctl->dev, grp->grp.npins, sizeof(*pin), GFP_KERNEL); 558 if (!grp->data) 559 return -ENOMEM; 560 561 pins = devm_kcalloc(ipctl->dev, grp->grp.npins, sizeof(*pins), GFP_KERNEL); 562 if (!pins) 563 return -ENOMEM; 564 grp->grp.pins = pins; 565 566 for (i = 0; i < grp->grp.npins; i++) { 567 pin = &((struct imx_pin *)(grp->data))[i]; 568 if (info->flags & IMX_USE_SCU) 569 info->imx_pinctrl_parse_pin(ipctl, &pins[i], pin, &list); 570 else 571 imx_pinctrl_parse_pin_mmio(ipctl, &pins[i], pin, &list, np); 572 } 573 574 return 0; 575 } 576 577 static int imx_pinctrl_parse_functions(struct device_node *np, 578 struct imx_pinctrl *ipctl, 579 u32 index) 580 { 581 struct pinctrl_dev *pctl = ipctl->pctl; 582 struct pinfunction *func; 583 struct group_desc *grp; 584 const char **group_names; 585 int ret; 586 u32 i; 587 588 dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np); 589 590 func = devm_kzalloc(ipctl->dev, sizeof(*func), GFP_KERNEL); 591 if (!func) 592 return -ENOMEM; 593 594 /* Initialise function */ 595 func->name = np->name; 596 func->ngroups = of_get_child_count(np); 597 if (func->ngroups == 0) { 598 dev_info(ipctl->dev, "no groups defined in %pOF\n", np); 599 return -EINVAL; 600 } 601 602 group_names = devm_kcalloc(ipctl->dev, func->ngroups, 603 sizeof(*func->groups), GFP_KERNEL); 604 if (!group_names) 605 return -ENOMEM; 606 i = 0; 607 for_each_child_of_node_scoped(np, child) 608 group_names[i++] = child->name; 609 func->groups = group_names; 610 611 ret = pinmux_generic_add_pinfunction(pctl, func, NULL); 612 if (ret < 0) 613 return ret; 614 615 i = 0; 616 for_each_child_of_node_scoped(np, child) { 617 grp = devm_kzalloc(ipctl->dev, sizeof(*grp), GFP_KERNEL); 618 if (!grp) 619 return -ENOMEM; 620 621 mutex_lock(&ipctl->mutex); 622 /* 623 * FIXME: This should use pinctrl_generic_add_group() and not 624 * access the private radix tree directly. 625 */ 626 radix_tree_insert(&pctl->pin_group_tree, 627 ipctl->group_index++, grp); 628 mutex_unlock(&ipctl->mutex); 629 630 imx_pinctrl_parse_groups(child, grp, ipctl, i++); 631 } 632 633 return 0; 634 } 635 636 /* 637 * Check if the DT contains pins in the direct child nodes. This indicates the 638 * newer DT format to store pins. This function returns true if the first found 639 * fsl,pins property is in a child of np. Otherwise false is returned. 640 */ 641 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) 642 { 643 for_each_child_of_node_scoped(np, function_np) { 644 if (of_property_present(function_np, "fsl,pins")) 645 return true; 646 647 for_each_child_of_node_scoped(function_np, pinctrl_np) { 648 if (of_property_present(pinctrl_np, "fsl,pins")) 649 return false; 650 } 651 } 652 653 return true; 654 } 655 656 static int imx_pinctrl_probe_dt(struct platform_device *pdev, 657 struct imx_pinctrl *ipctl) 658 { 659 struct device_node *np = pdev->dev.of_node; 660 struct device_node *child; 661 struct pinctrl_dev *pctl = ipctl->pctl; 662 u32 nfuncs = 0; 663 u32 i = 0; 664 bool flat_funcs; 665 666 if (!np) 667 return -ENODEV; 668 669 flat_funcs = imx_pinctrl_dt_is_flat_functions(np); 670 if (flat_funcs) { 671 nfuncs = 1; 672 } else { 673 nfuncs = of_get_child_count(np); 674 if (nfuncs == 0) { 675 dev_err(&pdev->dev, "no functions defined\n"); 676 return -EINVAL; 677 } 678 } 679 680 ipctl->group_index = 0; 681 if (flat_funcs) { 682 pctl->num_groups = of_get_child_count(np); 683 } else { 684 pctl->num_groups = 0; 685 for_each_child_of_node(np, child) 686 pctl->num_groups += of_get_child_count(child); 687 } 688 689 if (flat_funcs) { 690 imx_pinctrl_parse_functions(np, ipctl, 0); 691 } else { 692 i = 0; 693 for_each_child_of_node(np, child) 694 imx_pinctrl_parse_functions(child, ipctl, i++); 695 } 696 697 return 0; 698 } 699 700 int imx_pinctrl_probe(struct platform_device *pdev, 701 const struct imx_pinctrl_soc_info *info) 702 { 703 struct regmap_config config = { .name = "gpr" }; 704 struct device_node *dev_np = pdev->dev.of_node; 705 struct pinctrl_desc *imx_pinctrl_desc; 706 struct device_node *np; 707 struct imx_pinctrl *ipctl; 708 struct regmap *gpr; 709 int ret, i; 710 711 if (!info || !info->pins || !info->npins) { 712 dev_err(&pdev->dev, "wrong pinctrl info\n"); 713 return -EINVAL; 714 } 715 716 if (info->gpr_compatible) { 717 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible); 718 if (!IS_ERR(gpr)) 719 regmap_attach_dev(&pdev->dev, gpr, &config); 720 } 721 722 /* Create state holders etc for this driver */ 723 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 724 if (!ipctl) 725 return -ENOMEM; 726 727 if (!(info->flags & IMX_USE_SCU)) { 728 ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins, 729 sizeof(*ipctl->pin_regs), 730 GFP_KERNEL); 731 if (!ipctl->pin_regs) 732 return -ENOMEM; 733 734 for (i = 0; i < info->npins; i++) { 735 ipctl->pin_regs[i].mux_reg = -1; 736 ipctl->pin_regs[i].conf_reg = -1; 737 } 738 739 ipctl->base = devm_platform_ioremap_resource(pdev, 0); 740 if (IS_ERR(ipctl->base)) 741 return PTR_ERR(ipctl->base); 742 743 if (of_property_present(dev_np, "fsl,input-sel")) { 744 np = of_parse_phandle(dev_np, "fsl,input-sel", 0); 745 if (!np) { 746 dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); 747 return -EINVAL; 748 } 749 750 ipctl->input_sel_base = of_iomap(np, 0); 751 of_node_put(np); 752 if (!ipctl->input_sel_base) { 753 dev_err(&pdev->dev, 754 "iomuxc input select base address not found\n"); 755 return -ENOMEM; 756 } 757 } 758 } 759 760 imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc), 761 GFP_KERNEL); 762 if (!imx_pinctrl_desc) 763 return -ENOMEM; 764 765 imx_pinctrl_desc->name = dev_name(&pdev->dev); 766 imx_pinctrl_desc->pins = info->pins; 767 imx_pinctrl_desc->npins = info->npins; 768 imx_pinctrl_desc->pctlops = &imx_pctrl_ops; 769 imx_pinctrl_desc->pmxops = &imx_pmx_ops; 770 imx_pinctrl_desc->confops = &imx_pinconf_ops; 771 imx_pinctrl_desc->owner = THIS_MODULE; 772 773 /* platform specific callback */ 774 imx_pmx_ops.gpio_set_direction = info->gpio_set_direction; 775 776 mutex_init(&ipctl->mutex); 777 778 ipctl->info = info; 779 ipctl->dev = &pdev->dev; 780 platform_set_drvdata(pdev, ipctl); 781 ret = devm_pinctrl_register_and_init(&pdev->dev, 782 imx_pinctrl_desc, ipctl, 783 &ipctl->pctl); 784 if (ret) { 785 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); 786 return ret; 787 } 788 789 ret = imx_pinctrl_probe_dt(pdev, ipctl); 790 if (ret) { 791 dev_err(&pdev->dev, "fail to probe dt properties\n"); 792 return ret; 793 } 794 795 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); 796 797 return pinctrl_enable(ipctl->pctl); 798 } 799 EXPORT_SYMBOL_GPL(imx_pinctrl_probe); 800 801 static int imx_pinctrl_suspend(struct device *dev) 802 { 803 struct imx_pinctrl *ipctl = dev_get_drvdata(dev); 804 805 return pinctrl_force_sleep(ipctl->pctl); 806 } 807 808 static int imx_pinctrl_resume(struct device *dev) 809 { 810 struct imx_pinctrl *ipctl = dev_get_drvdata(dev); 811 812 return pinctrl_force_default(ipctl->pctl); 813 } 814 815 const struct dev_pm_ops imx_pinctrl_pm_ops = { 816 LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend, imx_pinctrl_resume) 817 }; 818 EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops); 819 820 MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>"); 821 MODULE_DESCRIPTION("NXP i.MX common pinctrl driver"); 822 MODULE_LICENSE("GPL v2"); 823