1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Core driver for the imx pin controller 4 // 5 // Copyright (C) 2012 Freescale Semiconductor, Inc. 6 // Copyright (C) 2012 Linaro Ltd. 7 // 8 // Author: Dong Aisheng <dong.aisheng@linaro.org> 9 10 #include <linux/err.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/pinctrl/machine.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/slab.h> 22 #include <linux/regmap.h> 23 24 #include "../core.h" 25 #include "../pinconf.h" 26 #include "../pinmux.h" 27 #include "pinctrl-imx.h" 28 29 /* The bits in CONFIG cell defined in binding doc*/ 30 #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ 31 #define IMX_PAD_SION 0x40000000 /* set SION */ 32 33 static inline const struct group_desc *imx_pinctrl_find_group_by_name( 34 struct pinctrl_dev *pctldev, 35 const char *name) 36 { 37 const struct group_desc *grp = NULL; 38 int i; 39 40 for (i = 0; i < pctldev->num_groups; i++) { 41 grp = pinctrl_generic_get_group(pctldev, i); 42 if (grp && !strcmp(grp->name, name)) 43 break; 44 } 45 46 return grp; 47 } 48 49 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 50 unsigned offset) 51 { 52 seq_printf(s, "%s", dev_name(pctldev->dev)); 53 } 54 55 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, 56 struct device_node *np, 57 struct pinctrl_map **map, unsigned *num_maps) 58 { 59 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 60 const struct imx_pinctrl_soc_info *info = ipctl->info; 61 const struct group_desc *grp; 62 struct pinctrl_map *new_map; 63 struct device_node *parent; 64 struct imx_pin *pin; 65 int map_num = 1; 66 int i, j; 67 68 /* 69 * first find the group of this node and check if we need create 70 * config maps for pins 71 */ 72 grp = imx_pinctrl_find_group_by_name(pctldev, np->name); 73 if (!grp) { 74 dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np); 75 return -EINVAL; 76 } 77 78 if (info->flags & IMX_USE_SCU) { 79 map_num += grp->num_pins; 80 } else { 81 for (i = 0; i < grp->num_pins; i++) { 82 pin = &((struct imx_pin *)(grp->data))[i]; 83 if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) 84 map_num++; 85 } 86 } 87 88 new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map), 89 GFP_KERNEL); 90 if (!new_map) 91 return -ENOMEM; 92 93 *map = new_map; 94 *num_maps = map_num; 95 96 /* create mux map */ 97 parent = of_get_parent(np); 98 if (!parent) { 99 kfree(new_map); 100 return -EINVAL; 101 } 102 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 103 new_map[0].data.mux.function = parent->name; 104 new_map[0].data.mux.group = np->name; 105 of_node_put(parent); 106 107 /* create config map */ 108 new_map++; 109 for (i = j = 0; i < grp->num_pins; i++) { 110 pin = &((struct imx_pin *)(grp->data))[i]; 111 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; 112 new_map[j].data.configs.group_or_pin = 113 pin_get_name(pctldev, pin->pin); 114 115 if (info->flags & IMX_USE_SCU) { 116 /* 117 * For SCU case, we set mux and conf together 118 * in one IPC call 119 */ 120 new_map[j].data.configs.configs = 121 (unsigned long *)&pin->conf.scu; 122 new_map[j].data.configs.num_configs = 2; 123 } else if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) { 124 new_map[j].data.configs.configs = 125 &pin->conf.mmio.config; 126 new_map[j].data.configs.num_configs = 1; 127 } 128 129 j++; 130 } 131 132 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 133 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 134 135 return 0; 136 } 137 138 static void imx_dt_free_map(struct pinctrl_dev *pctldev, 139 struct pinctrl_map *map, unsigned num_maps) 140 { 141 kfree(map); 142 } 143 144 static const struct pinctrl_ops imx_pctrl_ops = { 145 .get_groups_count = pinctrl_generic_get_group_count, 146 .get_group_name = pinctrl_generic_get_group_name, 147 .get_group_pins = pinctrl_generic_get_group_pins, 148 .pin_dbg_show = imx_pin_dbg_show, 149 .dt_node_to_map = imx_dt_node_to_map, 150 .dt_free_map = imx_dt_free_map, 151 }; 152 153 static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl, 154 struct imx_pin *pin) 155 { 156 const struct imx_pinctrl_soc_info *info = ipctl->info; 157 struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; 158 const struct imx_pin_reg *pin_reg; 159 unsigned int pin_id; 160 161 pin_id = pin->pin; 162 pin_reg = &ipctl->pin_regs[pin_id]; 163 164 if (pin_reg->mux_reg == -1) { 165 dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", 166 info->pins[pin_id].name); 167 return 0; 168 } 169 170 if (info->flags & SHARE_MUX_CONF_REG) { 171 u32 reg; 172 173 reg = readl(ipctl->base + pin_reg->mux_reg); 174 reg &= ~info->mux_mask; 175 reg |= (pin_mmio->mux_mode << info->mux_shift); 176 writel(reg, ipctl->base + pin_reg->mux_reg); 177 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 178 pin_reg->mux_reg, reg); 179 } else { 180 writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg); 181 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 182 pin_reg->mux_reg, pin_mmio->mux_mode); 183 } 184 185 /* 186 * If the select input value begins with 0xff, it's a quirky 187 * select input and the value should be interpreted as below. 188 * 31 23 15 7 0 189 * | 0xff | shift | width | select | 190 * It's used to work around the problem that the select 191 * input for some pin is not implemented in the select 192 * input register but in some general purpose register. 193 * We encode the select input value, width and shift of 194 * the bit field into input_val cell of pin function ID 195 * in device tree, and then decode them here for setting 196 * up the select input bits in general purpose register. 197 */ 198 if (pin_mmio->input_val >> 24 == 0xff) { 199 u32 val = pin_mmio->input_val; 200 u8 select = val & 0xff; 201 u8 width = (val >> 8) & 0xff; 202 u8 shift = (val >> 16) & 0xff; 203 u32 mask = ((1 << width) - 1) << shift; 204 /* 205 * The input_reg[i] here is actually some IOMUXC general 206 * purpose register, not regular select input register. 207 */ 208 val = readl(ipctl->base + pin_mmio->input_reg); 209 val &= ~mask; 210 val |= select << shift; 211 writel(val, ipctl->base + pin_mmio->input_reg); 212 } else if (pin_mmio->input_reg) { 213 /* 214 * Regular select input register can never be at offset 215 * 0, and we only print register value for regular case. 216 */ 217 if (ipctl->input_sel_base) 218 writel(pin_mmio->input_val, ipctl->input_sel_base + 219 pin_mmio->input_reg); 220 else 221 writel(pin_mmio->input_val, ipctl->base + 222 pin_mmio->input_reg); 223 dev_dbg(ipctl->dev, 224 "==>select_input: offset 0x%x val 0x%x\n", 225 pin_mmio->input_reg, pin_mmio->input_val); 226 } 227 228 return 0; 229 } 230 231 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 232 unsigned group) 233 { 234 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 235 const struct imx_pinctrl_soc_info *info = ipctl->info; 236 struct function_desc *func; 237 struct group_desc *grp; 238 struct imx_pin *pin; 239 unsigned int npins; 240 int i, err; 241 242 /* 243 * Configure the mux mode for each pin in the group for a specific 244 * function. 245 */ 246 grp = pinctrl_generic_get_group(pctldev, group); 247 if (!grp) 248 return -EINVAL; 249 250 func = pinmux_generic_get_function(pctldev, selector); 251 if (!func) 252 return -EINVAL; 253 254 npins = grp->num_pins; 255 256 dev_dbg(ipctl->dev, "enable function %s group %s\n", 257 func->name, grp->name); 258 259 for (i = 0; i < npins; i++) { 260 /* 261 * For IMX_USE_SCU case, we postpone the mux setting 262 * until config is set as we can set them together 263 * in one IPC call 264 */ 265 pin = &((struct imx_pin *)(grp->data))[i]; 266 if (!(info->flags & IMX_USE_SCU)) { 267 err = imx_pmx_set_one_pin_mmio(ipctl, pin); 268 if (err) 269 return err; 270 } 271 } 272 273 return 0; 274 } 275 276 struct pinmux_ops imx_pmx_ops = { 277 .get_functions_count = pinmux_generic_get_function_count, 278 .get_function_name = pinmux_generic_get_function_name, 279 .get_function_groups = pinmux_generic_get_function_groups, 280 .set_mux = imx_pmx_set, 281 }; 282 283 /* decode generic config into raw register values */ 284 static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl, 285 unsigned long *configs, 286 unsigned int num_configs) 287 { 288 const struct imx_pinctrl_soc_info *info = ipctl->info; 289 const struct imx_cfg_params_decode *decode; 290 enum pin_config_param param; 291 u32 raw_config = 0; 292 u32 param_val; 293 int i, j; 294 295 WARN_ON(num_configs > info->num_decodes); 296 297 for (i = 0; i < num_configs; i++) { 298 param = pinconf_to_config_param(configs[i]); 299 param_val = pinconf_to_config_argument(configs[i]); 300 decode = info->decodes; 301 for (j = 0; j < info->num_decodes; j++) { 302 if (param == decode->param) { 303 if (decode->invert) 304 param_val = !param_val; 305 raw_config |= (param_val << decode->shift) 306 & decode->mask; 307 break; 308 } 309 decode++; 310 } 311 } 312 313 if (info->fixup) 314 info->fixup(configs, num_configs, &raw_config); 315 316 return raw_config; 317 } 318 319 static u32 imx_pinconf_parse_generic_config(struct device_node *np, 320 struct imx_pinctrl *ipctl) 321 { 322 const struct imx_pinctrl_soc_info *info = ipctl->info; 323 struct pinctrl_dev *pctl = ipctl->pctl; 324 unsigned int num_configs; 325 unsigned long *configs; 326 int ret; 327 328 if (!info->generic_pinconf) 329 return 0; 330 331 ret = pinconf_generic_parse_dt_config(np, pctl, &configs, 332 &num_configs); 333 if (ret) 334 return 0; 335 336 return imx_pinconf_decode_generic_config(ipctl, configs, num_configs); 337 } 338 339 static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id, 340 unsigned long *config) 341 { 342 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 343 const struct imx_pinctrl_soc_info *info = ipctl->info; 344 const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; 345 346 if (pin_reg->conf_reg == -1) { 347 dev_err(ipctl->dev, "Pin(%s) does not support config function\n", 348 info->pins[pin_id].name); 349 return -EINVAL; 350 } 351 352 *config = readl(ipctl->base + pin_reg->conf_reg); 353 354 if (info->flags & SHARE_MUX_CONF_REG) 355 *config &= ~info->mux_mask; 356 357 return 0; 358 } 359 360 static int imx_pinconf_get(struct pinctrl_dev *pctldev, 361 unsigned pin_id, unsigned long *config) 362 { 363 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 364 const struct imx_pinctrl_soc_info *info = ipctl->info; 365 366 if (info->flags & IMX_USE_SCU) 367 return imx_pinconf_get_scu(pctldev, pin_id, config); 368 else 369 return imx_pinconf_get_mmio(pctldev, pin_id, config); 370 } 371 372 static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev, 373 unsigned pin_id, unsigned long *configs, 374 unsigned num_configs) 375 { 376 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 377 const struct imx_pinctrl_soc_info *info = ipctl->info; 378 const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; 379 int i; 380 381 if (pin_reg->conf_reg == -1) { 382 dev_err(ipctl->dev, "Pin(%s) does not support config function\n", 383 info->pins[pin_id].name); 384 return -EINVAL; 385 } 386 387 dev_dbg(ipctl->dev, "pinconf set pin %s\n", 388 info->pins[pin_id].name); 389 390 for (i = 0; i < num_configs; i++) { 391 if (info->flags & SHARE_MUX_CONF_REG) { 392 u32 reg; 393 reg = readl(ipctl->base + pin_reg->conf_reg); 394 reg &= info->mux_mask; 395 reg |= configs[i]; 396 writel(reg, ipctl->base + pin_reg->conf_reg); 397 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 398 pin_reg->conf_reg, reg); 399 } else { 400 writel(configs[i], ipctl->base + pin_reg->conf_reg); 401 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", 402 pin_reg->conf_reg, configs[i]); 403 } 404 } /* for each config */ 405 406 return 0; 407 } 408 409 static int imx_pinconf_set(struct pinctrl_dev *pctldev, 410 unsigned pin_id, unsigned long *configs, 411 unsigned num_configs) 412 { 413 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 414 const struct imx_pinctrl_soc_info *info = ipctl->info; 415 416 if (info->flags & IMX_USE_SCU) 417 return imx_pinconf_set_scu(pctldev, pin_id, 418 configs, num_configs); 419 else 420 return imx_pinconf_set_mmio(pctldev, pin_id, 421 configs, num_configs); 422 } 423 424 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 425 struct seq_file *s, unsigned pin_id) 426 { 427 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 428 const struct imx_pinctrl_soc_info *info = ipctl->info; 429 const struct imx_pin_reg *pin_reg; 430 unsigned long config; 431 int ret; 432 433 if (info->flags & IMX_USE_SCU) { 434 ret = imx_pinconf_get_scu(pctldev, pin_id, &config); 435 if (ret) { 436 dev_err(ipctl->dev, "failed to get %s pinconf\n", 437 pin_get_name(pctldev, pin_id)); 438 seq_puts(s, "N/A"); 439 return; 440 } 441 } else { 442 pin_reg = &ipctl->pin_regs[pin_id]; 443 if (!pin_reg || pin_reg->conf_reg == -1) { 444 seq_puts(s, "N/A"); 445 return; 446 } 447 448 config = readl(ipctl->base + pin_reg->conf_reg); 449 } 450 451 seq_printf(s, "0x%lx", config); 452 } 453 454 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 455 struct seq_file *s, unsigned group) 456 { 457 struct group_desc *grp; 458 unsigned long config; 459 const char *name; 460 int i, ret; 461 462 if (group >= pctldev->num_groups) 463 return; 464 465 seq_puts(s, "\n"); 466 grp = pinctrl_generic_get_group(pctldev, group); 467 if (!grp) 468 return; 469 470 for (i = 0; i < grp->num_pins; i++) { 471 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 472 473 name = pin_get_name(pctldev, pin->pin); 474 ret = imx_pinconf_get(pctldev, pin->pin, &config); 475 if (ret) 476 return; 477 seq_printf(s, " %s: 0x%lx\n", name, config); 478 } 479 } 480 481 static const struct pinconf_ops imx_pinconf_ops = { 482 .pin_config_get = imx_pinconf_get, 483 .pin_config_set = imx_pinconf_set, 484 .pin_config_dbg_show = imx_pinconf_dbg_show, 485 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, 486 }; 487 488 /* 489 * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID 490 * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin. 491 * For generic_pinconf case, there's no extra u32 CONFIG. 492 * 493 * PIN_FUNC_ID format: 494 * Default: 495 * <mux_reg conf_reg input_reg mux_mode input_val> 496 * SHARE_MUX_CONF_REG: 497 * <mux_conf_reg input_reg mux_mode input_val> 498 * IMX_USE_SCU: 499 * <pin_id mux_mode> 500 */ 501 #define FSL_PIN_SIZE 24 502 #define FSL_PIN_SHARE_SIZE 20 503 #define FSL_SCU_PIN_SIZE 12 504 505 static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl, 506 unsigned int *pin_id, struct imx_pin *pin, 507 const __be32 **list_p, 508 struct device_node *np) 509 { 510 const struct imx_pinctrl_soc_info *info = ipctl->info; 511 struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; 512 struct imx_pin_reg *pin_reg; 513 const __be32 *list = *list_p; 514 u32 mux_reg, conf_reg; 515 u32 config; 516 517 mux_reg = be32_to_cpu(*list++); 518 519 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) 520 mux_reg = -1; 521 522 if (info->flags & SHARE_MUX_CONF_REG) { 523 conf_reg = mux_reg; 524 } else { 525 conf_reg = be32_to_cpu(*list++); 526 if (!conf_reg) 527 conf_reg = -1; 528 } 529 530 *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; 531 pin_reg = &ipctl->pin_regs[*pin_id]; 532 pin->pin = *pin_id; 533 pin_reg->mux_reg = mux_reg; 534 pin_reg->conf_reg = conf_reg; 535 pin_mmio->input_reg = be32_to_cpu(*list++); 536 pin_mmio->mux_mode = be32_to_cpu(*list++); 537 pin_mmio->input_val = be32_to_cpu(*list++); 538 539 if (info->generic_pinconf) { 540 /* generic pin config decoded */ 541 pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl); 542 } else { 543 /* legacy pin config read from devicetree */ 544 config = be32_to_cpu(*list++); 545 546 /* SION bit is in mux register */ 547 if (config & IMX_PAD_SION) 548 pin_mmio->mux_mode |= IOMUXC_CONFIG_SION; 549 pin_mmio->config = config & ~IMX_PAD_SION; 550 } 551 552 dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name, 553 pin_mmio->mux_mode, pin_mmio->config); 554 } 555 556 static int imx_pinctrl_parse_groups(struct device_node *np, 557 struct group_desc *grp, 558 struct imx_pinctrl *ipctl, 559 u32 index) 560 { 561 const struct imx_pinctrl_soc_info *info = ipctl->info; 562 struct imx_pin *pin; 563 int size, pin_size; 564 const __be32 *list; 565 int i; 566 567 dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np); 568 569 if (info->flags & IMX_USE_SCU) 570 pin_size = FSL_SCU_PIN_SIZE; 571 else if (info->flags & SHARE_MUX_CONF_REG) 572 pin_size = FSL_PIN_SHARE_SIZE; 573 else 574 pin_size = FSL_PIN_SIZE; 575 576 if (info->generic_pinconf) 577 pin_size -= 4; 578 579 /* Initialise group */ 580 grp->name = np->name; 581 582 /* 583 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, 584 * do sanity check and calculate pins number 585 * 586 * First try legacy 'fsl,pins' property, then fall back to the 587 * generic 'pinmux'. 588 * 589 * Note: for generic 'pinmux' case, there's no CONFIG part in 590 * the binding format. 591 */ 592 list = of_get_property(np, "fsl,pins", &size); 593 if (!list) { 594 list = of_get_property(np, "pinmux", &size); 595 if (!list) { 596 dev_err(ipctl->dev, 597 "no fsl,pins and pins property in node %pOF\n", np); 598 return -EINVAL; 599 } 600 } 601 602 /* we do not check return since it's safe node passed down */ 603 if (!size || size % pin_size) { 604 dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np); 605 return -EINVAL; 606 } 607 608 grp->num_pins = size / pin_size; 609 grp->data = devm_kcalloc(ipctl->dev, 610 grp->num_pins, sizeof(struct imx_pin), 611 GFP_KERNEL); 612 grp->pins = devm_kcalloc(ipctl->dev, 613 grp->num_pins, sizeof(unsigned int), 614 GFP_KERNEL); 615 if (!grp->pins || !grp->data) 616 return -ENOMEM; 617 618 for (i = 0; i < grp->num_pins; i++) { 619 pin = &((struct imx_pin *)(grp->data))[i]; 620 if (info->flags & IMX_USE_SCU) 621 imx_pinctrl_parse_pin_scu(ipctl, &grp->pins[i], 622 pin, &list); 623 else 624 imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i], 625 pin, &list, np); 626 } 627 628 return 0; 629 } 630 631 static int imx_pinctrl_parse_functions(struct device_node *np, 632 struct imx_pinctrl *ipctl, 633 u32 index) 634 { 635 struct pinctrl_dev *pctl = ipctl->pctl; 636 struct device_node *child; 637 struct function_desc *func; 638 struct group_desc *grp; 639 u32 i = 0; 640 641 dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np); 642 643 func = pinmux_generic_get_function(pctl, index); 644 if (!func) 645 return -EINVAL; 646 647 /* Initialise function */ 648 func->name = np->name; 649 func->num_group_names = of_get_child_count(np); 650 if (func->num_group_names == 0) { 651 dev_err(ipctl->dev, "no groups defined in %pOF\n", np); 652 return -EINVAL; 653 } 654 func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names, 655 sizeof(char *), GFP_KERNEL); 656 if (!func->group_names) 657 return -ENOMEM; 658 659 for_each_child_of_node(np, child) { 660 func->group_names[i] = child->name; 661 662 grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc), 663 GFP_KERNEL); 664 if (!grp) 665 return -ENOMEM; 666 667 mutex_lock(&ipctl->mutex); 668 radix_tree_insert(&pctl->pin_group_tree, 669 ipctl->group_index++, grp); 670 mutex_unlock(&ipctl->mutex); 671 672 imx_pinctrl_parse_groups(child, grp, ipctl, i++); 673 } 674 675 return 0; 676 } 677 678 /* 679 * Check if the DT contains pins in the direct child nodes. This indicates the 680 * newer DT format to store pins. This function returns true if the first found 681 * fsl,pins property is in a child of np. Otherwise false is returned. 682 */ 683 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) 684 { 685 struct device_node *function_np; 686 struct device_node *pinctrl_np; 687 688 for_each_child_of_node(np, function_np) { 689 if (of_property_read_bool(function_np, "fsl,pins")) 690 return true; 691 692 for_each_child_of_node(function_np, pinctrl_np) { 693 if (of_property_read_bool(pinctrl_np, "fsl,pins")) 694 return false; 695 } 696 } 697 698 return true; 699 } 700 701 static int imx_pinctrl_probe_dt(struct platform_device *pdev, 702 struct imx_pinctrl *ipctl) 703 { 704 struct device_node *np = pdev->dev.of_node; 705 struct device_node *child; 706 struct pinctrl_dev *pctl = ipctl->pctl; 707 u32 nfuncs = 0; 708 u32 i = 0; 709 bool flat_funcs; 710 711 if (!np) 712 return -ENODEV; 713 714 flat_funcs = imx_pinctrl_dt_is_flat_functions(np); 715 if (flat_funcs) { 716 nfuncs = 1; 717 } else { 718 nfuncs = of_get_child_count(np); 719 if (nfuncs == 0) { 720 dev_err(&pdev->dev, "no functions defined\n"); 721 return -EINVAL; 722 } 723 } 724 725 for (i = 0; i < nfuncs; i++) { 726 struct function_desc *function; 727 728 function = devm_kzalloc(&pdev->dev, sizeof(*function), 729 GFP_KERNEL); 730 if (!function) 731 return -ENOMEM; 732 733 mutex_lock(&ipctl->mutex); 734 radix_tree_insert(&pctl->pin_function_tree, i, function); 735 mutex_unlock(&ipctl->mutex); 736 } 737 pctl->num_functions = nfuncs; 738 739 ipctl->group_index = 0; 740 if (flat_funcs) { 741 pctl->num_groups = of_get_child_count(np); 742 } else { 743 pctl->num_groups = 0; 744 for_each_child_of_node(np, child) 745 pctl->num_groups += of_get_child_count(child); 746 } 747 748 if (flat_funcs) { 749 imx_pinctrl_parse_functions(np, ipctl, 0); 750 } else { 751 i = 0; 752 for_each_child_of_node(np, child) 753 imx_pinctrl_parse_functions(child, ipctl, i++); 754 } 755 756 return 0; 757 } 758 759 /* 760 * imx_free_resources() - free memory used by this driver 761 * @info: info driver instance 762 */ 763 static void imx_free_resources(struct imx_pinctrl *ipctl) 764 { 765 if (ipctl->pctl) 766 pinctrl_unregister(ipctl->pctl); 767 } 768 769 int imx_pinctrl_probe(struct platform_device *pdev, 770 const struct imx_pinctrl_soc_info *info) 771 { 772 struct regmap_config config = { .name = "gpr" }; 773 struct device_node *dev_np = pdev->dev.of_node; 774 struct pinctrl_desc *imx_pinctrl_desc; 775 struct device_node *np; 776 struct imx_pinctrl *ipctl; 777 struct resource *res; 778 struct regmap *gpr; 779 int ret, i; 780 781 if (!info || !info->pins || !info->npins) { 782 dev_err(&pdev->dev, "wrong pinctrl info\n"); 783 return -EINVAL; 784 } 785 786 if (info->gpr_compatible) { 787 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible); 788 if (!IS_ERR(gpr)) 789 regmap_attach_dev(&pdev->dev, gpr, &config); 790 } 791 792 /* Create state holders etc for this driver */ 793 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 794 if (!ipctl) 795 return -ENOMEM; 796 797 if (!(info->flags & IMX_USE_SCU)) { 798 ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins, 799 sizeof(*ipctl->pin_regs), 800 GFP_KERNEL); 801 if (!ipctl->pin_regs) 802 return -ENOMEM; 803 804 for (i = 0; i < info->npins; i++) { 805 ipctl->pin_regs[i].mux_reg = -1; 806 ipctl->pin_regs[i].conf_reg = -1; 807 } 808 809 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 810 ipctl->base = devm_ioremap_resource(&pdev->dev, res); 811 if (IS_ERR(ipctl->base)) 812 return PTR_ERR(ipctl->base); 813 814 if (of_property_read_bool(dev_np, "fsl,input-sel")) { 815 np = of_parse_phandle(dev_np, "fsl,input-sel", 0); 816 if (!np) { 817 dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); 818 return -EINVAL; 819 } 820 821 ipctl->input_sel_base = of_iomap(np, 0); 822 of_node_put(np); 823 if (!ipctl->input_sel_base) { 824 dev_err(&pdev->dev, 825 "iomuxc input select base address not found\n"); 826 return -ENOMEM; 827 } 828 } 829 } 830 831 imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc), 832 GFP_KERNEL); 833 if (!imx_pinctrl_desc) 834 return -ENOMEM; 835 836 imx_pinctrl_desc->name = dev_name(&pdev->dev); 837 imx_pinctrl_desc->pins = info->pins; 838 imx_pinctrl_desc->npins = info->npins; 839 imx_pinctrl_desc->pctlops = &imx_pctrl_ops; 840 imx_pinctrl_desc->pmxops = &imx_pmx_ops; 841 imx_pinctrl_desc->confops = &imx_pinconf_ops; 842 imx_pinctrl_desc->owner = THIS_MODULE; 843 844 /* for generic pinconf */ 845 imx_pinctrl_desc->custom_params = info->custom_params; 846 imx_pinctrl_desc->num_custom_params = info->num_custom_params; 847 848 /* platform specific callback */ 849 imx_pmx_ops.gpio_set_direction = info->gpio_set_direction; 850 851 mutex_init(&ipctl->mutex); 852 853 ipctl->info = info; 854 ipctl->dev = &pdev->dev; 855 platform_set_drvdata(pdev, ipctl); 856 ret = devm_pinctrl_register_and_init(&pdev->dev, 857 imx_pinctrl_desc, ipctl, 858 &ipctl->pctl); 859 if (ret) { 860 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); 861 goto free; 862 } 863 864 ret = imx_pinctrl_probe_dt(pdev, ipctl); 865 if (ret) { 866 dev_err(&pdev->dev, "fail to probe dt properties\n"); 867 goto free; 868 } 869 870 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); 871 872 return pinctrl_enable(ipctl->pctl); 873 874 free: 875 imx_free_resources(ipctl); 876 877 return ret; 878 } 879