1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2014-2017 Broadcom 3 4 /* 5 * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that 6 * supports the chipCommonA GPIO controller. Basic PINCONF such as bias, 7 * pull up/down, slew and drive strength are also supported in this driver. 8 * 9 * Pins from the chipCommonA GPIO can be individually muxed to GPIO function, 10 * through the interaction with the NSP IOMUX controller. 11 */ 12 13 #include <linux/gpio/driver.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/ioport.h> 17 #include <linux/kernel.h> 18 #include <linux/of.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/platform_device.h> 23 #include <linux/slab.h> 24 #include <linux/string_choices.h> 25 26 #include "../pinctrl-utils.h" 27 28 #define NSP_CHIP_A_INT_STATUS 0x00 29 #define NSP_CHIP_A_INT_MASK 0x04 30 #define NSP_GPIO_DATA_IN 0x40 31 #define NSP_GPIO_DATA_OUT 0x44 32 #define NSP_GPIO_OUT_EN 0x48 33 #define NSP_GPIO_INT_POLARITY 0x50 34 #define NSP_GPIO_INT_MASK 0x54 35 #define NSP_GPIO_EVENT 0x58 36 #define NSP_GPIO_EVENT_INT_MASK 0x5c 37 #define NSP_GPIO_EVENT_INT_POLARITY 0x64 38 #define NSP_CHIP_A_GPIO_INT_BIT 0x01 39 40 /* I/O parameters offset for chipcommon A GPIO */ 41 #define NSP_GPIO_DRV_CTRL 0x00 42 #define NSP_GPIO_HYSTERESIS_EN 0x10 43 #define NSP_GPIO_SLEW_RATE_EN 0x14 44 #define NSP_PULL_UP_EN 0x18 45 #define NSP_PULL_DOWN_EN 0x1c 46 #define GPIO_DRV_STRENGTH_BITS 0x03 47 48 /* 49 * nsp GPIO core 50 * 51 * @dev: pointer to device 52 * @base: I/O register base for nsp GPIO controller 53 * @io_ctrl: I/O register base for PINCONF support outside the GPIO block 54 * @gc: GPIO chip 55 * @pctl: pointer to pinctrl_dev 56 * @pctldesc: pinctrl descriptor 57 * @lock: lock to protect access to I/O registers 58 */ 59 struct nsp_gpio { 60 struct device *dev; 61 void __iomem *base; 62 void __iomem *io_ctrl; 63 struct gpio_chip gc; 64 struct pinctrl_dev *pctl; 65 struct pinctrl_desc pctldesc; 66 raw_spinlock_t lock; 67 }; 68 69 enum base_type { 70 REG, 71 IO_CTRL 72 }; 73 74 /* 75 * Mapping from PINCONF pins to GPIO pins is 1-to-1 76 */ 77 static inline unsigned nsp_pin_to_gpio(unsigned pin) 78 { 79 return pin; 80 } 81 82 /* 83 * nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a 84 * nsp GPIO register 85 * 86 * @nsp_gpio: nsp GPIO device 87 * @base_type: reg base to modify 88 * @reg: register offset 89 * @gpio: GPIO pin 90 * @set: set or clear 91 */ 92 static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address, 93 unsigned int reg, unsigned gpio, bool set) 94 { 95 u32 val; 96 void __iomem *base_address; 97 98 if (address == IO_CTRL) 99 base_address = chip->io_ctrl; 100 else 101 base_address = chip->base; 102 103 val = readl(base_address + reg); 104 if (set) 105 val |= BIT(gpio); 106 else 107 val &= ~BIT(gpio); 108 109 writel(val, base_address + reg); 110 } 111 112 /* 113 * nsp_get_bit - get one bit (corresponding to the GPIO pin) in a 114 * nsp GPIO register 115 */ 116 static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address, 117 unsigned int reg, unsigned gpio) 118 { 119 if (address == IO_CTRL) 120 return !!(readl(chip->io_ctrl + reg) & BIT(gpio)); 121 else 122 return !!(readl(chip->base + reg) & BIT(gpio)); 123 } 124 125 static irqreturn_t nsp_gpio_irq_handler(int irq, void *data) 126 { 127 struct gpio_chip *gc = (struct gpio_chip *)data; 128 struct nsp_gpio *chip = gpiochip_get_data(gc); 129 int bit; 130 unsigned long int_bits = 0; 131 u32 int_status; 132 133 /* go through the entire GPIOs and handle all interrupts */ 134 int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS); 135 if (int_status & NSP_CHIP_A_GPIO_INT_BIT) { 136 unsigned int event, level; 137 138 /* Get level and edge interrupts */ 139 event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) & 140 readl(chip->base + NSP_GPIO_EVENT); 141 level = readl(chip->base + NSP_GPIO_DATA_IN) ^ 142 readl(chip->base + NSP_GPIO_INT_POLARITY); 143 level &= readl(chip->base + NSP_GPIO_INT_MASK); 144 int_bits = level | event; 145 146 for_each_set_bit(bit, &int_bits, gc->ngpio) 147 generic_handle_domain_irq(gc->irq.domain, bit); 148 } 149 150 return int_bits ? IRQ_HANDLED : IRQ_NONE; 151 } 152 153 static void nsp_gpio_irq_ack(struct irq_data *d) 154 { 155 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 156 struct nsp_gpio *chip = gpiochip_get_data(gc); 157 unsigned gpio = d->hwirq; 158 u32 val = BIT(gpio); 159 u32 trigger_type; 160 161 trigger_type = irq_get_trigger_type(d->irq); 162 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 163 writel(val, chip->base + NSP_GPIO_EVENT); 164 } 165 166 /* 167 * nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt 168 * 169 * @d: IRQ chip data 170 * @unmask: mask/unmask GPIO interrupt 171 */ 172 static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask) 173 { 174 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 175 struct nsp_gpio *chip = gpiochip_get_data(gc); 176 unsigned gpio = d->hwirq; 177 u32 trigger_type; 178 179 trigger_type = irq_get_trigger_type(d->irq); 180 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 181 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask); 182 else 183 nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask); 184 } 185 186 static void nsp_gpio_irq_mask(struct irq_data *d) 187 { 188 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 189 struct nsp_gpio *chip = gpiochip_get_data(gc); 190 unsigned long flags; 191 192 raw_spin_lock_irqsave(&chip->lock, flags); 193 nsp_gpio_irq_set_mask(d, false); 194 raw_spin_unlock_irqrestore(&chip->lock, flags); 195 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 196 } 197 198 static void nsp_gpio_irq_unmask(struct irq_data *d) 199 { 200 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 201 struct nsp_gpio *chip = gpiochip_get_data(gc); 202 unsigned long flags; 203 204 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 205 raw_spin_lock_irqsave(&chip->lock, flags); 206 nsp_gpio_irq_set_mask(d, true); 207 raw_spin_unlock_irqrestore(&chip->lock, flags); 208 } 209 210 static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type) 211 { 212 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 213 struct nsp_gpio *chip = gpiochip_get_data(gc); 214 unsigned gpio = d->hwirq; 215 bool level_low; 216 bool falling; 217 unsigned long flags; 218 219 raw_spin_lock_irqsave(&chip->lock, flags); 220 falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio); 221 level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio); 222 223 switch (type & IRQ_TYPE_SENSE_MASK) { 224 case IRQ_TYPE_EDGE_RISING: 225 falling = false; 226 break; 227 228 case IRQ_TYPE_EDGE_FALLING: 229 falling = true; 230 break; 231 232 case IRQ_TYPE_LEVEL_HIGH: 233 level_low = false; 234 break; 235 236 case IRQ_TYPE_LEVEL_LOW: 237 level_low = true; 238 break; 239 240 default: 241 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n", 242 type); 243 raw_spin_unlock_irqrestore(&chip->lock, flags); 244 return -EINVAL; 245 } 246 247 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling); 248 nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low); 249 250 if (type & IRQ_TYPE_EDGE_BOTH) 251 irq_set_handler_locked(d, handle_edge_irq); 252 else 253 irq_set_handler_locked(d, handle_level_irq); 254 255 raw_spin_unlock_irqrestore(&chip->lock, flags); 256 257 dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio, 258 str_true_false(level_low), str_true_false(falling)); 259 return 0; 260 } 261 262 static const struct irq_chip nsp_gpio_irq_chip = { 263 .name = "gpio-a", 264 .irq_ack = nsp_gpio_irq_ack, 265 .irq_mask = nsp_gpio_irq_mask, 266 .irq_unmask = nsp_gpio_irq_unmask, 267 .irq_set_type = nsp_gpio_irq_set_type, 268 .flags = IRQCHIP_IMMUTABLE, 269 GPIOCHIP_IRQ_RESOURCE_HELPERS, 270 }; 271 272 static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) 273 { 274 struct nsp_gpio *chip = gpiochip_get_data(gc); 275 unsigned long flags; 276 277 raw_spin_lock_irqsave(&chip->lock, flags); 278 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false); 279 raw_spin_unlock_irqrestore(&chip->lock, flags); 280 281 dev_dbg(chip->dev, "gpio:%u set input\n", gpio); 282 return 0; 283 } 284 285 static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, 286 int val) 287 { 288 struct nsp_gpio *chip = gpiochip_get_data(gc); 289 unsigned long flags; 290 291 raw_spin_lock_irqsave(&chip->lock, flags); 292 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true); 293 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val)); 294 raw_spin_unlock_irqrestore(&chip->lock, flags); 295 296 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); 297 return 0; 298 } 299 300 static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio) 301 { 302 struct nsp_gpio *chip = gpiochip_get_data(gc); 303 unsigned long flags; 304 int val; 305 306 raw_spin_lock_irqsave(&chip->lock, flags); 307 val = nsp_get_bit(chip, REG, NSP_GPIO_OUT_EN, gpio); 308 raw_spin_unlock_irqrestore(&chip->lock, flags); 309 310 return !val; 311 } 312 313 static int nsp_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 314 { 315 struct nsp_gpio *chip = gpiochip_get_data(gc); 316 unsigned long flags; 317 318 raw_spin_lock_irqsave(&chip->lock, flags); 319 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val)); 320 raw_spin_unlock_irqrestore(&chip->lock, flags); 321 322 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); 323 324 return 0; 325 } 326 327 static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio) 328 { 329 struct nsp_gpio *chip = gpiochip_get_data(gc); 330 331 return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio)); 332 } 333 334 static int nsp_get_groups_count(struct pinctrl_dev *pctldev) 335 { 336 return 1; 337 } 338 339 /* 340 * Only one group: "gpio_grp", since this local pinctrl device only performs 341 * GPIO specific PINCONF configurations 342 */ 343 static const char *nsp_get_group_name(struct pinctrl_dev *pctldev, 344 unsigned selector) 345 { 346 return "gpio_grp"; 347 } 348 349 static const struct pinctrl_ops nsp_pctrl_ops = { 350 .get_groups_count = nsp_get_groups_count, 351 .get_group_name = nsp_get_group_name, 352 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 353 .dt_free_map = pinctrl_utils_free_map, 354 }; 355 356 static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u32 slew) 357 { 358 if (slew) 359 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true); 360 else 361 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false); 362 363 return 0; 364 } 365 366 static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio, 367 bool pull_up, bool pull_down) 368 { 369 unsigned long flags; 370 371 raw_spin_lock_irqsave(&chip->lock, flags); 372 nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down); 373 nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up); 374 raw_spin_unlock_irqrestore(&chip->lock, flags); 375 376 dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n", 377 gpio, pull_up, pull_down); 378 return 0; 379 } 380 381 static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio, 382 bool *pull_up, bool *pull_down) 383 { 384 unsigned long flags; 385 386 raw_spin_lock_irqsave(&chip->lock, flags); 387 *pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio); 388 *pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio); 389 raw_spin_unlock_irqrestore(&chip->lock, flags); 390 } 391 392 static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio, 393 u32 strength) 394 { 395 u32 offset, shift, i; 396 u32 val; 397 unsigned long flags; 398 399 /* make sure drive strength is supported */ 400 if (strength < 2 || strength > 16 || (strength % 2)) 401 return -ENOTSUPP; 402 403 shift = gpio; 404 offset = NSP_GPIO_DRV_CTRL; 405 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, 406 strength); 407 raw_spin_lock_irqsave(&chip->lock, flags); 408 strength = (strength / 2) - 1; 409 for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) { 410 val = readl(chip->io_ctrl + offset); 411 val &= ~BIT(shift); 412 val |= ((strength >> (i-1)) & 0x1) << shift; 413 writel(val, chip->io_ctrl + offset); 414 offset += 4; 415 } 416 raw_spin_unlock_irqrestore(&chip->lock, flags); 417 418 return 0; 419 } 420 421 static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio, 422 u16 *strength) 423 { 424 unsigned int offset, shift; 425 u32 val; 426 unsigned long flags; 427 int i; 428 429 offset = NSP_GPIO_DRV_CTRL; 430 shift = gpio; 431 432 raw_spin_lock_irqsave(&chip->lock, flags); 433 *strength = 0; 434 for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) { 435 val = readl(chip->io_ctrl + offset) & BIT(shift); 436 val >>= shift; 437 *strength += (val << i); 438 offset += 4; 439 } 440 441 /* convert to mA */ 442 *strength = (*strength + 1) * 2; 443 raw_spin_unlock_irqrestore(&chip->lock, flags); 444 445 return 0; 446 } 447 448 static int nsp_pin_config_group_get(struct pinctrl_dev *pctldev, 449 unsigned selector, 450 unsigned long *config) 451 { 452 return 0; 453 } 454 455 static int nsp_pin_config_group_set(struct pinctrl_dev *pctldev, 456 unsigned selector, 457 unsigned long *configs, unsigned num_configs) 458 { 459 return 0; 460 } 461 462 static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 463 unsigned long *config) 464 { 465 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev); 466 enum pin_config_param param = pinconf_to_config_param(*config); 467 unsigned int gpio; 468 u16 arg = 0; 469 bool pull_up, pull_down; 470 int ret; 471 472 gpio = nsp_pin_to_gpio(pin); 473 switch (param) { 474 case PIN_CONFIG_BIAS_DISABLE: 475 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down); 476 if ((pull_up == false) && (pull_down == false)) 477 return 0; 478 else 479 return -EINVAL; 480 481 case PIN_CONFIG_BIAS_PULL_UP: 482 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down); 483 if (pull_up) 484 return 0; 485 else 486 return -EINVAL; 487 488 case PIN_CONFIG_BIAS_PULL_DOWN: 489 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down); 490 if (pull_down) 491 return 0; 492 else 493 return -EINVAL; 494 495 case PIN_CONFIG_DRIVE_STRENGTH: 496 ret = nsp_gpio_get_strength(chip, gpio, &arg); 497 if (ret) 498 return ret; 499 *config = pinconf_to_config_packed(param, arg); 500 return 0; 501 502 default: 503 return -ENOTSUPP; 504 } 505 } 506 507 static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 508 unsigned long *configs, unsigned num_configs) 509 { 510 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev); 511 enum pin_config_param param; 512 u32 arg; 513 unsigned int i, gpio; 514 int ret = -ENOTSUPP; 515 516 gpio = nsp_pin_to_gpio(pin); 517 for (i = 0; i < num_configs; i++) { 518 param = pinconf_to_config_param(configs[i]); 519 arg = pinconf_to_config_argument(configs[i]); 520 521 switch (param) { 522 case PIN_CONFIG_BIAS_DISABLE: 523 ret = nsp_gpio_set_pull(chip, gpio, false, false); 524 if (ret < 0) 525 goto out; 526 break; 527 528 case PIN_CONFIG_BIAS_PULL_UP: 529 ret = nsp_gpio_set_pull(chip, gpio, true, false); 530 if (ret < 0) 531 goto out; 532 break; 533 534 case PIN_CONFIG_BIAS_PULL_DOWN: 535 ret = nsp_gpio_set_pull(chip, gpio, false, true); 536 if (ret < 0) 537 goto out; 538 break; 539 540 case PIN_CONFIG_DRIVE_STRENGTH: 541 ret = nsp_gpio_set_strength(chip, gpio, arg); 542 if (ret < 0) 543 goto out; 544 break; 545 546 case PIN_CONFIG_SLEW_RATE: 547 ret = nsp_gpio_set_slew(chip, gpio, arg); 548 if (ret < 0) 549 goto out; 550 break; 551 552 default: 553 dev_err(chip->dev, "invalid configuration\n"); 554 return -ENOTSUPP; 555 } 556 } 557 558 out: 559 return ret; 560 } 561 562 static const struct pinconf_ops nsp_pconf_ops = { 563 .is_generic = true, 564 .pin_config_get = nsp_pin_config_get, 565 .pin_config_set = nsp_pin_config_set, 566 .pin_config_group_get = nsp_pin_config_group_get, 567 .pin_config_group_set = nsp_pin_config_group_set, 568 }; 569 570 /* 571 * NSP GPIO controller supports some PINCONF related configurations such as 572 * pull up, pull down, slew and drive strength, when the pin is configured 573 * to GPIO. 574 * 575 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the 576 * local GPIO pins 577 */ 578 static int nsp_gpio_register_pinconf(struct nsp_gpio *chip) 579 { 580 struct pinctrl_desc *pctldesc = &chip->pctldesc; 581 struct pinctrl_pin_desc *pins; 582 struct gpio_chip *gc = &chip->gc; 583 int i; 584 585 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL); 586 if (!pins) 587 return -ENOMEM; 588 for (i = 0; i < gc->ngpio; i++) { 589 pins[i].number = i; 590 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL, 591 "gpio-%d", i); 592 if (!pins[i].name) 593 return -ENOMEM; 594 } 595 pctldesc->name = dev_name(chip->dev); 596 pctldesc->pctlops = &nsp_pctrl_ops; 597 pctldesc->pins = pins; 598 pctldesc->npins = gc->ngpio; 599 pctldesc->confops = &nsp_pconf_ops; 600 601 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip); 602 if (IS_ERR(chip->pctl)) { 603 dev_err(chip->dev, "unable to register pinctrl device\n"); 604 return PTR_ERR(chip->pctl); 605 } 606 607 return 0; 608 } 609 610 static const struct of_device_id nsp_gpio_of_match[] = { 611 {.compatible = "brcm,nsp-gpio-a",}, 612 {} 613 }; 614 615 static int nsp_gpio_probe(struct platform_device *pdev) 616 { 617 struct device *dev = &pdev->dev; 618 struct nsp_gpio *chip; 619 struct gpio_chip *gc; 620 u32 val; 621 int irq, ret; 622 623 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) { 624 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 625 return -ENODEV; 626 } 627 628 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 629 if (!chip) 630 return -ENOMEM; 631 632 chip->dev = dev; 633 platform_set_drvdata(pdev, chip); 634 635 chip->base = devm_platform_ioremap_resource(pdev, 0); 636 if (IS_ERR(chip->base)) { 637 dev_err(dev, "unable to map I/O memory\n"); 638 return PTR_ERR(chip->base); 639 } 640 641 chip->io_ctrl = devm_platform_ioremap_resource(pdev, 1); 642 if (IS_ERR(chip->io_ctrl)) { 643 dev_err(dev, "unable to map I/O memory\n"); 644 return PTR_ERR(chip->io_ctrl); 645 } 646 647 raw_spin_lock_init(&chip->lock); 648 gc = &chip->gc; 649 gc->base = -1; 650 gc->can_sleep = false; 651 gc->ngpio = val; 652 gc->label = dev_name(dev); 653 gc->parent = dev; 654 gc->request = gpiochip_generic_request; 655 gc->free = gpiochip_generic_free; 656 gc->direction_input = nsp_gpio_direction_input; 657 gc->direction_output = nsp_gpio_direction_output; 658 gc->get_direction = nsp_gpio_get_direction; 659 gc->set = nsp_gpio_set; 660 gc->get = nsp_gpio_get; 661 662 /* optional GPIO interrupt support */ 663 irq = platform_get_irq(pdev, 0); 664 if (irq > 0) { 665 struct gpio_irq_chip *girq; 666 667 val = readl(chip->base + NSP_CHIP_A_INT_MASK); 668 val = val | NSP_CHIP_A_GPIO_INT_BIT; 669 writel(val, (chip->base + NSP_CHIP_A_INT_MASK)); 670 671 /* Install ISR for this GPIO controller. */ 672 ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler, 673 IRQF_SHARED, "gpio-a", &chip->gc); 674 if (ret) { 675 dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n", 676 irq, ret); 677 return ret; 678 } 679 680 girq = &chip->gc.irq; 681 gpio_irq_chip_set_chip(girq, &nsp_gpio_irq_chip); 682 /* This will let us handle the parent IRQ in the driver */ 683 girq->parent_handler = NULL; 684 girq->num_parents = 0; 685 girq->parents = NULL; 686 girq->default_type = IRQ_TYPE_NONE; 687 girq->handler = handle_bad_irq; 688 } 689 690 ret = devm_gpiochip_add_data(dev, gc, chip); 691 if (ret < 0) 692 return dev_err_probe(dev, ret, "unable to add GPIO chip\n"); 693 694 ret = nsp_gpio_register_pinconf(chip); 695 if (ret) { 696 dev_err(dev, "unable to register pinconf\n"); 697 return ret; 698 } 699 700 return 0; 701 } 702 703 static struct platform_driver nsp_gpio_driver = { 704 .driver = { 705 .name = "nsp-gpio-a", 706 .of_match_table = nsp_gpio_of_match, 707 }, 708 .probe = nsp_gpio_probe, 709 }; 710 711 static int __init nsp_gpio_init(void) 712 { 713 return platform_driver_register(&nsp_gpio_driver); 714 } 715 arch_initcall_sync(nsp_gpio_init); 716