xref: /linux/drivers/pinctrl/bcm/pinctrl-bcm2835.c (revision f3956ebb3bf06ab2266ad5ee2214aed46405810c) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
4  *
5  * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
6  *
7  * This driver is inspired by:
8  * pinctrl-nomadik.c, please see original file for copyright information
9  * pinctrl-tegra.c, please see original file for copyright information
10  */
11 
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_address.h>
24 #include <linux/of.h>
25 #include <linux/of_irq.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/platform_device.h>
33 #include <linux/seq_file.h>
34 #include <linux/slab.h>
35 #include <linux/spinlock.h>
36 #include <linux/types.h>
37 #include <dt-bindings/pinctrl/bcm2835.h>
38 
39 #define MODULE_NAME "pinctrl-bcm2835"
40 #define BCM2835_NUM_GPIOS 54
41 #define BCM2711_NUM_GPIOS 58
42 #define BCM2835_NUM_BANKS 2
43 #define BCM2835_NUM_IRQS  3
44 
45 /* GPIO register offsets */
46 #define GPFSEL0		0x0	/* Function Select */
47 #define GPSET0		0x1c	/* Pin Output Set */
48 #define GPCLR0		0x28	/* Pin Output Clear */
49 #define GPLEV0		0x34	/* Pin Level */
50 #define GPEDS0		0x40	/* Pin Event Detect Status */
51 #define GPREN0		0x4c	/* Pin Rising Edge Detect Enable */
52 #define GPFEN0		0x58	/* Pin Falling Edge Detect Enable */
53 #define GPHEN0		0x64	/* Pin High Detect Enable */
54 #define GPLEN0		0x70	/* Pin Low Detect Enable */
55 #define GPAREN0		0x7c	/* Pin Async Rising Edge Detect */
56 #define GPAFEN0		0x88	/* Pin Async Falling Edge Detect */
57 #define GPPUD		0x94	/* Pin Pull-up/down Enable */
58 #define GPPUDCLK0	0x98	/* Pin Pull-up/down Enable Clock */
59 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
60 
61 #define FSEL_REG(p)		(GPFSEL0 + (((p) / 10) * 4))
62 #define FSEL_SHIFT(p)		(((p) % 10) * 3)
63 #define GPIO_REG_OFFSET(p)	((p) / 32)
64 #define GPIO_REG_SHIFT(p)	((p) % 32)
65 
66 #define PUD_2711_MASK		0x3
67 #define PUD_2711_REG_OFFSET(p)	((p) / 16)
68 #define PUD_2711_REG_SHIFT(p)	(((p) % 16) * 2)
69 
70 /* argument: bcm2835_pinconf_pull */
71 #define BCM2835_PINCONF_PARAM_PULL	(PIN_CONFIG_END + 1)
72 
73 #define BCM2711_PULL_NONE	0x0
74 #define BCM2711_PULL_UP		0x1
75 #define BCM2711_PULL_DOWN	0x2
76 
77 struct bcm2835_pinctrl {
78 	struct device *dev;
79 	void __iomem *base;
80 	int *wake_irq;
81 
82 	/* note: locking assumes each bank will have its own unsigned long */
83 	unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
84 	unsigned int irq_type[BCM2711_NUM_GPIOS];
85 
86 	struct pinctrl_dev *pctl_dev;
87 	struct gpio_chip gpio_chip;
88 	struct pinctrl_desc pctl_desc;
89 	struct pinctrl_gpio_range gpio_range;
90 
91 	raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
92 };
93 
94 /* pins are just named GPIO0..GPIO53 */
95 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
96 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
97 	BCM2835_GPIO_PIN(0),
98 	BCM2835_GPIO_PIN(1),
99 	BCM2835_GPIO_PIN(2),
100 	BCM2835_GPIO_PIN(3),
101 	BCM2835_GPIO_PIN(4),
102 	BCM2835_GPIO_PIN(5),
103 	BCM2835_GPIO_PIN(6),
104 	BCM2835_GPIO_PIN(7),
105 	BCM2835_GPIO_PIN(8),
106 	BCM2835_GPIO_PIN(9),
107 	BCM2835_GPIO_PIN(10),
108 	BCM2835_GPIO_PIN(11),
109 	BCM2835_GPIO_PIN(12),
110 	BCM2835_GPIO_PIN(13),
111 	BCM2835_GPIO_PIN(14),
112 	BCM2835_GPIO_PIN(15),
113 	BCM2835_GPIO_PIN(16),
114 	BCM2835_GPIO_PIN(17),
115 	BCM2835_GPIO_PIN(18),
116 	BCM2835_GPIO_PIN(19),
117 	BCM2835_GPIO_PIN(20),
118 	BCM2835_GPIO_PIN(21),
119 	BCM2835_GPIO_PIN(22),
120 	BCM2835_GPIO_PIN(23),
121 	BCM2835_GPIO_PIN(24),
122 	BCM2835_GPIO_PIN(25),
123 	BCM2835_GPIO_PIN(26),
124 	BCM2835_GPIO_PIN(27),
125 	BCM2835_GPIO_PIN(28),
126 	BCM2835_GPIO_PIN(29),
127 	BCM2835_GPIO_PIN(30),
128 	BCM2835_GPIO_PIN(31),
129 	BCM2835_GPIO_PIN(32),
130 	BCM2835_GPIO_PIN(33),
131 	BCM2835_GPIO_PIN(34),
132 	BCM2835_GPIO_PIN(35),
133 	BCM2835_GPIO_PIN(36),
134 	BCM2835_GPIO_PIN(37),
135 	BCM2835_GPIO_PIN(38),
136 	BCM2835_GPIO_PIN(39),
137 	BCM2835_GPIO_PIN(40),
138 	BCM2835_GPIO_PIN(41),
139 	BCM2835_GPIO_PIN(42),
140 	BCM2835_GPIO_PIN(43),
141 	BCM2835_GPIO_PIN(44),
142 	BCM2835_GPIO_PIN(45),
143 	BCM2835_GPIO_PIN(46),
144 	BCM2835_GPIO_PIN(47),
145 	BCM2835_GPIO_PIN(48),
146 	BCM2835_GPIO_PIN(49),
147 	BCM2835_GPIO_PIN(50),
148 	BCM2835_GPIO_PIN(51),
149 	BCM2835_GPIO_PIN(52),
150 	BCM2835_GPIO_PIN(53),
151 	BCM2835_GPIO_PIN(54),
152 	BCM2835_GPIO_PIN(55),
153 	BCM2835_GPIO_PIN(56),
154 	BCM2835_GPIO_PIN(57),
155 };
156 
157 /* one pin per group */
158 static const char * const bcm2835_gpio_groups[] = {
159 	"gpio0",
160 	"gpio1",
161 	"gpio2",
162 	"gpio3",
163 	"gpio4",
164 	"gpio5",
165 	"gpio6",
166 	"gpio7",
167 	"gpio8",
168 	"gpio9",
169 	"gpio10",
170 	"gpio11",
171 	"gpio12",
172 	"gpio13",
173 	"gpio14",
174 	"gpio15",
175 	"gpio16",
176 	"gpio17",
177 	"gpio18",
178 	"gpio19",
179 	"gpio20",
180 	"gpio21",
181 	"gpio22",
182 	"gpio23",
183 	"gpio24",
184 	"gpio25",
185 	"gpio26",
186 	"gpio27",
187 	"gpio28",
188 	"gpio29",
189 	"gpio30",
190 	"gpio31",
191 	"gpio32",
192 	"gpio33",
193 	"gpio34",
194 	"gpio35",
195 	"gpio36",
196 	"gpio37",
197 	"gpio38",
198 	"gpio39",
199 	"gpio40",
200 	"gpio41",
201 	"gpio42",
202 	"gpio43",
203 	"gpio44",
204 	"gpio45",
205 	"gpio46",
206 	"gpio47",
207 	"gpio48",
208 	"gpio49",
209 	"gpio50",
210 	"gpio51",
211 	"gpio52",
212 	"gpio53",
213 	"gpio54",
214 	"gpio55",
215 	"gpio56",
216 	"gpio57",
217 };
218 
219 enum bcm2835_fsel {
220 	BCM2835_FSEL_COUNT = 8,
221 	BCM2835_FSEL_MASK = 0x7,
222 };
223 
224 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
225 	[BCM2835_FSEL_GPIO_IN] = "gpio_in",
226 	[BCM2835_FSEL_GPIO_OUT] = "gpio_out",
227 	[BCM2835_FSEL_ALT0] = "alt0",
228 	[BCM2835_FSEL_ALT1] = "alt1",
229 	[BCM2835_FSEL_ALT2] = "alt2",
230 	[BCM2835_FSEL_ALT3] = "alt3",
231 	[BCM2835_FSEL_ALT4] = "alt4",
232 	[BCM2835_FSEL_ALT5] = "alt5",
233 };
234 
235 static const char * const irq_type_names[] = {
236 	[IRQ_TYPE_NONE] = "none",
237 	[IRQ_TYPE_EDGE_RISING] = "edge-rising",
238 	[IRQ_TYPE_EDGE_FALLING] = "edge-falling",
239 	[IRQ_TYPE_EDGE_BOTH] = "edge-both",
240 	[IRQ_TYPE_LEVEL_HIGH] = "level-high",
241 	[IRQ_TYPE_LEVEL_LOW] = "level-low",
242 };
243 
244 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
245 {
246 	return readl(pc->base + reg);
247 }
248 
249 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
250 		u32 val)
251 {
252 	writel(val, pc->base + reg);
253 }
254 
255 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
256 		unsigned bit)
257 {
258 	reg += GPIO_REG_OFFSET(bit) * 4;
259 	return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
260 }
261 
262 /* note NOT a read/modify/write cycle */
263 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
264 		unsigned reg, unsigned bit)
265 {
266 	reg += GPIO_REG_OFFSET(bit) * 4;
267 	bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
268 }
269 
270 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
271 		struct bcm2835_pinctrl *pc, unsigned pin)
272 {
273 	u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
274 	enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
275 
276 	dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
277 			bcm2835_functions[status]);
278 
279 	return status;
280 }
281 
282 static inline void bcm2835_pinctrl_fsel_set(
283 		struct bcm2835_pinctrl *pc, unsigned pin,
284 		enum bcm2835_fsel fsel)
285 {
286 	u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
287 	enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
288 
289 	dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
290 			bcm2835_functions[cur]);
291 
292 	if (cur == fsel)
293 		return;
294 
295 	if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
296 		/* always transition through GPIO_IN */
297 		val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
298 		val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
299 
300 		dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
301 				bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
302 		bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
303 	}
304 
305 	val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
306 	val |= fsel << FSEL_SHIFT(pin);
307 
308 	dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
309 			bcm2835_functions[fsel]);
310 	bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
311 }
312 
313 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
314 {
315 	return pinctrl_gpio_direction_input(chip->base + offset);
316 }
317 
318 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
319 {
320 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
321 
322 	return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
323 }
324 
325 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
326 {
327 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
328 	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
329 
330 	/* Alternative function doesn't clearly provide a direction */
331 	if (fsel > BCM2835_FSEL_GPIO_OUT)
332 		return -EINVAL;
333 
334 	if (fsel == BCM2835_FSEL_GPIO_IN)
335 		return GPIO_LINE_DIRECTION_IN;
336 
337 	return GPIO_LINE_DIRECTION_OUT;
338 }
339 
340 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
341 {
342 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
343 
344 	bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
345 }
346 
347 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
348 		unsigned offset, int value)
349 {
350 	bcm2835_gpio_set(chip, offset, value);
351 	return pinctrl_gpio_direction_output(chip->base + offset);
352 }
353 
354 static const struct gpio_chip bcm2835_gpio_chip = {
355 	.label = MODULE_NAME,
356 	.owner = THIS_MODULE,
357 	.request = gpiochip_generic_request,
358 	.free = gpiochip_generic_free,
359 	.direction_input = bcm2835_gpio_direction_input,
360 	.direction_output = bcm2835_gpio_direction_output,
361 	.get_direction = bcm2835_gpio_get_direction,
362 	.get = bcm2835_gpio_get,
363 	.set = bcm2835_gpio_set,
364 	.set_config = gpiochip_generic_config,
365 	.base = -1,
366 	.ngpio = BCM2835_NUM_GPIOS,
367 	.can_sleep = false,
368 };
369 
370 static const struct gpio_chip bcm2711_gpio_chip = {
371 	.label = "pinctrl-bcm2711",
372 	.owner = THIS_MODULE,
373 	.request = gpiochip_generic_request,
374 	.free = gpiochip_generic_free,
375 	.direction_input = bcm2835_gpio_direction_input,
376 	.direction_output = bcm2835_gpio_direction_output,
377 	.get_direction = bcm2835_gpio_get_direction,
378 	.get = bcm2835_gpio_get,
379 	.set = bcm2835_gpio_set,
380 	.set_config = gpiochip_generic_config,
381 	.base = -1,
382 	.ngpio = BCM2711_NUM_GPIOS,
383 	.can_sleep = false,
384 };
385 
386 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
387 					 unsigned int bank, u32 mask)
388 {
389 	unsigned long events;
390 	unsigned offset;
391 	unsigned gpio;
392 
393 	events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
394 	events &= mask;
395 	events &= pc->enabled_irq_map[bank];
396 	for_each_set_bit(offset, &events, 32) {
397 		gpio = (32 * bank) + offset;
398 		generic_handle_domain_irq(pc->gpio_chip.irq.domain,
399 					  gpio);
400 	}
401 }
402 
403 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
404 {
405 	struct gpio_chip *chip = irq_desc_get_handler_data(desc);
406 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
407 	struct irq_chip *host_chip = irq_desc_get_chip(desc);
408 	int irq = irq_desc_get_irq(desc);
409 	int group;
410 	int i;
411 
412 	for (i = 0; i < BCM2835_NUM_IRQS; i++) {
413 		if (chip->irq.parents[i] == irq) {
414 			group = i;
415 			break;
416 		}
417 	}
418 	/* This should not happen, every IRQ has a bank */
419 	BUG_ON(i == BCM2835_NUM_IRQS);
420 
421 	chained_irq_enter(host_chip, desc);
422 
423 	switch (group) {
424 	case 0: /* IRQ0 covers GPIOs 0-27 */
425 		bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
426 		break;
427 	case 1: /* IRQ1 covers GPIOs 28-45 */
428 		bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
429 		bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
430 		break;
431 	case 2: /* IRQ2 covers GPIOs 46-57 */
432 		bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
433 		break;
434 	}
435 
436 	chained_irq_exit(host_chip, desc);
437 }
438 
439 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
440 {
441 	return IRQ_HANDLED;
442 }
443 
444 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
445 	unsigned reg, unsigned offset, bool enable)
446 {
447 	u32 value;
448 	reg += GPIO_REG_OFFSET(offset) * 4;
449 	value = bcm2835_gpio_rd(pc, reg);
450 	if (enable)
451 		value |= BIT(GPIO_REG_SHIFT(offset));
452 	else
453 		value &= ~(BIT(GPIO_REG_SHIFT(offset)));
454 	bcm2835_gpio_wr(pc, reg, value);
455 }
456 
457 /* fast path for IRQ handler */
458 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
459 	unsigned offset, bool enable)
460 {
461 	switch (pc->irq_type[offset]) {
462 	case IRQ_TYPE_EDGE_RISING:
463 		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
464 		break;
465 
466 	case IRQ_TYPE_EDGE_FALLING:
467 		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
468 		break;
469 
470 	case IRQ_TYPE_EDGE_BOTH:
471 		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
472 		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
473 		break;
474 
475 	case IRQ_TYPE_LEVEL_HIGH:
476 		__bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
477 		break;
478 
479 	case IRQ_TYPE_LEVEL_LOW:
480 		__bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
481 		break;
482 	}
483 }
484 
485 static void bcm2835_gpio_irq_enable(struct irq_data *data)
486 {
487 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
488 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
489 	unsigned gpio = irqd_to_hwirq(data);
490 	unsigned offset = GPIO_REG_SHIFT(gpio);
491 	unsigned bank = GPIO_REG_OFFSET(gpio);
492 	unsigned long flags;
493 
494 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
495 	set_bit(offset, &pc->enabled_irq_map[bank]);
496 	bcm2835_gpio_irq_config(pc, gpio, true);
497 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
498 }
499 
500 static void bcm2835_gpio_irq_disable(struct irq_data *data)
501 {
502 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
503 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
504 	unsigned gpio = irqd_to_hwirq(data);
505 	unsigned offset = GPIO_REG_SHIFT(gpio);
506 	unsigned bank = GPIO_REG_OFFSET(gpio);
507 	unsigned long flags;
508 
509 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
510 	bcm2835_gpio_irq_config(pc, gpio, false);
511 	/* Clear events that were latched prior to clearing event sources */
512 	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
513 	clear_bit(offset, &pc->enabled_irq_map[bank]);
514 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
515 }
516 
517 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
518 	unsigned offset, unsigned int type)
519 {
520 	switch (type) {
521 	case IRQ_TYPE_NONE:
522 	case IRQ_TYPE_EDGE_RISING:
523 	case IRQ_TYPE_EDGE_FALLING:
524 	case IRQ_TYPE_EDGE_BOTH:
525 	case IRQ_TYPE_LEVEL_HIGH:
526 	case IRQ_TYPE_LEVEL_LOW:
527 		pc->irq_type[offset] = type;
528 		break;
529 
530 	default:
531 		return -EINVAL;
532 	}
533 	return 0;
534 }
535 
536 /* slower path for reconfiguring IRQ type */
537 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
538 	unsigned offset, unsigned int type)
539 {
540 	switch (type) {
541 	case IRQ_TYPE_NONE:
542 		if (pc->irq_type[offset] != type) {
543 			bcm2835_gpio_irq_config(pc, offset, false);
544 			pc->irq_type[offset] = type;
545 		}
546 		break;
547 
548 	case IRQ_TYPE_EDGE_RISING:
549 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
550 			/* RISING already enabled, disable FALLING */
551 			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
552 			bcm2835_gpio_irq_config(pc, offset, false);
553 			pc->irq_type[offset] = type;
554 		} else if (pc->irq_type[offset] != type) {
555 			bcm2835_gpio_irq_config(pc, offset, false);
556 			pc->irq_type[offset] = type;
557 			bcm2835_gpio_irq_config(pc, offset, true);
558 		}
559 		break;
560 
561 	case IRQ_TYPE_EDGE_FALLING:
562 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
563 			/* FALLING already enabled, disable RISING */
564 			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
565 			bcm2835_gpio_irq_config(pc, offset, false);
566 			pc->irq_type[offset] = type;
567 		} else if (pc->irq_type[offset] != type) {
568 			bcm2835_gpio_irq_config(pc, offset, false);
569 			pc->irq_type[offset] = type;
570 			bcm2835_gpio_irq_config(pc, offset, true);
571 		}
572 		break;
573 
574 	case IRQ_TYPE_EDGE_BOTH:
575 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
576 			/* RISING already enabled, enable FALLING too */
577 			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
578 			bcm2835_gpio_irq_config(pc, offset, true);
579 			pc->irq_type[offset] = type;
580 		} else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
581 			/* FALLING already enabled, enable RISING too */
582 			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
583 			bcm2835_gpio_irq_config(pc, offset, true);
584 			pc->irq_type[offset] = type;
585 		} else if (pc->irq_type[offset] != type) {
586 			bcm2835_gpio_irq_config(pc, offset, false);
587 			pc->irq_type[offset] = type;
588 			bcm2835_gpio_irq_config(pc, offset, true);
589 		}
590 		break;
591 
592 	case IRQ_TYPE_LEVEL_HIGH:
593 	case IRQ_TYPE_LEVEL_LOW:
594 		if (pc->irq_type[offset] != type) {
595 			bcm2835_gpio_irq_config(pc, offset, false);
596 			pc->irq_type[offset] = type;
597 			bcm2835_gpio_irq_config(pc, offset, true);
598 		}
599 		break;
600 
601 	default:
602 		return -EINVAL;
603 	}
604 	return 0;
605 }
606 
607 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
608 {
609 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
610 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
611 	unsigned gpio = irqd_to_hwirq(data);
612 	unsigned offset = GPIO_REG_SHIFT(gpio);
613 	unsigned bank = GPIO_REG_OFFSET(gpio);
614 	unsigned long flags;
615 	int ret;
616 
617 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
618 
619 	if (test_bit(offset, &pc->enabled_irq_map[bank]))
620 		ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
621 	else
622 		ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
623 
624 	if (type & IRQ_TYPE_EDGE_BOTH)
625 		irq_set_handler_locked(data, handle_edge_irq);
626 	else
627 		irq_set_handler_locked(data, handle_level_irq);
628 
629 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
630 
631 	return ret;
632 }
633 
634 static void bcm2835_gpio_irq_ack(struct irq_data *data)
635 {
636 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
637 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
638 	unsigned gpio = irqd_to_hwirq(data);
639 
640 	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
641 }
642 
643 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
644 {
645 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
646 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
647 	unsigned gpio = irqd_to_hwirq(data);
648 	unsigned int irqgroup;
649 	int ret = -EINVAL;
650 
651 	if (!pc->wake_irq)
652 		return ret;
653 
654 	if (gpio <= 27)
655 		irqgroup = 0;
656 	else if (gpio >= 28 && gpio <= 45)
657 		irqgroup = 1;
658 	else if (gpio >= 46 && gpio <= 57)
659 		irqgroup = 2;
660 	else
661 		return ret;
662 
663 	if (on)
664 		ret = enable_irq_wake(pc->wake_irq[irqgroup]);
665 	else
666 		ret = disable_irq_wake(pc->wake_irq[irqgroup]);
667 
668 	return ret;
669 }
670 
671 static struct irq_chip bcm2835_gpio_irq_chip = {
672 	.name = MODULE_NAME,
673 	.irq_enable = bcm2835_gpio_irq_enable,
674 	.irq_disable = bcm2835_gpio_irq_disable,
675 	.irq_set_type = bcm2835_gpio_irq_set_type,
676 	.irq_ack = bcm2835_gpio_irq_ack,
677 	.irq_mask = bcm2835_gpio_irq_disable,
678 	.irq_unmask = bcm2835_gpio_irq_enable,
679 	.irq_set_wake = bcm2835_gpio_irq_set_wake,
680 	.flags = IRQCHIP_MASK_ON_SUSPEND,
681 };
682 
683 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
684 {
685 	return BCM2835_NUM_GPIOS;
686 }
687 
688 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
689 		unsigned selector)
690 {
691 	return bcm2835_gpio_groups[selector];
692 }
693 
694 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
695 		unsigned selector,
696 		const unsigned **pins,
697 		unsigned *num_pins)
698 {
699 	*pins = &bcm2835_gpio_pins[selector].number;
700 	*num_pins = 1;
701 
702 	return 0;
703 }
704 
705 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
706 		struct seq_file *s,
707 		unsigned offset)
708 {
709 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
710 	struct gpio_chip *chip = &pc->gpio_chip;
711 	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
712 	const char *fname = bcm2835_functions[fsel];
713 	int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
714 	int irq = irq_find_mapping(chip->irq.domain, offset);
715 
716 	seq_printf(s, "function %s in %s; irq %d (%s)",
717 		fname, value ? "hi" : "lo",
718 		irq, irq_type_names[pc->irq_type[offset]]);
719 }
720 
721 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
722 		struct pinctrl_map *maps, unsigned num_maps)
723 {
724 	int i;
725 
726 	for (i = 0; i < num_maps; i++)
727 		if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
728 			kfree(maps[i].data.configs.configs);
729 
730 	kfree(maps);
731 }
732 
733 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
734 		struct device_node *np, u32 pin, u32 fnum,
735 		struct pinctrl_map **maps)
736 {
737 	struct pinctrl_map *map = *maps;
738 
739 	if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
740 		dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
741 		return -EINVAL;
742 	}
743 
744 	map->type = PIN_MAP_TYPE_MUX_GROUP;
745 	map->data.mux.group = bcm2835_gpio_groups[pin];
746 	map->data.mux.function = bcm2835_functions[fnum];
747 	(*maps)++;
748 
749 	return 0;
750 }
751 
752 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
753 		struct device_node *np, u32 pin, u32 pull,
754 		struct pinctrl_map **maps)
755 {
756 	struct pinctrl_map *map = *maps;
757 	unsigned long *configs;
758 
759 	if (pull > 2) {
760 		dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
761 		return -EINVAL;
762 	}
763 
764 	configs = kzalloc(sizeof(*configs), GFP_KERNEL);
765 	if (!configs)
766 		return -ENOMEM;
767 	configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
768 
769 	map->type = PIN_MAP_TYPE_CONFIGS_PIN;
770 	map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
771 	map->data.configs.configs = configs;
772 	map->data.configs.num_configs = 1;
773 	(*maps)++;
774 
775 	return 0;
776 }
777 
778 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
779 		struct device_node *np,
780 		struct pinctrl_map **map, unsigned int *num_maps)
781 {
782 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
783 	struct property *pins, *funcs, *pulls;
784 	int num_pins, num_funcs, num_pulls, maps_per_pin;
785 	struct pinctrl_map *maps, *cur_map;
786 	int i, err;
787 	u32 pin, func, pull;
788 
789 	/* Check for generic binding in this node */
790 	err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
791 	if (err || *num_maps)
792 		return err;
793 
794 	/* Generic binding did not find anything continue with legacy parse */
795 	pins = of_find_property(np, "brcm,pins", NULL);
796 	if (!pins) {
797 		dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
798 		return -EINVAL;
799 	}
800 
801 	funcs = of_find_property(np, "brcm,function", NULL);
802 	pulls = of_find_property(np, "brcm,pull", NULL);
803 
804 	if (!funcs && !pulls) {
805 		dev_err(pc->dev,
806 			"%pOF: neither brcm,function nor brcm,pull specified\n",
807 			np);
808 		return -EINVAL;
809 	}
810 
811 	num_pins = pins->length / 4;
812 	num_funcs = funcs ? (funcs->length / 4) : 0;
813 	num_pulls = pulls ? (pulls->length / 4) : 0;
814 
815 	if (num_funcs > 1 && num_funcs != num_pins) {
816 		dev_err(pc->dev,
817 			"%pOF: brcm,function must have 1 or %d entries\n",
818 			np, num_pins);
819 		return -EINVAL;
820 	}
821 
822 	if (num_pulls > 1 && num_pulls != num_pins) {
823 		dev_err(pc->dev,
824 			"%pOF: brcm,pull must have 1 or %d entries\n",
825 			np, num_pins);
826 		return -EINVAL;
827 	}
828 
829 	maps_per_pin = 0;
830 	if (num_funcs)
831 		maps_per_pin++;
832 	if (num_pulls)
833 		maps_per_pin++;
834 	cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
835 				 GFP_KERNEL);
836 	if (!maps)
837 		return -ENOMEM;
838 
839 	for (i = 0; i < num_pins; i++) {
840 		err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
841 		if (err)
842 			goto out;
843 		if (pin >= pc->pctl_desc.npins) {
844 			dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
845 				np, pin);
846 			err = -EINVAL;
847 			goto out;
848 		}
849 
850 		if (num_funcs) {
851 			err = of_property_read_u32_index(np, "brcm,function",
852 					(num_funcs > 1) ? i : 0, &func);
853 			if (err)
854 				goto out;
855 			err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
856 							func, &cur_map);
857 			if (err)
858 				goto out;
859 		}
860 		if (num_pulls) {
861 			err = of_property_read_u32_index(np, "brcm,pull",
862 					(num_pulls > 1) ? i : 0, &pull);
863 			if (err)
864 				goto out;
865 			err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
866 							pull, &cur_map);
867 			if (err)
868 				goto out;
869 		}
870 	}
871 
872 	*map = maps;
873 	*num_maps = num_pins * maps_per_pin;
874 
875 	return 0;
876 
877 out:
878 	bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
879 	return err;
880 }
881 
882 static const struct pinctrl_ops bcm2835_pctl_ops = {
883 	.get_groups_count = bcm2835_pctl_get_groups_count,
884 	.get_group_name = bcm2835_pctl_get_group_name,
885 	.get_group_pins = bcm2835_pctl_get_group_pins,
886 	.pin_dbg_show = bcm2835_pctl_pin_dbg_show,
887 	.dt_node_to_map = bcm2835_pctl_dt_node_to_map,
888 	.dt_free_map = bcm2835_pctl_dt_free_map,
889 };
890 
891 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
892 		unsigned offset)
893 {
894 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
895 
896 	/* disable by setting to GPIO_IN */
897 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
898 	return 0;
899 }
900 
901 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
902 {
903 	return BCM2835_FSEL_COUNT;
904 }
905 
906 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
907 		unsigned selector)
908 {
909 	return bcm2835_functions[selector];
910 }
911 
912 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
913 		unsigned selector,
914 		const char * const **groups,
915 		unsigned * const num_groups)
916 {
917 	/* every pin can do every function */
918 	*groups = bcm2835_gpio_groups;
919 	*num_groups = BCM2835_NUM_GPIOS;
920 
921 	return 0;
922 }
923 
924 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
925 		unsigned func_selector,
926 		unsigned group_selector)
927 {
928 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
929 
930 	bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
931 
932 	return 0;
933 }
934 
935 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
936 		struct pinctrl_gpio_range *range,
937 		unsigned offset)
938 {
939 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
940 
941 	/* disable by setting to GPIO_IN */
942 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
943 }
944 
945 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
946 		struct pinctrl_gpio_range *range,
947 		unsigned offset,
948 		bool input)
949 {
950 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
951 	enum bcm2835_fsel fsel = input ?
952 		BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
953 
954 	bcm2835_pinctrl_fsel_set(pc, offset, fsel);
955 
956 	return 0;
957 }
958 
959 static const struct pinmux_ops bcm2835_pmx_ops = {
960 	.free = bcm2835_pmx_free,
961 	.get_functions_count = bcm2835_pmx_get_functions_count,
962 	.get_function_name = bcm2835_pmx_get_function_name,
963 	.get_function_groups = bcm2835_pmx_get_function_groups,
964 	.set_mux = bcm2835_pmx_set,
965 	.gpio_disable_free = bcm2835_pmx_gpio_disable_free,
966 	.gpio_set_direction = bcm2835_pmx_gpio_set_direction,
967 };
968 
969 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
970 			unsigned pin, unsigned long *config)
971 {
972 	/* No way to read back config in HW */
973 	return -ENOTSUPP;
974 }
975 
976 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
977 		unsigned int pin, unsigned int arg)
978 {
979 	u32 off, bit;
980 
981 	off = GPIO_REG_OFFSET(pin);
982 	bit = GPIO_REG_SHIFT(pin);
983 
984 	bcm2835_gpio_wr(pc, GPPUD, arg & 3);
985 	/*
986 	 * BCM2835 datasheet say to wait 150 cycles, but not of what.
987 	 * But the VideoCore firmware delay for this operation
988 	 * based nearly on the same amount of VPU cycles and this clock
989 	 * runs at 250 MHz.
990 	 */
991 	udelay(1);
992 	bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
993 	udelay(1);
994 	bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
995 }
996 
997 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
998 			unsigned int pin, unsigned long *configs,
999 			unsigned int num_configs)
1000 {
1001 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1002 	u32 param, arg;
1003 	int i;
1004 
1005 	for (i = 0; i < num_configs; i++) {
1006 		param = pinconf_to_config_param(configs[i]);
1007 		arg = pinconf_to_config_argument(configs[i]);
1008 
1009 		switch (param) {
1010 		/* Set legacy brcm,pull */
1011 		case BCM2835_PINCONF_PARAM_PULL:
1012 			bcm2835_pull_config_set(pc, pin, arg);
1013 			break;
1014 
1015 		/* Set pull generic bindings */
1016 		case PIN_CONFIG_BIAS_DISABLE:
1017 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1018 			break;
1019 
1020 		case PIN_CONFIG_BIAS_PULL_DOWN:
1021 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1022 			break;
1023 
1024 		case PIN_CONFIG_BIAS_PULL_UP:
1025 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1026 			break;
1027 
1028 		/* Set output-high or output-low */
1029 		case PIN_CONFIG_OUTPUT:
1030 			bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1031 			break;
1032 
1033 		default:
1034 			return -ENOTSUPP;
1035 
1036 		} /* switch param type */
1037 	} /* for each config */
1038 
1039 	return 0;
1040 }
1041 
1042 static const struct pinconf_ops bcm2835_pinconf_ops = {
1043 	.is_generic = true,
1044 	.pin_config_get = bcm2835_pinconf_get,
1045 	.pin_config_set = bcm2835_pinconf_set,
1046 };
1047 
1048 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1049 				    unsigned int pin, unsigned int arg)
1050 {
1051 	u32 shifter;
1052 	u32 value;
1053 	u32 off;
1054 
1055 	off = PUD_2711_REG_OFFSET(pin);
1056 	shifter = PUD_2711_REG_SHIFT(pin);
1057 
1058 	value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1059 	value &= ~(PUD_2711_MASK << shifter);
1060 	value |= (arg << shifter);
1061 	bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1062 }
1063 
1064 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1065 			       unsigned int pin, unsigned long *configs,
1066 			       unsigned int num_configs)
1067 {
1068 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1069 	u32 param, arg;
1070 	int i;
1071 
1072 	for (i = 0; i < num_configs; i++) {
1073 		param = pinconf_to_config_param(configs[i]);
1074 		arg = pinconf_to_config_argument(configs[i]);
1075 
1076 		switch (param) {
1077 		/* convert legacy brcm,pull */
1078 		case BCM2835_PINCONF_PARAM_PULL:
1079 			if (arg == BCM2835_PUD_UP)
1080 				arg = BCM2711_PULL_UP;
1081 			else if (arg == BCM2835_PUD_DOWN)
1082 				arg = BCM2711_PULL_DOWN;
1083 			else
1084 				arg = BCM2711_PULL_NONE;
1085 
1086 			bcm2711_pull_config_set(pc, pin, arg);
1087 			break;
1088 
1089 		/* Set pull generic bindings */
1090 		case PIN_CONFIG_BIAS_DISABLE:
1091 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1092 			break;
1093 		case PIN_CONFIG_BIAS_PULL_DOWN:
1094 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1095 			break;
1096 		case PIN_CONFIG_BIAS_PULL_UP:
1097 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1098 			break;
1099 
1100 		/* Set output-high or output-low */
1101 		case PIN_CONFIG_OUTPUT:
1102 			bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1103 			break;
1104 
1105 		default:
1106 			return -ENOTSUPP;
1107 		}
1108 	} /* for each config */
1109 
1110 	return 0;
1111 }
1112 
1113 static const struct pinconf_ops bcm2711_pinconf_ops = {
1114 	.is_generic = true,
1115 	.pin_config_get = bcm2835_pinconf_get,
1116 	.pin_config_set = bcm2711_pinconf_set,
1117 };
1118 
1119 static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1120 	.name = MODULE_NAME,
1121 	.pins = bcm2835_gpio_pins,
1122 	.npins = BCM2835_NUM_GPIOS,
1123 	.pctlops = &bcm2835_pctl_ops,
1124 	.pmxops = &bcm2835_pmx_ops,
1125 	.confops = &bcm2835_pinconf_ops,
1126 	.owner = THIS_MODULE,
1127 };
1128 
1129 static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1130 	.name = "pinctrl-bcm2711",
1131 	.pins = bcm2835_gpio_pins,
1132 	.npins = BCM2711_NUM_GPIOS,
1133 	.pctlops = &bcm2835_pctl_ops,
1134 	.pmxops = &bcm2835_pmx_ops,
1135 	.confops = &bcm2711_pinconf_ops,
1136 	.owner = THIS_MODULE,
1137 };
1138 
1139 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1140 	.name = MODULE_NAME,
1141 	.npins = BCM2835_NUM_GPIOS,
1142 };
1143 
1144 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1145 	.name = "pinctrl-bcm2711",
1146 	.npins = BCM2711_NUM_GPIOS,
1147 };
1148 
1149 struct bcm_plat_data {
1150 	const struct gpio_chip *gpio_chip;
1151 	const struct pinctrl_desc *pctl_desc;
1152 	const struct pinctrl_gpio_range *gpio_range;
1153 };
1154 
1155 static const struct bcm_plat_data bcm2835_plat_data = {
1156 	.gpio_chip = &bcm2835_gpio_chip,
1157 	.pctl_desc = &bcm2835_pinctrl_desc,
1158 	.gpio_range = &bcm2835_pinctrl_gpio_range,
1159 };
1160 
1161 static const struct bcm_plat_data bcm2711_plat_data = {
1162 	.gpio_chip = &bcm2711_gpio_chip,
1163 	.pctl_desc = &bcm2711_pinctrl_desc,
1164 	.gpio_range = &bcm2711_pinctrl_gpio_range,
1165 };
1166 
1167 static const struct of_device_id bcm2835_pinctrl_match[] = {
1168 	{
1169 		.compatible = "brcm,bcm2835-gpio",
1170 		.data = &bcm2835_plat_data,
1171 	},
1172 	{
1173 		.compatible = "brcm,bcm2711-gpio",
1174 		.data = &bcm2711_plat_data,
1175 	},
1176 	{
1177 		.compatible = "brcm,bcm7211-gpio",
1178 		.data = &bcm2711_plat_data,
1179 	},
1180 	{}
1181 };
1182 
1183 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1184 {
1185 	struct device *dev = &pdev->dev;
1186 	struct device_node *np = dev->of_node;
1187 	const struct bcm_plat_data *pdata;
1188 	struct bcm2835_pinctrl *pc;
1189 	struct gpio_irq_chip *girq;
1190 	struct resource iomem;
1191 	int err, i;
1192 	const struct of_device_id *match;
1193 	int is_7211 = 0;
1194 
1195 	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1196 	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1197 
1198 	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1199 	if (!pc)
1200 		return -ENOMEM;
1201 
1202 	platform_set_drvdata(pdev, pc);
1203 	pc->dev = dev;
1204 
1205 	err = of_address_to_resource(np, 0, &iomem);
1206 	if (err) {
1207 		dev_err(dev, "could not get IO memory\n");
1208 		return err;
1209 	}
1210 
1211 	pc->base = devm_ioremap_resource(dev, &iomem);
1212 	if (IS_ERR(pc->base))
1213 		return PTR_ERR(pc->base);
1214 
1215 	match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1216 	if (!match)
1217 		return -EINVAL;
1218 
1219 	pdata = match->data;
1220 	is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1221 
1222 	pc->gpio_chip = *pdata->gpio_chip;
1223 	pc->gpio_chip.parent = dev;
1224 	pc->gpio_chip.of_node = np;
1225 
1226 	for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1227 		unsigned long events;
1228 		unsigned offset;
1229 
1230 		/* clear event detection flags */
1231 		bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1232 		bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1233 		bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1234 		bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1235 		bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1236 		bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1237 
1238 		/* clear all the events */
1239 		events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1240 		for_each_set_bit(offset, &events, 32)
1241 			bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1242 
1243 		raw_spin_lock_init(&pc->irq_lock[i]);
1244 	}
1245 
1246 	girq = &pc->gpio_chip.irq;
1247 	girq->chip = &bcm2835_gpio_irq_chip;
1248 	girq->parent_handler = bcm2835_gpio_irq_handler;
1249 	girq->num_parents = BCM2835_NUM_IRQS;
1250 	girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1251 				     sizeof(*girq->parents),
1252 				     GFP_KERNEL);
1253 	if (!girq->parents)
1254 		return -ENOMEM;
1255 
1256 	if (is_7211) {
1257 		pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1258 					    sizeof(*pc->wake_irq),
1259 					    GFP_KERNEL);
1260 		if (!pc->wake_irq)
1261 			return -ENOMEM;
1262 	}
1263 
1264 	/*
1265 	 * Use the same handler for all groups: this is necessary
1266 	 * since we use one gpiochip to cover all lines - the
1267 	 * irq handler then needs to figure out which group and
1268 	 * bank that was firing the IRQ and look up the per-group
1269 	 * and bank data.
1270 	 */
1271 	for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1272 		int len;
1273 		char *name;
1274 
1275 		girq->parents[i] = irq_of_parse_and_map(np, i);
1276 		if (!is_7211) {
1277 			if (!girq->parents[i]) {
1278 				girq->num_parents = i;
1279 				break;
1280 			}
1281 			continue;
1282 		}
1283 		/* Skip over the all banks interrupts */
1284 		pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1285 						       BCM2835_NUM_IRQS + 1);
1286 
1287 		len = strlen(dev_name(pc->dev)) + 16;
1288 		name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1289 		if (!name)
1290 			return -ENOMEM;
1291 
1292 		snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1293 
1294 		/* These are optional interrupts */
1295 		err = devm_request_irq(dev, pc->wake_irq[i],
1296 				       bcm2835_gpio_wake_irq_handler,
1297 				       IRQF_SHARED, name, pc);
1298 		if (err)
1299 			dev_warn(dev, "unable to request wake IRQ %d\n",
1300 				 pc->wake_irq[i]);
1301 	}
1302 
1303 	girq->default_type = IRQ_TYPE_NONE;
1304 	girq->handler = handle_level_irq;
1305 
1306 	err = gpiochip_add_data(&pc->gpio_chip, pc);
1307 	if (err) {
1308 		dev_err(dev, "could not add GPIO chip\n");
1309 		return err;
1310 	}
1311 
1312 	pc->pctl_desc = *pdata->pctl_desc;
1313 	pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1314 	if (IS_ERR(pc->pctl_dev)) {
1315 		gpiochip_remove(&pc->gpio_chip);
1316 		return PTR_ERR(pc->pctl_dev);
1317 	}
1318 
1319 	pc->gpio_range = *pdata->gpio_range;
1320 	pc->gpio_range.base = pc->gpio_chip.base;
1321 	pc->gpio_range.gc = &pc->gpio_chip;
1322 	pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1323 
1324 	return 0;
1325 }
1326 
1327 static struct platform_driver bcm2835_pinctrl_driver = {
1328 	.probe = bcm2835_pinctrl_probe,
1329 	.driver = {
1330 		.name = MODULE_NAME,
1331 		.of_match_table = bcm2835_pinctrl_match,
1332 		.suppress_bind_attrs = true,
1333 	},
1334 };
1335 builtin_platform_driver(bcm2835_pinctrl_driver);
1336