1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO) 4 * 5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren 6 * 7 * This driver is inspired by: 8 * pinctrl-nomadik.c, please see original file for copyright information 9 * pinctrl-tegra.c, please see original file for copyright information 10 */ 11 12 #include <linux/bitmap.h> 13 #include <linux/bug.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/err.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/io.h> 19 #include <linux/irq.h> 20 #include <linux/irqdesc.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/module.h> 24 #include <linux/of_address.h> 25 #include <linux/of.h> 26 #include <linux/of_irq.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/pinctrl/machine.h> 29 #include <linux/pinctrl/pinconf.h> 30 #include <linux/pinctrl/pinctrl.h> 31 #include <linux/pinctrl/pinmux.h> 32 #include <linux/pinctrl/pinconf-generic.h> 33 #include <linux/platform_device.h> 34 #include <linux/seq_file.h> 35 #include <linux/slab.h> 36 #include <linux/spinlock.h> 37 #include <linux/string_choices.h> 38 #include <linux/types.h> 39 #include <dt-bindings/pinctrl/bcm2835.h> 40 41 #define MODULE_NAME "pinctrl-bcm2835" 42 #define BCM2835_NUM_GPIOS 54 43 #define BCM2711_NUM_GPIOS 58 44 #define BCM2835_NUM_BANKS 2 45 #define BCM2835_NUM_IRQS 3 46 47 /* GPIO register offsets */ 48 #define GPFSEL0 0x0 /* Function Select */ 49 #define GPSET0 0x1c /* Pin Output Set */ 50 #define GPCLR0 0x28 /* Pin Output Clear */ 51 #define GPLEV0 0x34 /* Pin Level */ 52 #define GPEDS0 0x40 /* Pin Event Detect Status */ 53 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */ 54 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */ 55 #define GPHEN0 0x64 /* Pin High Detect Enable */ 56 #define GPLEN0 0x70 /* Pin Low Detect Enable */ 57 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */ 58 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */ 59 #define GPPUD 0x94 /* Pin Pull-up/down Enable */ 60 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */ 61 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */ 62 63 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4)) 64 #define FSEL_SHIFT(p) (((p) % 10) * 3) 65 #define GPIO_REG_OFFSET(p) ((p) / 32) 66 #define GPIO_REG_SHIFT(p) ((p) % 32) 67 68 #define PUD_2711_MASK 0x3 69 #define PUD_2711_REG_OFFSET(p) ((p) / 16) 70 #define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2) 71 72 /* argument: bcm2835_pinconf_pull */ 73 #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1) 74 75 #define BCM2711_PULL_NONE 0x0 76 #define BCM2711_PULL_UP 0x1 77 #define BCM2711_PULL_DOWN 0x2 78 79 struct bcm2835_pinctrl { 80 struct device *dev; 81 void __iomem *base; 82 int *wake_irq; 83 84 /* note: locking assumes each bank will have its own unsigned long */ 85 unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; 86 unsigned int irq_type[BCM2711_NUM_GPIOS]; 87 88 struct pinctrl_dev *pctl_dev; 89 struct gpio_chip gpio_chip; 90 struct pinctrl_desc pctl_desc; 91 struct pinctrl_gpio_range gpio_range; 92 93 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS]; 94 /* Protect FSEL registers */ 95 spinlock_t fsel_lock; 96 }; 97 98 /* pins are just named GPIO0..GPIO53 */ 99 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) 100 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = { 101 BCM2835_GPIO_PIN(0), 102 BCM2835_GPIO_PIN(1), 103 BCM2835_GPIO_PIN(2), 104 BCM2835_GPIO_PIN(3), 105 BCM2835_GPIO_PIN(4), 106 BCM2835_GPIO_PIN(5), 107 BCM2835_GPIO_PIN(6), 108 BCM2835_GPIO_PIN(7), 109 BCM2835_GPIO_PIN(8), 110 BCM2835_GPIO_PIN(9), 111 BCM2835_GPIO_PIN(10), 112 BCM2835_GPIO_PIN(11), 113 BCM2835_GPIO_PIN(12), 114 BCM2835_GPIO_PIN(13), 115 BCM2835_GPIO_PIN(14), 116 BCM2835_GPIO_PIN(15), 117 BCM2835_GPIO_PIN(16), 118 BCM2835_GPIO_PIN(17), 119 BCM2835_GPIO_PIN(18), 120 BCM2835_GPIO_PIN(19), 121 BCM2835_GPIO_PIN(20), 122 BCM2835_GPIO_PIN(21), 123 BCM2835_GPIO_PIN(22), 124 BCM2835_GPIO_PIN(23), 125 BCM2835_GPIO_PIN(24), 126 BCM2835_GPIO_PIN(25), 127 BCM2835_GPIO_PIN(26), 128 BCM2835_GPIO_PIN(27), 129 BCM2835_GPIO_PIN(28), 130 BCM2835_GPIO_PIN(29), 131 BCM2835_GPIO_PIN(30), 132 BCM2835_GPIO_PIN(31), 133 BCM2835_GPIO_PIN(32), 134 BCM2835_GPIO_PIN(33), 135 BCM2835_GPIO_PIN(34), 136 BCM2835_GPIO_PIN(35), 137 BCM2835_GPIO_PIN(36), 138 BCM2835_GPIO_PIN(37), 139 BCM2835_GPIO_PIN(38), 140 BCM2835_GPIO_PIN(39), 141 BCM2835_GPIO_PIN(40), 142 BCM2835_GPIO_PIN(41), 143 BCM2835_GPIO_PIN(42), 144 BCM2835_GPIO_PIN(43), 145 BCM2835_GPIO_PIN(44), 146 BCM2835_GPIO_PIN(45), 147 BCM2835_GPIO_PIN(46), 148 BCM2835_GPIO_PIN(47), 149 BCM2835_GPIO_PIN(48), 150 BCM2835_GPIO_PIN(49), 151 BCM2835_GPIO_PIN(50), 152 BCM2835_GPIO_PIN(51), 153 BCM2835_GPIO_PIN(52), 154 BCM2835_GPIO_PIN(53), 155 BCM2835_GPIO_PIN(54), 156 BCM2835_GPIO_PIN(55), 157 BCM2835_GPIO_PIN(56), 158 BCM2835_GPIO_PIN(57), 159 }; 160 161 /* one pin per group */ 162 static const char * const bcm2835_gpio_groups[] = { 163 "gpio0", 164 "gpio1", 165 "gpio2", 166 "gpio3", 167 "gpio4", 168 "gpio5", 169 "gpio6", 170 "gpio7", 171 "gpio8", 172 "gpio9", 173 "gpio10", 174 "gpio11", 175 "gpio12", 176 "gpio13", 177 "gpio14", 178 "gpio15", 179 "gpio16", 180 "gpio17", 181 "gpio18", 182 "gpio19", 183 "gpio20", 184 "gpio21", 185 "gpio22", 186 "gpio23", 187 "gpio24", 188 "gpio25", 189 "gpio26", 190 "gpio27", 191 "gpio28", 192 "gpio29", 193 "gpio30", 194 "gpio31", 195 "gpio32", 196 "gpio33", 197 "gpio34", 198 "gpio35", 199 "gpio36", 200 "gpio37", 201 "gpio38", 202 "gpio39", 203 "gpio40", 204 "gpio41", 205 "gpio42", 206 "gpio43", 207 "gpio44", 208 "gpio45", 209 "gpio46", 210 "gpio47", 211 "gpio48", 212 "gpio49", 213 "gpio50", 214 "gpio51", 215 "gpio52", 216 "gpio53", 217 "gpio54", 218 "gpio55", 219 "gpio56", 220 "gpio57", 221 }; 222 223 enum bcm2835_fsel { 224 BCM2835_FSEL_COUNT = 8, 225 BCM2835_FSEL_MASK = 0x7, 226 }; 227 228 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = { 229 [BCM2835_FSEL_GPIO_IN] = "gpio_in", 230 [BCM2835_FSEL_GPIO_OUT] = "gpio_out", 231 [BCM2835_FSEL_ALT0] = "alt0", 232 [BCM2835_FSEL_ALT1] = "alt1", 233 [BCM2835_FSEL_ALT2] = "alt2", 234 [BCM2835_FSEL_ALT3] = "alt3", 235 [BCM2835_FSEL_ALT4] = "alt4", 236 [BCM2835_FSEL_ALT5] = "alt5", 237 }; 238 239 static const char * const irq_type_names[] = { 240 [IRQ_TYPE_NONE] = "none", 241 [IRQ_TYPE_EDGE_RISING] = "edge-rising", 242 [IRQ_TYPE_EDGE_FALLING] = "edge-falling", 243 [IRQ_TYPE_EDGE_BOTH] = "edge-both", 244 [IRQ_TYPE_LEVEL_HIGH] = "level-high", 245 [IRQ_TYPE_LEVEL_LOW] = "level-low", 246 }; 247 248 static bool persist_gpio_outputs; 249 module_param(persist_gpio_outputs, bool, 0444); 250 MODULE_PARM_DESC(persist_gpio_outputs, "Enable GPIO_OUT persistence when pin is freed"); 251 252 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg) 253 { 254 return readl(pc->base + reg); 255 } 256 257 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg, 258 u32 val) 259 { 260 writel(val, pc->base + reg); 261 } 262 263 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg, 264 unsigned bit) 265 { 266 reg += GPIO_REG_OFFSET(bit) * 4; 267 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1; 268 } 269 270 /* note NOT a read/modify/write cycle */ 271 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc, 272 unsigned reg, unsigned bit) 273 { 274 reg += GPIO_REG_OFFSET(bit) * 4; 275 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit))); 276 } 277 278 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get( 279 struct bcm2835_pinctrl *pc, unsigned pin) 280 { 281 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 282 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 283 284 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin, 285 bcm2835_functions[status]); 286 287 return status; 288 } 289 290 static inline void bcm2835_pinctrl_fsel_set( 291 struct bcm2835_pinctrl *pc, unsigned pin, 292 enum bcm2835_fsel fsel) 293 { 294 u32 val; 295 enum bcm2835_fsel cur; 296 unsigned long flags; 297 298 spin_lock_irqsave(&pc->fsel_lock, flags); 299 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 300 cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 301 302 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin, 303 bcm2835_functions[cur]); 304 305 if (cur == fsel) 306 goto unlock; 307 308 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) { 309 /* always transition through GPIO_IN */ 310 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 311 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin); 312 313 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin, 314 bcm2835_functions[BCM2835_FSEL_GPIO_IN]); 315 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 316 } 317 318 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 319 val |= fsel << FSEL_SHIFT(pin); 320 321 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin, 322 bcm2835_functions[fsel]); 323 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 324 325 unlock: 326 spin_unlock_irqrestore(&pc->fsel_lock, flags); 327 } 328 329 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 330 { 331 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 332 333 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); 334 return 0; 335 } 336 337 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) 338 { 339 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 340 341 return bcm2835_gpio_get_bit(pc, GPLEV0, offset); 342 } 343 344 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 345 { 346 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 347 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 348 349 if (fsel == BCM2835_FSEL_GPIO_OUT) 350 return GPIO_LINE_DIRECTION_OUT; 351 352 /* 353 * Alternative function doesn't clearly provide a direction. Default 354 * to INPUT. 355 */ 356 return GPIO_LINE_DIRECTION_IN; 357 } 358 359 static int bcm2835_gpio_set(struct gpio_chip *chip, unsigned int offset, 360 int value) 361 { 362 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 363 364 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); 365 366 return 0; 367 } 368 369 static int bcm2835_gpio_direction_output(struct gpio_chip *chip, 370 unsigned offset, int value) 371 { 372 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 373 374 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); 375 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT); 376 return 0; 377 } 378 379 static int bcm2835_add_pin_ranges_fallback(struct gpio_chip *gc) 380 { 381 struct device_node *np = dev_of_node(gc->parent); 382 struct pinctrl_dev *pctldev = of_pinctrl_get(np); 383 384 if (!pctldev) 385 return 0; 386 387 return gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0, 388 gc->ngpio); 389 } 390 391 static const struct gpio_chip bcm2835_gpio_chip = { 392 .label = MODULE_NAME, 393 .owner = THIS_MODULE, 394 .request = gpiochip_generic_request, 395 .free = gpiochip_generic_free, 396 .direction_input = bcm2835_gpio_direction_input, 397 .direction_output = bcm2835_gpio_direction_output, 398 .get_direction = bcm2835_gpio_get_direction, 399 .get = bcm2835_gpio_get, 400 .set = bcm2835_gpio_set, 401 .set_config = gpiochip_generic_config, 402 .base = -1, 403 .ngpio = BCM2835_NUM_GPIOS, 404 .can_sleep = false, 405 .add_pin_ranges = bcm2835_add_pin_ranges_fallback, 406 }; 407 408 static const struct gpio_chip bcm2711_gpio_chip = { 409 .label = "pinctrl-bcm2711", 410 .owner = THIS_MODULE, 411 .request = gpiochip_generic_request, 412 .free = gpiochip_generic_free, 413 .direction_input = bcm2835_gpio_direction_input, 414 .direction_output = bcm2835_gpio_direction_output, 415 .get_direction = bcm2835_gpio_get_direction, 416 .get = bcm2835_gpio_get, 417 .set = bcm2835_gpio_set, 418 .set_config = gpiochip_generic_config, 419 .base = -1, 420 .ngpio = BCM2711_NUM_GPIOS, 421 .can_sleep = false, 422 .add_pin_ranges = bcm2835_add_pin_ranges_fallback, 423 }; 424 425 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, 426 unsigned int bank, u32 mask) 427 { 428 unsigned long events; 429 unsigned offset; 430 unsigned gpio; 431 432 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); 433 events &= mask; 434 events &= pc->enabled_irq_map[bank]; 435 for_each_set_bit(offset, &events, 32) { 436 gpio = (32 * bank) + offset; 437 generic_handle_domain_irq(pc->gpio_chip.irq.domain, 438 gpio); 439 } 440 } 441 442 static void bcm2835_gpio_irq_handler(struct irq_desc *desc) 443 { 444 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 445 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 446 struct irq_chip *host_chip = irq_desc_get_chip(desc); 447 int irq = irq_desc_get_irq(desc); 448 int group = 0; 449 int i; 450 451 for (i = 0; i < BCM2835_NUM_IRQS; i++) { 452 if (chip->irq.parents[i] == irq) { 453 group = i; 454 break; 455 } 456 } 457 /* This should not happen, every IRQ has a bank */ 458 BUG_ON(i == BCM2835_NUM_IRQS); 459 460 chained_irq_enter(host_chip, desc); 461 462 switch (group) { 463 case 0: /* IRQ0 covers GPIOs 0-27 */ 464 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff); 465 break; 466 case 1: /* IRQ1 covers GPIOs 28-45 */ 467 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000); 468 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff); 469 break; 470 case 2: /* IRQ2 covers GPIOs 46-57 */ 471 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000); 472 break; 473 } 474 475 chained_irq_exit(host_chip, desc); 476 } 477 478 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id) 479 { 480 return IRQ_HANDLED; 481 } 482 483 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 484 unsigned reg, unsigned offset, bool enable) 485 { 486 u32 value; 487 reg += GPIO_REG_OFFSET(offset) * 4; 488 value = bcm2835_gpio_rd(pc, reg); 489 if (enable) 490 value |= BIT(GPIO_REG_SHIFT(offset)); 491 else 492 value &= ~(BIT(GPIO_REG_SHIFT(offset))); 493 bcm2835_gpio_wr(pc, reg, value); 494 } 495 496 /* fast path for IRQ handler */ 497 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 498 unsigned offset, bool enable) 499 { 500 switch (pc->irq_type[offset]) { 501 case IRQ_TYPE_EDGE_RISING: 502 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 503 break; 504 505 case IRQ_TYPE_EDGE_FALLING: 506 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 507 break; 508 509 case IRQ_TYPE_EDGE_BOTH: 510 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 511 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 512 break; 513 514 case IRQ_TYPE_LEVEL_HIGH: 515 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable); 516 break; 517 518 case IRQ_TYPE_LEVEL_LOW: 519 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable); 520 break; 521 } 522 } 523 524 static void bcm2835_gpio_irq_unmask(struct irq_data *data) 525 { 526 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 527 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 528 unsigned gpio = irqd_to_hwirq(data); 529 unsigned offset = GPIO_REG_SHIFT(gpio); 530 unsigned bank = GPIO_REG_OFFSET(gpio); 531 unsigned long flags; 532 533 gpiochip_enable_irq(chip, gpio); 534 535 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); 536 set_bit(offset, &pc->enabled_irq_map[bank]); 537 bcm2835_gpio_irq_config(pc, gpio, true); 538 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 539 } 540 541 static void bcm2835_gpio_irq_mask(struct irq_data *data) 542 { 543 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 544 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 545 unsigned gpio = irqd_to_hwirq(data); 546 unsigned offset = GPIO_REG_SHIFT(gpio); 547 unsigned bank = GPIO_REG_OFFSET(gpio); 548 unsigned long flags; 549 550 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); 551 bcm2835_gpio_irq_config(pc, gpio, false); 552 /* Clear events that were latched prior to clearing event sources */ 553 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 554 clear_bit(offset, &pc->enabled_irq_map[bank]); 555 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 556 557 gpiochip_disable_irq(chip, gpio); 558 } 559 560 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc, 561 unsigned offset, unsigned int type) 562 { 563 switch (type) { 564 case IRQ_TYPE_NONE: 565 case IRQ_TYPE_EDGE_RISING: 566 case IRQ_TYPE_EDGE_FALLING: 567 case IRQ_TYPE_EDGE_BOTH: 568 case IRQ_TYPE_LEVEL_HIGH: 569 case IRQ_TYPE_LEVEL_LOW: 570 pc->irq_type[offset] = type; 571 break; 572 573 default: 574 return -EINVAL; 575 } 576 return 0; 577 } 578 579 /* slower path for reconfiguring IRQ type */ 580 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc, 581 unsigned offset, unsigned int type) 582 { 583 switch (type) { 584 case IRQ_TYPE_NONE: 585 if (pc->irq_type[offset] != type) { 586 bcm2835_gpio_irq_config(pc, offset, false); 587 pc->irq_type[offset] = type; 588 } 589 break; 590 591 case IRQ_TYPE_EDGE_RISING: 592 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 593 /* RISING already enabled, disable FALLING */ 594 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 595 bcm2835_gpio_irq_config(pc, offset, false); 596 pc->irq_type[offset] = type; 597 } else if (pc->irq_type[offset] != type) { 598 bcm2835_gpio_irq_config(pc, offset, false); 599 pc->irq_type[offset] = type; 600 bcm2835_gpio_irq_config(pc, offset, true); 601 } 602 break; 603 604 case IRQ_TYPE_EDGE_FALLING: 605 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 606 /* FALLING already enabled, disable RISING */ 607 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 608 bcm2835_gpio_irq_config(pc, offset, false); 609 pc->irq_type[offset] = type; 610 } else if (pc->irq_type[offset] != type) { 611 bcm2835_gpio_irq_config(pc, offset, false); 612 pc->irq_type[offset] = type; 613 bcm2835_gpio_irq_config(pc, offset, true); 614 } 615 break; 616 617 case IRQ_TYPE_EDGE_BOTH: 618 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) { 619 /* RISING already enabled, enable FALLING too */ 620 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 621 bcm2835_gpio_irq_config(pc, offset, true); 622 pc->irq_type[offset] = type; 623 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) { 624 /* FALLING already enabled, enable RISING too */ 625 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 626 bcm2835_gpio_irq_config(pc, offset, true); 627 pc->irq_type[offset] = type; 628 } else if (pc->irq_type[offset] != type) { 629 bcm2835_gpio_irq_config(pc, offset, false); 630 pc->irq_type[offset] = type; 631 bcm2835_gpio_irq_config(pc, offset, true); 632 } 633 break; 634 635 case IRQ_TYPE_LEVEL_HIGH: 636 case IRQ_TYPE_LEVEL_LOW: 637 if (pc->irq_type[offset] != type) { 638 bcm2835_gpio_irq_config(pc, offset, false); 639 pc->irq_type[offset] = type; 640 bcm2835_gpio_irq_config(pc, offset, true); 641 } 642 break; 643 644 default: 645 return -EINVAL; 646 } 647 return 0; 648 } 649 650 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) 651 { 652 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 653 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 654 unsigned gpio = irqd_to_hwirq(data); 655 unsigned offset = GPIO_REG_SHIFT(gpio); 656 unsigned bank = GPIO_REG_OFFSET(gpio); 657 unsigned long flags; 658 int ret; 659 660 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); 661 662 if (test_bit(offset, &pc->enabled_irq_map[bank])) 663 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type); 664 else 665 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type); 666 667 if (type & IRQ_TYPE_EDGE_BOTH) 668 irq_set_handler_locked(data, handle_edge_irq); 669 else 670 irq_set_handler_locked(data, handle_level_irq); 671 672 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 673 674 return ret; 675 } 676 677 static void bcm2835_gpio_irq_ack(struct irq_data *data) 678 { 679 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 680 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 681 unsigned gpio = irqd_to_hwirq(data); 682 683 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 684 } 685 686 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on) 687 { 688 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 689 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 690 unsigned gpio = irqd_to_hwirq(data); 691 unsigned int irqgroup; 692 int ret = -EINVAL; 693 694 if (!pc->wake_irq) 695 return ret; 696 697 if (gpio <= 27) 698 irqgroup = 0; 699 else if (gpio >= 28 && gpio <= 45) 700 irqgroup = 1; 701 else if (gpio >= 46 && gpio <= 57) 702 irqgroup = 2; 703 else 704 return ret; 705 706 if (on) 707 ret = enable_irq_wake(pc->wake_irq[irqgroup]); 708 else 709 ret = disable_irq_wake(pc->wake_irq[irqgroup]); 710 711 return ret; 712 } 713 714 static const struct irq_chip bcm2835_gpio_irq_chip = { 715 .name = MODULE_NAME, 716 .irq_set_type = bcm2835_gpio_irq_set_type, 717 .irq_ack = bcm2835_gpio_irq_ack, 718 .irq_mask = bcm2835_gpio_irq_mask, 719 .irq_unmask = bcm2835_gpio_irq_unmask, 720 .irq_set_wake = bcm2835_gpio_irq_set_wake, 721 .flags = (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE), 722 GPIOCHIP_IRQ_RESOURCE_HELPERS, 723 }; 724 725 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev) 726 { 727 return BCM2835_NUM_GPIOS; 728 } 729 730 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev, 731 unsigned selector) 732 { 733 return bcm2835_gpio_groups[selector]; 734 } 735 736 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev, 737 unsigned selector, 738 const unsigned **pins, 739 unsigned *num_pins) 740 { 741 *pins = &bcm2835_gpio_pins[selector].number; 742 *num_pins = 1; 743 744 return 0; 745 } 746 747 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, 748 struct seq_file *s, 749 unsigned offset) 750 { 751 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 752 struct gpio_chip *chip = &pc->gpio_chip; 753 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 754 const char *fname = bcm2835_functions[fsel]; 755 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset); 756 int irq = irq_find_mapping(chip->irq.domain, offset); 757 758 seq_printf(s, "function %s in %s; irq %d (%s)", 759 fname, str_hi_lo(value), 760 irq, irq_type_names[pc->irq_type[offset]]); 761 } 762 763 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev, 764 struct pinctrl_map *maps, unsigned num_maps) 765 { 766 int i; 767 768 for (i = 0; i < num_maps; i++) 769 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 770 kfree(maps[i].data.configs.configs); 771 772 kfree(maps); 773 } 774 775 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc, 776 struct device_node *np, u32 pin, u32 fnum, 777 struct pinctrl_map **maps) 778 { 779 struct pinctrl_map *map = *maps; 780 781 if (fnum >= ARRAY_SIZE(bcm2835_functions)) { 782 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum); 783 return -EINVAL; 784 } 785 786 map->type = PIN_MAP_TYPE_MUX_GROUP; 787 map->data.mux.group = bcm2835_gpio_groups[pin]; 788 map->data.mux.function = bcm2835_functions[fnum]; 789 (*maps)++; 790 791 return 0; 792 } 793 794 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc, 795 struct device_node *np, u32 pin, u32 pull, 796 struct pinctrl_map **maps) 797 { 798 struct pinctrl_map *map = *maps; 799 unsigned long *configs; 800 801 if (pull > 2) { 802 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull); 803 return -EINVAL; 804 } 805 806 configs = kzalloc_obj(*configs); 807 if (!configs) 808 return -ENOMEM; 809 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull); 810 811 map->type = PIN_MAP_TYPE_CONFIGS_PIN; 812 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name; 813 map->data.configs.configs = configs; 814 map->data.configs.num_configs = 1; 815 (*maps)++; 816 817 return 0; 818 } 819 820 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 821 struct device_node *np, 822 struct pinctrl_map **map, unsigned int *num_maps) 823 { 824 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 825 struct property *pins, *funcs, *pulls; 826 int num_pins, num_funcs, num_pulls, maps_per_pin; 827 struct pinctrl_map *maps, *cur_map; 828 int i, err; 829 u32 pin, func, pull; 830 831 /* Check for generic binding in this node */ 832 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps); 833 if (err || *num_maps) 834 return err; 835 836 /* Generic binding did not find anything continue with legacy parse */ 837 pins = of_find_property(np, "brcm,pins", NULL); 838 if (!pins) { 839 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np); 840 return -EINVAL; 841 } 842 843 funcs = of_find_property(np, "brcm,function", NULL); 844 pulls = of_find_property(np, "brcm,pull", NULL); 845 846 if (!funcs && !pulls) { 847 dev_err(pc->dev, 848 "%pOF: neither brcm,function nor brcm,pull specified\n", 849 np); 850 return -EINVAL; 851 } 852 853 num_pins = pins->length / 4; 854 num_funcs = funcs ? (funcs->length / 4) : 0; 855 num_pulls = pulls ? (pulls->length / 4) : 0; 856 857 if (num_funcs > 1 && num_funcs != num_pins) { 858 dev_err(pc->dev, 859 "%pOF: brcm,function must have 1 or %d entries\n", 860 np, num_pins); 861 return -EINVAL; 862 } 863 864 if (num_pulls > 1 && num_pulls != num_pins) { 865 dev_err(pc->dev, 866 "%pOF: brcm,pull must have 1 or %d entries\n", 867 np, num_pins); 868 return -EINVAL; 869 } 870 871 maps_per_pin = 0; 872 if (num_funcs) 873 maps_per_pin++; 874 if (num_pulls) 875 maps_per_pin++; 876 cur_map = maps = kzalloc_objs(*maps, num_pins * maps_per_pin); 877 if (!maps) 878 return -ENOMEM; 879 880 for (i = 0; i < num_pins; i++) { 881 err = of_property_read_u32_index(np, "brcm,pins", i, &pin); 882 if (err) 883 goto out; 884 if (pin >= pc->pctl_desc.npins) { 885 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n", 886 np, pin); 887 err = -EINVAL; 888 goto out; 889 } 890 891 if (num_funcs) { 892 err = of_property_read_u32_index(np, "brcm,function", 893 (num_funcs > 1) ? i : 0, &func); 894 if (err) 895 goto out; 896 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin, 897 func, &cur_map); 898 if (err) 899 goto out; 900 } 901 if (num_pulls) { 902 err = of_property_read_u32_index(np, "brcm,pull", 903 (num_pulls > 1) ? i : 0, &pull); 904 if (err) 905 goto out; 906 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin, 907 pull, &cur_map); 908 if (err) 909 goto out; 910 } 911 } 912 913 *map = maps; 914 *num_maps = num_pins * maps_per_pin; 915 916 return 0; 917 918 out: 919 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin); 920 return err; 921 } 922 923 static const struct pinctrl_ops bcm2835_pctl_ops = { 924 .get_groups_count = bcm2835_pctl_get_groups_count, 925 .get_group_name = bcm2835_pctl_get_group_name, 926 .get_group_pins = bcm2835_pctl_get_group_pins, 927 .pin_dbg_show = bcm2835_pctl_pin_dbg_show, 928 .dt_node_to_map = bcm2835_pctl_dt_node_to_map, 929 .dt_free_map = bcm2835_pctl_dt_free_map, 930 }; 931 932 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev, 933 unsigned offset) 934 { 935 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 936 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 937 938 if (fsel == BCM2835_FSEL_GPIO_IN) 939 return 0; 940 941 if (persist_gpio_outputs && fsel == BCM2835_FSEL_GPIO_OUT) 942 return 0; 943 944 /* disable by setting to GPIO_IN */ 945 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); 946 return 0; 947 } 948 949 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev) 950 { 951 return BCM2835_FSEL_COUNT; 952 } 953 954 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev, 955 unsigned selector) 956 { 957 return bcm2835_functions[selector]; 958 } 959 960 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev, 961 unsigned selector, 962 const char * const **groups, 963 unsigned * const num_groups) 964 { 965 /* every pin can do every function */ 966 *groups = bcm2835_gpio_groups; 967 *num_groups = BCM2835_NUM_GPIOS; 968 969 return 0; 970 } 971 972 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev, 973 unsigned func_selector, 974 unsigned group_selector) 975 { 976 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 977 978 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector); 979 980 return 0; 981 } 982 983 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 984 struct pinctrl_gpio_range *range, 985 unsigned offset) 986 { 987 bcm2835_pmx_free(pctldev, offset); 988 } 989 990 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 991 struct pinctrl_gpio_range *range, 992 unsigned offset, 993 bool input) 994 { 995 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 996 enum bcm2835_fsel fsel = input ? 997 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT; 998 999 bcm2835_pinctrl_fsel_set(pc, offset, fsel); 1000 1001 return 0; 1002 } 1003 1004 static const struct pinmux_ops bcm2835_pmx_ops = { 1005 .free = bcm2835_pmx_free, 1006 .get_functions_count = bcm2835_pmx_get_functions_count, 1007 .get_function_name = bcm2835_pmx_get_function_name, 1008 .get_function_groups = bcm2835_pmx_get_function_groups, 1009 .set_mux = bcm2835_pmx_set, 1010 .gpio_disable_free = bcm2835_pmx_gpio_disable_free, 1011 .gpio_set_direction = bcm2835_pmx_gpio_set_direction, 1012 }; 1013 1014 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev, 1015 unsigned pin, unsigned long *config) 1016 { 1017 enum pin_config_param param = pinconf_to_config_param(*config); 1018 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 1019 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, pin); 1020 u32 val; 1021 1022 /* No way to read back bias config in HW */ 1023 1024 switch (param) { 1025 case PIN_CONFIG_LEVEL: 1026 if (fsel != BCM2835_FSEL_GPIO_OUT) 1027 return -EINVAL; 1028 1029 val = bcm2835_gpio_get_bit(pc, GPLEV0, pin); 1030 *config = pinconf_to_config_packed(param, val); 1031 break; 1032 1033 default: 1034 return -ENOTSUPP; 1035 } 1036 1037 return 0; 1038 } 1039 1040 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc, 1041 unsigned int pin, unsigned int arg) 1042 { 1043 u32 off, bit; 1044 1045 off = GPIO_REG_OFFSET(pin); 1046 bit = GPIO_REG_SHIFT(pin); 1047 1048 bcm2835_gpio_wr(pc, GPPUD, arg & 3); 1049 /* 1050 * BCM2835 datasheet say to wait 150 cycles, but not of what. 1051 * But the VideoCore firmware delay for this operation 1052 * based nearly on the same amount of VPU cycles and this clock 1053 * runs at 250 MHz. 1054 */ 1055 udelay(1); 1056 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); 1057 udelay(1); 1058 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); 1059 } 1060 1061 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, 1062 unsigned int pin, unsigned long *configs, 1063 unsigned int num_configs) 1064 { 1065 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 1066 u32 param, arg; 1067 int i; 1068 1069 for (i = 0; i < num_configs; i++) { 1070 param = pinconf_to_config_param(configs[i]); 1071 arg = pinconf_to_config_argument(configs[i]); 1072 1073 switch (param) { 1074 /* Set legacy brcm,pull */ 1075 case BCM2835_PINCONF_PARAM_PULL: 1076 bcm2835_pull_config_set(pc, pin, arg); 1077 break; 1078 1079 /* Set pull generic bindings */ 1080 case PIN_CONFIG_BIAS_DISABLE: 1081 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF); 1082 break; 1083 1084 case PIN_CONFIG_BIAS_PULL_DOWN: 1085 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN); 1086 break; 1087 1088 case PIN_CONFIG_BIAS_PULL_UP: 1089 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP); 1090 break; 1091 1092 /* Set output-high or output-low */ 1093 case PIN_CONFIG_LEVEL: 1094 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin); 1095 break; 1096 1097 default: 1098 return -ENOTSUPP; 1099 1100 } /* switch param type */ 1101 } /* for each config */ 1102 1103 return 0; 1104 } 1105 1106 static const struct pinconf_ops bcm2835_pinconf_ops = { 1107 .is_generic = true, 1108 .pin_config_get = bcm2835_pinconf_get, 1109 .pin_config_set = bcm2835_pinconf_set, 1110 }; 1111 1112 static int bcm2711_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, 1113 unsigned long *config) 1114 { 1115 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 1116 enum pin_config_param param = pinconf_to_config_param(*config); 1117 u32 offset, shift, val; 1118 1119 offset = PUD_2711_REG_OFFSET(pin); 1120 shift = PUD_2711_REG_SHIFT(pin); 1121 val = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (offset * 4)); 1122 1123 switch (param) { 1124 case PIN_CONFIG_BIAS_DISABLE: 1125 if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_NONE) 1126 return -EINVAL; 1127 1128 break; 1129 1130 case PIN_CONFIG_BIAS_PULL_UP: 1131 if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_UP) 1132 return -EINVAL; 1133 1134 *config = pinconf_to_config_packed(param, 50000); 1135 break; 1136 1137 case PIN_CONFIG_BIAS_PULL_DOWN: 1138 if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_DOWN) 1139 return -EINVAL; 1140 1141 *config = pinconf_to_config_packed(param, 50000); 1142 break; 1143 1144 default: 1145 return bcm2835_pinconf_get(pctldev, pin, config); 1146 } 1147 1148 return 0; 1149 } 1150 1151 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc, 1152 unsigned int pin, unsigned int arg) 1153 { 1154 u32 shifter; 1155 u32 value; 1156 u32 off; 1157 1158 off = PUD_2711_REG_OFFSET(pin); 1159 shifter = PUD_2711_REG_SHIFT(pin); 1160 1161 value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4)); 1162 value &= ~(PUD_2711_MASK << shifter); 1163 value |= (arg << shifter); 1164 bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value); 1165 } 1166 1167 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev, 1168 unsigned int pin, unsigned long *configs, 1169 unsigned int num_configs) 1170 { 1171 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 1172 u32 param, arg; 1173 int i; 1174 1175 for (i = 0; i < num_configs; i++) { 1176 param = pinconf_to_config_param(configs[i]); 1177 arg = pinconf_to_config_argument(configs[i]); 1178 1179 switch (param) { 1180 /* convert legacy brcm,pull */ 1181 case BCM2835_PINCONF_PARAM_PULL: 1182 if (arg == BCM2835_PUD_UP) 1183 arg = BCM2711_PULL_UP; 1184 else if (arg == BCM2835_PUD_DOWN) 1185 arg = BCM2711_PULL_DOWN; 1186 else 1187 arg = BCM2711_PULL_NONE; 1188 1189 bcm2711_pull_config_set(pc, pin, arg); 1190 break; 1191 1192 /* Set pull generic bindings */ 1193 case PIN_CONFIG_BIAS_DISABLE: 1194 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE); 1195 break; 1196 case PIN_CONFIG_BIAS_PULL_DOWN: 1197 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN); 1198 break; 1199 case PIN_CONFIG_BIAS_PULL_UP: 1200 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP); 1201 break; 1202 1203 /* Set output-high or output-low */ 1204 case PIN_CONFIG_LEVEL: 1205 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin); 1206 break; 1207 1208 default: 1209 return -ENOTSUPP; 1210 } 1211 } /* for each config */ 1212 1213 return 0; 1214 } 1215 1216 static const struct pinconf_ops bcm2711_pinconf_ops = { 1217 .is_generic = true, 1218 .pin_config_get = bcm2711_pinconf_get, 1219 .pin_config_set = bcm2711_pinconf_set, 1220 }; 1221 1222 static const struct pinctrl_desc bcm2835_pinctrl_desc = { 1223 .name = MODULE_NAME, 1224 .pins = bcm2835_gpio_pins, 1225 .npins = BCM2835_NUM_GPIOS, 1226 .pctlops = &bcm2835_pctl_ops, 1227 .pmxops = &bcm2835_pmx_ops, 1228 .confops = &bcm2835_pinconf_ops, 1229 .owner = THIS_MODULE, 1230 }; 1231 1232 static const struct pinctrl_desc bcm2711_pinctrl_desc = { 1233 .name = "pinctrl-bcm2711", 1234 .pins = bcm2835_gpio_pins, 1235 .npins = BCM2711_NUM_GPIOS, 1236 .pctlops = &bcm2835_pctl_ops, 1237 .pmxops = &bcm2835_pmx_ops, 1238 .confops = &bcm2711_pinconf_ops, 1239 .owner = THIS_MODULE, 1240 }; 1241 1242 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = { 1243 .name = MODULE_NAME, 1244 .npins = BCM2835_NUM_GPIOS, 1245 }; 1246 1247 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = { 1248 .name = "pinctrl-bcm2711", 1249 .npins = BCM2711_NUM_GPIOS, 1250 }; 1251 1252 struct bcm_plat_data { 1253 const struct gpio_chip *gpio_chip; 1254 const struct pinctrl_desc *pctl_desc; 1255 const struct pinctrl_gpio_range *gpio_range; 1256 }; 1257 1258 static const struct bcm_plat_data bcm2835_plat_data = { 1259 .gpio_chip = &bcm2835_gpio_chip, 1260 .pctl_desc = &bcm2835_pinctrl_desc, 1261 .gpio_range = &bcm2835_pinctrl_gpio_range, 1262 }; 1263 1264 static const struct bcm_plat_data bcm2711_plat_data = { 1265 .gpio_chip = &bcm2711_gpio_chip, 1266 .pctl_desc = &bcm2711_pinctrl_desc, 1267 .gpio_range = &bcm2711_pinctrl_gpio_range, 1268 }; 1269 1270 static const struct of_device_id bcm2835_pinctrl_match[] = { 1271 { 1272 .compatible = "brcm,bcm2835-gpio", 1273 .data = &bcm2835_plat_data, 1274 }, 1275 { 1276 .compatible = "brcm,bcm2711-gpio", 1277 .data = &bcm2711_plat_data, 1278 }, 1279 { 1280 .compatible = "brcm,bcm7211-gpio", 1281 .data = &bcm2711_plat_data, 1282 }, 1283 {} 1284 }; 1285 MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match); 1286 1287 static int bcm2835_pinctrl_probe(struct platform_device *pdev) 1288 { 1289 struct device *dev = &pdev->dev; 1290 struct device_node *np = dev->of_node; 1291 const struct bcm_plat_data *pdata; 1292 struct bcm2835_pinctrl *pc; 1293 struct gpio_irq_chip *girq; 1294 struct resource iomem; 1295 int err, i; 1296 const struct of_device_id *match; 1297 int is_7211 = 0; 1298 1299 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS); 1300 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS); 1301 1302 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); 1303 if (!pc) 1304 return -ENOMEM; 1305 1306 platform_set_drvdata(pdev, pc); 1307 pc->dev = dev; 1308 1309 err = of_address_to_resource(np, 0, &iomem); 1310 if (err) { 1311 dev_err(dev, "could not get IO memory\n"); 1312 return err; 1313 } 1314 1315 pc->base = devm_ioremap_resource(dev, &iomem); 1316 if (IS_ERR(pc->base)) 1317 return PTR_ERR(pc->base); 1318 1319 match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node); 1320 if (!match) 1321 return -EINVAL; 1322 1323 pdata = match->data; 1324 is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio"); 1325 1326 pc->gpio_chip = *pdata->gpio_chip; 1327 pc->gpio_chip.parent = dev; 1328 1329 spin_lock_init(&pc->fsel_lock); 1330 for (i = 0; i < BCM2835_NUM_BANKS; i++) { 1331 unsigned long events; 1332 unsigned offset; 1333 1334 /* clear event detection flags */ 1335 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); 1336 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0); 1337 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0); 1338 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0); 1339 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0); 1340 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0); 1341 1342 /* clear all the events */ 1343 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4); 1344 for_each_set_bit(offset, &events, 32) 1345 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); 1346 1347 raw_spin_lock_init(&pc->irq_lock[i]); 1348 } 1349 1350 pc->pctl_desc = *pdata->pctl_desc; 1351 pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc); 1352 if (IS_ERR(pc->pctl_dev)) { 1353 gpiochip_remove(&pc->gpio_chip); 1354 return PTR_ERR(pc->pctl_dev); 1355 } 1356 1357 pc->gpio_range = *pdata->gpio_range; 1358 pc->gpio_range.base = pc->gpio_chip.base; 1359 pc->gpio_range.gc = &pc->gpio_chip; 1360 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range); 1361 1362 girq = &pc->gpio_chip.irq; 1363 gpio_irq_chip_set_chip(girq, &bcm2835_gpio_irq_chip); 1364 girq->parent_handler = bcm2835_gpio_irq_handler; 1365 girq->num_parents = BCM2835_NUM_IRQS; 1366 girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS, 1367 sizeof(*girq->parents), 1368 GFP_KERNEL); 1369 if (!girq->parents) { 1370 err = -ENOMEM; 1371 goto out_remove; 1372 } 1373 1374 if (is_7211) { 1375 pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS, 1376 sizeof(*pc->wake_irq), 1377 GFP_KERNEL); 1378 if (!pc->wake_irq) { 1379 err = -ENOMEM; 1380 goto out_remove; 1381 } 1382 } 1383 1384 /* 1385 * Use the same handler for all groups: this is necessary 1386 * since we use one gpiochip to cover all lines - the 1387 * irq handler then needs to figure out which group and 1388 * bank that was firing the IRQ and look up the per-group 1389 * and bank data. 1390 */ 1391 for (i = 0; i < BCM2835_NUM_IRQS; i++) { 1392 int len; 1393 char *name; 1394 1395 girq->parents[i] = irq_of_parse_and_map(np, i); 1396 if (!is_7211) { 1397 if (!girq->parents[i]) { 1398 girq->num_parents = i; 1399 break; 1400 } 1401 continue; 1402 } 1403 /* Skip over the all banks interrupts */ 1404 pc->wake_irq[i] = irq_of_parse_and_map(np, i + 1405 BCM2835_NUM_IRQS + 1); 1406 1407 len = strlen(dev_name(pc->dev)) + 16; 1408 name = devm_kzalloc(pc->dev, len, GFP_KERNEL); 1409 if (!name) { 1410 err = -ENOMEM; 1411 goto out_remove; 1412 } 1413 1414 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i); 1415 1416 /* These are optional interrupts */ 1417 err = devm_request_irq(dev, pc->wake_irq[i], 1418 bcm2835_gpio_wake_irq_handler, 1419 IRQF_SHARED, name, pc); 1420 if (err) 1421 dev_warn(dev, "unable to request wake IRQ %d\n", 1422 pc->wake_irq[i]); 1423 } 1424 1425 girq->default_type = IRQ_TYPE_NONE; 1426 girq->handler = handle_level_irq; 1427 1428 err = gpiochip_add_data(&pc->gpio_chip, pc); 1429 if (err) { 1430 dev_err(dev, "could not add GPIO chip\n"); 1431 goto out_remove; 1432 } 1433 1434 dev_info(dev, "GPIO_OUT persistence: %s\n", 1435 str_yes_no(persist_gpio_outputs)); 1436 1437 return 0; 1438 1439 out_remove: 1440 pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range); 1441 return err; 1442 } 1443 1444 static struct platform_driver bcm2835_pinctrl_driver = { 1445 .probe = bcm2835_pinctrl_probe, 1446 .driver = { 1447 .name = MODULE_NAME, 1448 .of_match_table = bcm2835_pinctrl_match, 1449 .suppress_bind_attrs = true, 1450 }, 1451 }; 1452 module_platform_driver(bcm2835_pinctrl_driver); 1453 1454 MODULE_AUTHOR("Chris Boot"); 1455 MODULE_AUTHOR("Simon Arlott"); 1456 MODULE_AUTHOR("Stephen Warren"); 1457 MODULE_DESCRIPTION("Broadcom BCM2835/2711 pinctrl and GPIO driver"); 1458 MODULE_LICENSE("GPL"); 1459